NCP51705MNTXG - ON SEMICONDUCTOR

April, 2019 − Rev. 3

1Publication Order Number:

NCP51705/D

NCP51705

Single 6 A High-Speed,

Low-Side SiC MOSFET

Driver

The NCP51705 driver is designed to primarily drive SiC MOSFET

transistors. To achieve the lowest possible conduction losses, the

driver is capable to deliver the maximum allowable gate voltage to the

SiC MOSFET device. By providing high peak current during turn−on

and turn−off, switching losses are also minimized. For improved

reliability, dV/dt immunity and even faster turn−off, the NCP51705

can utilize its on−board charge pump to generate a user selectable

negative voltage rail.

For full compatibility and to minimize the complexity of the bias

solution in isolated gate drive applications the NCP51705 also

provides an externally accessible 5 V rail to power the secondary side

of digital or high speed opto isolators.

The NCP51705 offers important protection functions such as

under−voltage lockout monitoring for the bias power and thermal

shutdown based on the junction temperature of the driver circuit.

Features

•High Peak Output Current with Split Output Stages to allow

independent Turn−ON/Turn−OFF Adjustment;

♦Source Capability: 6 A

♦Sink Capability: 6 A

•Extended Positive Voltage Rating for Efficient SiC MOSFET

Operation during the Conduction Period

•User−adjustable Built−in Negative Charge Pump for Fast Turn−off

and Robust dV/dt Immunity

•Accessible 5 V Reference / Bias Rail for Digital Oscillator Supply

•Adjustable Under−Voltage Lockout

•Desaturation Function

•Thermal Shutdown Function (TSD)

•Small & Low Parasitic Inductance QFN24 Package

Typical Applications

•Driving SiC MOSFET

•Industrial Inverters, Motor Drivers

•PFC, AC to DC and DC to DC Converters

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MARKING

DIAGRAM

Device Package Shipping†

ORDERING INFORMATION

NCP51705MNTXG QFN24

(Pb−Free)

3000 / Tape & Reel

QFN24 4x4

MN SUFFIX

CASE 485L

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

PIN CONNECTIONS

NCP51705

(Top View )

PGND

VCH

C+

PGND

VEE

OUTSNK

OUTSRC

UVSET

V5V

SVDD

VDD

OUTSRC

PGND

OUTSNK

VEE VDD

SGND

C−

DESAT

VEESET

XEN

IN+

IN−

Z = Plant Code

X= 1−Digit Year Code

Y= 1−Digit Week Code

TT = 2−Digit Die Run Code

MP = Package Type (QFN)

X = Package Type (Tape & Reel)

ZXYTT

P51705

MPX

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Figure 1. Typical Application Schematics

(a) Low Side Switching Configuration

(b) Half Bridge Switching Configuration

Digital Controller

Isolation

Boundary

ENABLE

PWM_HS

XEN_HS

PWM_LS

XEN_LS

FAULT_HS

FAULT_LS

Digital

Isolators

ISOLATOR BIAS

CONTROLLER BIAS(3.3 V or 5 V) 20 V BIAS (isolated)

20 V BIAS (isolated)

NCP51705

(Top View)

PGND

IN+

IN−

XEN

VCH

C+

PGND

VEE

OUTSNK

OUTSRC

UVSET

V5V

DESAT

VDD

OUTSRC

PGND

OUTSNK

VEE VDD

SGND

C−

SVDD

VEESET

Controller

20 V

Note: Make single point connection

From SGND to PGND on PCB.

VEESET = SGND ³OFF

VEESET = OPEN ³−3.4 V

VEESET = V5V ³−5 V

VEESET = SVDD ³−8 V

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Figure 2. Internal Block Diagram

IN+

IN−

SGND

OUTSRC

OUTSNK

PGND

VDD

VEESET

VCH

C+

C−

VEE

UVSET

V5V

UVLO

PROTECTION

LOGIC

TSD

CHARGE

PUMP

REG CHARGE PUMP

POWER STAGE

DRIVER

LOGIC

LEVEL

SHIFT

VDD_OK

VEE_OK

CPCLK

RUN

5V REG

16 PGND

OUTSNK

OUTSRC

VDD

SVDD

XEN

VEE

11 12 9 10

PGND

22 DESAT/CS

5V_OK

INPUT LOGIC

DESAT /

CURRENT

SENSE

25 mA

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PIN CONNECTIONS

NCP51705

(Top View)

PGND

VCH

C+

PGND

VEE

OUTSNK

OUTSRC

UVSET

V5V

SVDD

VDD

OUTSRC

PGND

OUTSNK

VEE VDD

SGND

C−

DESAT

VEESET

XEN

IN+

IN−

Figure 3. Pin Assignments – 24 Leads QFN (Top View)

PIN FUNCTION DESCRIPTION

Pin # Name Description

1 IN+ Input for non−inverting, logic level PWM signal or ENABLE signal.

2IN−Input for inverting, logic level PWM signal or DISABLE signal.

3 XEN Driver state flag. See the application description for details.

4 SGND Signal ground.

5 VEESET Negative bias voltage select pin.

6 VCH Regulated bias voltage for the charge pump.

7 C+ Positive node of the flying charge pump capacitor.

8 C−Negative node of the flying charge pump capacitor.

9,10,15,16 PGND Power ground.

11,12 VEE Negative drive voltage, the output of the charge pump

13,14 OUTSNK Pull down drive.

17,18 OUTSRC Pull up drive.

19,20 VDD Positive bias voltage for the high current driver section.

21 SVDD Positive bias voltage for the control section of the driver.

22 DESAT Sense input for the desaturation / current limit input of the driver.

23 V5V External bypass for 5 V controller bias – suitable to power digital isolators

24 UVSET Input for setting the Under voltage lock out threshold. (minimum operating voltage level)

OUTPUT LOGIC

IN+ IN−OUTSRC

0 (Note 1) 0 0

0 (Note 1) 1 (Note 1) 0

1 0 1

11 (Note 1) 0

1. Default input signal if no external connection is made.

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ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min. Max. Unit

VDD Power Supply Voltage −0.3 28 V

VV5V Bias Rail −0.3 5.5 V

VCH Charge Pump Supply Voltage −0.3 10 V

VEE Charge Pump Output; Negative Gate Drive Voltage −9+0.3 V

VVEESET Charge Pump Output Voltage Select −0.3 28 V

VIN+; VIN-Logic Input Voltage Levels −0.3 V5V+0.3 V

VUVSET UVLO SET Voltage −0.3 V5V+0.3 V

VXEN Logic Output Voltage Levels −0.3 V5V+0.3 V

VDESAT Desaturation / Current sense voltage −0.3 12 V

VC+ Positive node of the flying charge pump capacitor −0.3 VCH+0.3 V

VC−Negative node of the flying charge pump capacitor +0.3 VEE -0.3 V

VOUTSRC Gate Drive Source Output Voltage VEE -0.3 VDD +0.3 V

VOUTSNK Gate Drive Sink Output Voltage VEE -0.3 VDD +0.3 V

fMAX Maximum Operating Frequency (Note 2) 500 kHz

TJJunction Temperature −55 150 °C

TSTG Storage Temperature −55 150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. Maximum operating frequency refers to ground reference applications and might be limited by power dissipation below the recommended

value.

THERMAL CHARACTERISTICS

Parameters Symbol Value Unit

Thermal Characteristics, QFN 4x4 24 Leads

Thermal Resistance Junction−Air (Notes 3 & 4)

1S0P with thermal vias

qJA

127

°C/W

1S2P with thermal vias 43

1S0P with thermal vias

Yjt

1S2P with thermal vias 3.7

Power Dissipation (Note 4)

1S0P with thermal vias

0.98

1S2P with thermal vias 2.9

3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

4. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2×114.3×1.6mm PCB (FR−4 glass epoxy material).

1S0P with thermal vias: one signal layer with zero power plane and thermal vias

1S2P with thermal vias: one signal layer with two power plane and thermal vias.

ESD CAPABILITY

Symbol Parameter Value Unit

ESD Human Body Model, JESD22−A114 (Note 5) 2000 V

ESD Charged Device Model, JESD22−C101 (Note 5) 1000 V

5. Meets JEDEC standards JESD 22−A114 and JESD 22−C101.

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RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Max. Unit

VDD Positive Power Supply Voltage 10 22 V

VEE Negative Power Supply Voltage −8 0 V

VCH Charge Pump Power Supply Voltage 0 8 V

VV5V 5 V internal/external bias output 0 5.5 V

VENA Logic Enable Voltage 0 5.5 V

VIN Logic Input Voltage 0 5.5 V

VXEN Logic Output Voltage 0 5.5 V

VVEESET Charge Pump Output Voltage Setting 0 22 V

VUVSET UVLO Threshold Setting 2 3.5 V

VDESAT Desaturation Voltage 0 10 V

fSW Operating Frequency (Note 6) 500 kHz

TAOperating Ambient Temperature −40 125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

6. Maximum operating frequency refers to ground referenced applications and might be limited by power dissipation below the recommended

value.

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ELECTRICAL CHARACTERISTICS (VDD=20 V, VEESET= 0 V and CLOAD = 1000 pF for typical values TA=25°C, for min/max values

TJ=TA=−40°C to +125°C, unless otherwise specified.) (Notes 7, 8)

Symbol Parameters Test Conditions Min. Typ. Max. Units

VDD Section

IDD Operating VDD Supply Current fIN = 100 kHz, VEESET = 5 V 12 18 mA

IQDD1 Quiescent VDD Supply Current 1 VIN+ = VIN− = 0 V, VEESET = 5 V 4.5 6.5 mA

IQDD2 Quiescent VDD Supply Current 2 VIN+ = 0 V, VIN− = 5 V 0.85 1 mA

IUVSET Source Current for UV Voltage Set VUVSET = 3 V 22 25 28 mA

VDDUV+

VDD Supply Under−Voltage

Positive−going Threshold Voltage VUVSET = 3 V 17 18 19 V

VDDUV−

VDD Supply Under−Voltage

Negative−going Threshold Voltage VUVSET = 3 V 16 17 18 V

VDDHYS VDD Supply UVLO Hysteresis Voltage VDDUV+ − VDDUV−1 V

VUVSET,MIN UVSET pin short protection Threshold Voltage VUVSET rising 1.55 V

VUVSET,HYS UVSET pin short protection Hysteresis 0.2 V

5V Regulator Section

VV5V 5 V Bias (Note 9)

TA = 25°C 4.9 5 5.1 V

Total Variation 4.75 5 5.25 V

VV5V_Reg

5 V Line Regulation 10 V < VDD < 22 V, IOUT = 10 mA 50 mV

5 V Load Regulation 0.1 mA < IOUT < 10 mA 50 mV

I5V_MAX Maximum Output Current (Note 10) for external load 20 25 mA

VEE Regulator Section

IVEESET Input VEESET Bias Current 5mA

VVCH,MAX Maximum VCH Output Voltage (Note 10) 10 V

Charge Pump Section

VEE Negative Bias Rail Voltage

VEESET = 5 V − 5.5 −5−4.5 V

VEESET = open −3.8 −3.4 −3.0 V

VEESET = VDD −8 V

IVEE, MAX Maximum Output Current of VEE CFYL = 0.47 mF, CVEE = 1.5 mF

CLOAD = 8.5 nF, VEESET = 5 V 50 mA

fOSC Oscillator Switching Frequency for Charge Pump 350 390 430 kHz

Desaturation Section

IDESAT DC Source Current VDESAT = 0 V 360 400 440 mA

VTH,DESAT Desaturation Protection Threshold Voltage 7 7.5 8 V

tDEL,DESAT Blanking Time after turn−on 350 500 650 ns

RON,DESAT Active Pull Down Resistance 5 10 W

Thermal Shutdown Section

TSD Thermal ShutDown Temperature (Note 10) 130 150 °C

TSD_HYS TSD Hysteresis (Note 10) 25 °C

7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C.

9. Exclude overshoot voltage at start−up.

10.This parameter, although guaranteed by design, is not tested in production.

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ELECTRICAL CHARACTERISTICS (VDD=20 V, VEESET= 0 V and CLOAD = 1000 pF for typical values TA=25°C, for min/max values

TJ=TA=−40°C to +125°C, unless otherwise specified.) (Notes 7, 8)

Symbol UnitsMax.Typ.Min.Test ConditionsParameters

Input Logic Section; IN+; IN−

VIH High Level Input Voltage 1.6 2.0 V

VIL Low Level Input Voltage 0.8 1.2 V

VINHYS Input Logic Hysteresis 0.4 V

IIN+ High Level Logic Input Bias Current VIN+ = 5 V 50 mA

IIN−Low Level Logic Input Bias Current VIN− = 0 V 50 mA

RIN+ Logic Input Pull−Down Resistance 75 100 125 kW

RIN−Logic Input Pull−Up Resistance 75 100 125 kW

Output Logic Section; XEN

VOHX High Level Output Voltage (V5V−VOH) IOUT = 1 mA 0 0.5 V

VOLX Low Level Output Voltage IOUT = 1 mA 0 0.2 V

IXENH High Level Logic Output Source Current (Note 10) 5 mA

IXENL High Level Logic Output Sink Current (Note 10) 5 mA

Gate Driver Output Section

ISOURCE OUTSRC Source Current (Note 10) OUTSRC = 0 V, VEESET = 5 V 6 A

ISINK OUTSNK Sink Current (Note 10) OUTSNK = 20 V, VEESET = 5 V 6 A

VOH High Level Output Voltage (VDD−VOUT) IOUT = 100 mA 0 0.5 V

VOL Low Level Output Voltage IOUT = 100 mA 0 0.2 V

tON Turn−On Propagation Delay Time CLOAD = 1 nF 25 50 ns

tOFF Turn−Off Propagation Delay Time CLOAD = 1 nF 25 50 ns

tRTurn−On Rise Time CLOAD = 1 nF 8 15 ns

tFTurn−Off Fall Time CLOAD = 1 nF 8 15 ns

7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C.

9. Exclude overshoot voltage at start−up.

10.This parameter, although guaranteed by design, is not tested in production.

NCP51705

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TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at 25°C and VDD = 20 V unless otherwise noted.

Figure 4. Operating Current (IDD) vs. Operating

Voltage (VDD)

Figure 5. Operating Current (IDD) vs. Operating

Frequency

Figure 6. Propagation Delay Time vs.

Operating Voltage (VDD)

Figure 7. Sourcing Current vs. Operating Voltage

(VDD)

Figure 8. Sinking Current vs. Operating Voltage

(VDD)

Figure 9. Operating Current (IDD) vs.

Temperature

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TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at 25°C and VDD = 20 V unless otherwise noted.

Figure 10. Quiescent Current 1 (IQDD1) vs.

Temperature

Figure 11. Quiescent Current 2 (IQDD2) vs.

Temperature

Figure 12. VDD UVLO vs. Temperature Figure 13. UVSET vs. Temperature

Figure 14. UVSET Current (IUVSET) vs.

Temperature

Figure 15. 5 V Regulated Output Voltage (V5V)

vs. Temperature

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TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at 25°C and VDD = 20 V unless otherwise noted.

Figure 16. Negative Bias Voltage of Charge

Pump vs. Temperature

Figure 17. VEE5 Regulated Voltage with

IVEE,MAX vs. Temperature

Figure 18. Charge Pump Operating Frequency

(fOSC) vs. Temperature

Figure 19. Desaturation Current (IDESAT) vs.

Temperature

Figure 20. DESAT Threshold Voltage

(VTH

DESAT) vs. Temperature

Figure 21. Desaturation Blanking Time (tDEL,

DESAT) vs. Temperature

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TYPICAL PERFORMANCE CHARACTERISTICS

Typical characteristics are provided at 25°C and VDD = 20 V unless otherwise noted.

Figure 22. DESAT Pull Down Resistance

(RDON,DESAT) vs. Temperature

Figure 23. Input Logic Threshold Voltage vs.

Temperature

Figure 24. Logic Input Resistance vs.

Temperature

Figure 25. XEN Logic Output Voltage vs.

Temperature

Figure 26. Propagation Delay Time vs.

Temperature

Figure 27. Turn On Rising and Turn Off Falling

Time vs. Temperature

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APPLICATIONS INFORMATION

The NCP51705 can be quickly configured by following

the steps outlined in this section. The component references

made throughout this section refer to the schematic diagram

and reference designations shown in Figure 28.

Figure 28. Application Schematic

NCP51705

(Top View)

PGND

IN+

IN−

XEN

VCH

C+

PGND

VEE

OUTSNK

OUTSRC

UVSET

V5V

DESAT

VDD

OUTSRC

PGND

OUTSNK

VEE VDD

SGND

C−

SVDD

VEESET

Controller

20 V

Note: Make single point connection

from SGND to PGND on PCB.

VEESET = SGND ³OFF

VEESET = OPEN ³−3.4 V

VEESET = V5V ³−5 V

VEESET = SVDD ³−8 V

CV5V

RUVSET

CUVSET

CSVDD RSVDD

CVDD1

CVDD2

RDESAT DDESAT

RSRC

RSNK

CFLY

CVCH

CVEE2 CVEE1

Input (IN+, IN−)

Both independent PWM inputs are TTL compatible and

are internally pulled to the correct states such that each

corresponding driver input is defaulted to the inactive

(disabled) state. The TTL input thresholds provide buffer

and level translation functions from logic inputs. The input

thresholds meet industry−standard TTL−logic thresholds,

independent of the VDD voltage, and there is a hysteresis

voltage of approximately 0.4 V. These levels permit the

inputs to be driven from a range of input logic signal levels

for which a voltage over 2 V is considered logic high. The

driving signal for the TTL inputs should have fast rising and

falling edges with a slew rate of 6 V/ms or faster, so a rise

time from 0 to 3.3 V should be 550 ns or less. With reduced

slew rate, circuit noise could cause the driver input voltage

to exceed the hysteresis voltage and retrigger the driver

input, causing erratic operation.

For non−inverting input logic the PWM input signal is

applied to IN+ while the IN− input can be used as an enable

function. If IN− is pulled HIGH, the driver output remains

LOW, regardless of the state of IN+. To enable the driver

output, IN− should be tied to SGND through a 10 kW

resistor, as shown in Figure 29, or can be used as an active

LOW enable pull down. The start−up logic waveforms

shown in Figure 30 illustrate the expected behavior when

applying a PWM input signal to the IN+ input while the IN−

input is pulled LOW to SGND. In this example, the PWM

signal is applied prior to the application of VDD. When

VDD is greater than X7.5 V, the NCP51705 internal charge

pump is enabled and begins switching. The output is only

enabled when VDD is greater than the set UVLO ON level

(VON) and VEE is less than 80% of the programmed voltage

level. The output begins switching corresponding to the next

PWM rising edge after both UVLO thresholds have been

crossed. This method of edge detection, assures the output

accurately represents the PWM input while preventing the

output from possibly switching in the middle of an IN+,

PWM pulse on−time.

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VDD

VEE

IN−

IN+ OUTSRC

OUTSNK

Figure 29. Non−inverting input configuration

Table 1. Non−inverting logic, IN+, truth table

IN+ (PWM) IN− (SGND) OUTSRC OUTSNK

0 0 0 1

1 0 1 0

7.5 V

VDD

VEE

0.8*VEE

VON

IN+

IN−(0 V)

VDD

VEE

(UVLO)

VDD

(UVLO)

VEE

(EN)

OUT

RISING IN+ EDGE

Figure 30. Non−inverting start−up logic

For inverting input logic the PWM input signal is applied

to IN− while the IN+ input can be used as an enable function.

If IN+ is pulled LOW, the driver output remains LOW,

regardless of the state of IN−. To enable the driver output,

IN+ should be tied to V5V (5 V) through a 10 kW resistor,

as shown in Figure 31, or can be used as an active HIGH

enable pull up. The start−up logic waveforms shown in

Figure 32 illustrate the expected behavior when applying a

PWM input signal to the IN− input while the IN+ input is

pulled HIGH to V5V. In this example, the PWM signal is

applied prior to the application of VDD. When VDD is

greater than 7.5 V, the NCP51705 internal charge pump is

enabled and begins switching. The output is only enabled

when VDD is greater than the set UVLO ON level (VON)

and VEE is less than 80% of the programmed voltage level.

The output begins switching corresponding to the next

PWM falling edge after both UVLO thresholds have been

crossed. This method of edge detection, assures the output

accurately represents the PWM input while preventing the

output from possibly switching in the middle of an IN−,

PWM pulse off−time.

VDD

VEE

IN−

IN+ OUTSRC

OUTSNK

V5V

Figure 31. Inverting input configuration

Table 2. Inverting logic, IN−, truth table

IN+ (V5V) IN− (PWM) OUTSRC OUTSNK

1 0 1 0

1 1 0 1

7.5 V

VDD

VEE

0.8*VEE

VON

IN−

VDD

VEE

(UVLO)

VDD

(UVLO)

IN+ (V5V)

VEE

(EN)

OUT

FALLING IN −EDGE

Figure 32. Inverting start−up logic

Driver State Reporting (XEN)

The XEN signal is a 5 V digital output representation of

the output state of the NCP51705 driver. XEN is directly

derived from the output of the driver and should not be

considered as the inverse of the non−inverting logic input to

the driver, IN+. The output of the NCP51705 driver can be

commanded to its OFF state while the input signal is still

HIGH by any of the protection functions of the driver. In

such instances, XEN will accurately represent that the driver

is OFF, independent of the input signal to the device.

The intent of this signal is that it can be used as a fault flag

and in half−bridge power topologies, can provide a

synchronization signal for implementing cross−conduction

(overlap) protection for the power transistors.

Whenever XEN is HIGH, VGS is LOW and the SiC

MOSFET is OFF. Therefore, if XEN and the PWM input

signals are both HIGH, a fault condition is detected and can

be digitally assigned to take whatever precautions might be

desired. XEN can also be used as a control signal for

cross−conduction prevention between a high−side and

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low−side switch used in a half or full−bridge configuration.

The schematic diagram shown in Figure 33 illustrates a

circuit example how to utilize the XEN signals for fault

detection and cross−conduction prevention. As can be seen

in this implementation, the functions are independent and it

is up to the designer to decide whether any one or both

functions are needed to be implemented in the system.

FLT_HS

FLT_LS

PWM_HS

PWM_LS

XEN_HS

XEN_LS

IN+_HS

IN+_LS

FAULT

DETECTION

ANTI CROSS−

CONDUCTION

Figure 33. Examples of XEN signal usage

If XEN_HS transitions from LOW to HIGH while

PWM_HS is HIGH, the PWM pulse width had been

terminated early by one of the protection functions of the

NCP51705. The protection function are; any of the Under

Voltage Lock−Out (UVLO) protections, Thermal Shut

Down (TSD), and Desaturation Detection (DESAT). As

Figure 33 indicates a FAULT signal can be generated by a

simple AND connection of the PWM input signal and the

corresponding XEN output.

In case of cross−conduction prevention, the XEN signal of

one driver is used to enable the operation of the other driver

as depicted in a simplified manner in Figure 33. The

isolation for the high side driver is not shown in the

simplified schematic of Figure 33 but the operation of the

system can be easily followed. While the high−side driver is

ON, XEN_HS is LOW preventing any gate drive to be

applied to the low−side driver. Once the high−side driver

turns OFF its XEN_HS signal transitions to HIGH and the

PWM_LS signal can pass through to the low−side driver. An

identical sequence exists to ensure that the high−side driver

cannot be turned ON until the low−side driver is OFF.

Signal Ground (SGND) and Power Ground (PGND)

Signal ground connection (SGND) is the GND for all

control logic biased from the 5 V rail (V5V). Internally, the

SGND and PGND pins are tied together by two anti−parallel

diodes to limit ground bounce difference due to bond wire

inductances during the switching actions of the high−current

gate drive circuits. It is recommended to connect the SGND

and PGND pins together with a short, low−impedance trace

on the PCB.

PGND is the reference potential (0 V) for the high−current

gate−drive circuit. Two bypass capacitors should be

connected between the VDD pin and the PGND pin. One is

the VDD energy storage capacitor, which provides bias

power during startup until the bootstrap power supply comes

up. The value of the energy storage capacitor is a strong

function of the gate charge requirement of the SiC

MOSFET. It is recommended to use a minimum of 1 mF to

ensure proper operation but the value is primarily dictated

by the biasing scheme and startup time of the system. The

second capacitor shall be a good−quality ceramic bypass

capacitor, located as close as possible to the PGND and

VDD pins to filter the high peak currents of the gate driver

source circuit. A ceramic bypass capacitor in the range of

10 nF to 100 nF is recommended.

Similarly, two bypass capacitors should be connected

between the VEE pin and the PGND pin. One is the VEE

energy storage capacitor, which smoothes the ripple voltage

seen at output of the internal charge pump power stage. It is

recommended to use a minimum of 470 nF to ensure

accurate DC regulation. The second capacitor shall be a

good−quality ceramic bypass capacitor, located as close as

possible to the PGND and VEE pins to filter the high peak

currents of the gate driver sink circuit. A ceramic bypass

capacitor in the range of 10 nF to 100 nF is recommended.

Note that the exposed metal pad beneath the IC is

thermally conductive but electrically not always connected

to GND potential. Do not connect this pad to SGND or

PGND.

Programmable VEE Voltage (VEESET)

VEE is regulated to the voltage set at VCH which is

determined by the internal low dropout regulator (LDO)

voltage, programmable by the VEESET pin. The

NCP51705 offers several convenient pin strapping options

for VEESET. If VEESET is left floating (a 100 pF bypass

capacitor from VEESET to SGND is recommended), then

VEE is set to regulate at −3 V. For a −5 V VEE voltage, the

VEESET pin should be connected directly to V5V (pin 23).

If VEESET is connected to any voltage between 9 V and

VDD, then VEE is clamped and set to regulate at the

minimum charge pump voltage of −8 V. The charge pump

starts when VDD > 7.5 V. Additionally, the VEE voltage rail

includes an internally fixed under−voltage lockout (UVLO)

set to 80% of the programmed VEE value. Since VDD and

VEE are each monitored by independent UVLO circuits, the

NCP51705 is smart enough to realize when both voltage

rails are within limits deemed safe for switching a given SiC

MOSFET.

Some SiC MOSFETs can operate between 0 V and VDD.

For these applications, 0 V<OUT<VDD switching can be

achieved by disabling the charge pump entirely. When

VEESET is connected to SGND and VEE is connected to

PGND, the charge pump is disabled. With the charge pump

disabled and VEE tied directly to PGND, the output switches

between 0 V<OUT<VDD. During this mode of operation the

internal VEE UVLO function is also disabled accordingly.

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Another configuration is to disable the charge pump but

allow the use of an external negative VEE voltage rail. This

option permits –VEE<OUT<VDD switching with a slight

savings in IC power dissipation, since the charge pump is not

switching. With VEESET connected to SGND, an external

negative voltage rail, VEE(EXT), can be connected directly

between VEE and PGND as shown in (bold highlight)

Figure 34. VEE(EXT) can be supplied from a dedicated bias

winding, LDO or an external negative DC power converter.

When using an external VEE(EXT) bias, be mindful that since

VEESET is 0 V, the internal VEE UVLO is disabled and

therefore the NCP51705 is unaware if the VEE voltage level

is within or outside of the expected range.

11 12

7 8

VDD

C C

VCH

VEE

CCH

GLDOLDO

5VEESET

SiC

Drive

(SINK ) 14

OUTSNK

CVEE

NCP51705

VEE Charge

Pump

VEE(EXT)

Figure 34. Supplying VEE with negative external

voltage bias

If none of the pin strapping options provide the desired

VEE negative bias voltage, the VEESET pin can be

programmed using an external voltage bias. An external

LDO from VDD or a simple resistive divider connected

between VDD and SGND can be used as shown in (bold

highlight) Figure 35.

11 12

7 8

VDD

C C

VCH

VEE

CCH

GLDOLDO

5VEESET

SiC

Drive

(SINK)

OUTSNK

CVEE

NCP51705

VEE Charge

Pump

RSET1

RSET2

Figure 35. Applying bias voltage to VEESET

The VEE voltage can programmed from −3.4

V<VEE<−7.6 V for a range of VEESET bias voltage

between 1.5 V<VEESET<10.5 V. The absolute minimum

programmable VEE voltage is −3 V and can be set by

applying 1 V to VEESET, or by simply leaving the VEESET

pin floating. For any VEESET voltage greater than 10.5 V,

up to VDD, the VEE voltage rail is clamped to an absolute

maximum programmable voltage of −7.6 V. The range of

programmable VEE negative voltage versus VEESET bias

voltage is shown graphically in Figure 36.

Figure 36. VEE versus VEESET bias voltage

-8

- 7.5

-7

- 6.5

-6

- 5.5

-5

- 4.5

-4

- 3.5

-3

1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 19.5 21

VEE (V)

VEESET (V)

The configurability of the VEESET pin is summarized in

Table 3

Table 3. Summary of VEESET Pin Configuration

VEESET COMMENT VEE VEE(UVLO)

VDD 10.5 V<VEESET<VDD −8 V −6.4 V

V5V −5 V −4 V

OPEN Add CVEE≤100 pF

from VEESET to

SGND

−3.4 V −2.72 V

SGND Remove CVEE and

connect VEE to PGND

0 V NA

SGND Connect VEE to ex-

ternal negative volt-

age supply

−VEXT NA

Resistor

divider

Resistor divider from

VDD to SGND

Variable NA

NCP51705

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Charge Pump Configuration (VCH, C+, C− and VEE)

As can be seen from the charge pump functional block

diagram shown in Figure 37, only three external capacitors

(CCH, CF and CVEE) are required to establish the negative

VEE voltage rail. The charge pump power stage essentially

consists of two PMOS and two NMOS switches arranged in

a bridge configuration.

11 12

7 8

VDD

C C

VCH

VEE

CCH

GLDOLDO

5VEESET

SiC

Drive

(SINK)

OUTSNK

VDS

CVEE

NCP51705

VEE Charge

Pump

ADJUST

Figure 37. NCP51705 VEE Charge Pump

An external flying capacitor, CF, is connected between the

midpoints of each leg of the bridge as shown. The switching

frequency is internally set at 390 kHz. The VEE output is

seen at the VEE pin and is released after VDD>7 V. Once VEE

exceeds 80% of the set amplitude, the VEE power rail is

deemed sufficient and the VEE Under Voltage Lock Out no

longer prevents switching.

Output (OUTSNK and OUTSRC)

The NCP51705 output is driven by a pure MOS,

low−impedance totem pole output stage to ensure full VEE

to VDD, rail−to−rail switching. The output slew rate is

determined primarily by VDD, VEE and the Ciss of the SiC

MOSFET. The turn−on (OUTSRC) and turn−off

(OUTSNK) functions each have dual dedicated pins. This

allows a single resistor between each pin and the SiC

MOSFET gate to independently control gate ringing as well

as fine tuning dVDS/dT turn−on and turn−off transitions

present on the SiC drain−source voltage. The driver

provides the high peak currents necessary for high−speed

switching, even at the higher Miller plateau voltage typical

of SiC MOSFETs. The outputs of the NCP51705

(OUTSRC, OUTSNK) are rated to 6 A peak current

capability.

Programmable Under−Voltage Lockout (UVSET)

UVLO for a gate driver IC is important for protecting the

MOSFET by disabling the output until VDD is above a

known threshold. This not only protects the load but verifies

to the controller that the applied VDD voltage is above the

turn−on threshold. Because the on−resistance of a SiC

MOSFET has a strong dependency on VGS (and therefore

VDD), allowing the driver output to switch at low VDD can

be detrimental for one SiC MOSFET but may be acceptable

for another depending on heat−sinking, cooling and VDD

start−up time. The optimal UVLO turn−on threshold can

also vary depending on how the VDD voltage rail is derived.

Some power systems may have a dedicated, housekeeping,

bias supply while others might rely on a VDD bootstrapping

technique.

The NCP51705 addresses this need through a

programmable UVLO turn−on threshold that can be set with

a single resistor between UVSET and SGND. As shown in

Figure 38, the UVSET pin is internally driven by a 25 mA

current source. The UVSET resistor, RUVSET, is chosen

according to a desired UVLO turn−on voltage, VON, as

defined by:

RUVSET +VON

6 25 mA(eq. 1)

V5V

25 μA

UVSET

NCP51705

UVSET Function

RUVSET

÷6

VDD

CUVF

Figure 38. NCP51705 UVSET Programmable UVLO

The value for VON is typically determined by referencing

the SiC MOSFET voltage versus current, output

characteristic curves. Because the on−resistance of a SiC

MOSFET dramatically increases even for a slight decrease

in VGS, the allowable UVLO hysteresis must be small. For

this reason, the NCP51705 has a fixed 1 V hysteresis so that

the turn−off voltage, VOFF, is always 1 V less than the set

VON. Due to the narrow, 1 V hysteresis band, a small filter

capacitor, CUVF, is recommended to prevent any periodic or

random noise disturbances on the UVSET pin. A ceramic

capacitor in the range of 10 nF<CUVF<100 nF should be

placed between UVSET and SGND as close as possible to

the IC.

Positive Bias Voltage (VDD and SVDD)

The positive bias voltage for the driver OUTSRC is

provided through VDD. The input bias voltage to the

internal 5 V regulator is provided through SVDD. VDD and

SVDD should be the same value coming from the same

voltage source but they are seperated to allow a small RC

filter to be used at the input to SVDD. A small resistor (few

W’s) can be inserted between VDD and SVDD to help

prevent any switching noise that might be present on VDD

from coupling into the control logic biased by the internal

NCP51705

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5 V regulator. In many cases this resistor may not be

necessary and VDD can be connected directly to SVDD.

However, it is recommended to allow a placeholder on the

PCB design to accommodate this resistor until it can be

determined if it is needed or not.

For VDD>7 V, quiescent current ramps up linearly until

the set UVLO threshold, VON, is crossed. After VDD>VON

and VEE>VEE(UVLO), the IC is properly biased to allow

output switching. Except for the case when

VEESET=SGND (VEE=0 V), both VDD and VEE UVLO

conditions must be met before output switching can ensue.

Two bypass capacitors must be used between VDD and

PGND as detailed in Signal Ground (SGND) and Power

Ground (PGND) section.

Over−Current Protection (DESAT)

The implementation of the NCP51705 DESAT function

can be realized using only two external components. As

shown in Figure 39, the drain−source voltage of the SiC

MOSFET, Q1 is monitored via the DESAT pin through R1

and D1.

1.25 V

500ns

Timer

VDD

400 mA

3.3 V

ENABLE

DESAT _FLT

SiC

Drive

DESAT

OUTSNK

OUTSRC

NCP51705

DESAT Function

R1D1

60 k

12 k

VDS

Figure 39. NCP51705 DESAT Function

During the time that Q1 is off several hundred volts can

appear across the drain−source terminals. Once Q1 is turned

on, the drain−source voltage rapidly falls and this transition

from high−voltage to near zero voltage is expected to

happen in less than a few hundred nano−seconds. During the

turn−on transition, the leading edge of the DESAT signal is

blanked by a 500 ns timer, consisting of a 5 W, low

impedance pull−down resistance. This allows sufficient

time for VDS to fall while at the same time ensuring DESAT

is not inadvertently activated. After 500 ns, the DESAT pin

is released and the 400 mA current source provides a constant

current through R1, D1 and the SiC MOSFET on−resistance.

During the on−time, if the DESAT pin rises above 7.5 V, the

DESAT comparator output goes HIGH which triggers the

clock input of an RS latch. Such a fault will reduce the

on−time of the Q_NOT output on a cycle−by−cycle basis.

The 400 mA current source is sufficient to ensure a

predictable forward voltage drop across D1 while also

allowing the voltage drop across R1 to be independent of

VDS during the on−time of the SiC MOSFET. If desired,

DESAT protection can be disabled by connecting the

DESAT pin to ground. Conversely, if the DESAT pin is left

floating, or R1 fails open, the 400 mA current source flowing

through the 12 kW resistor, puts a constant 4.8 V on the

non−inverting input of the DESAT comparator. This

condition essentially disables the gate drive to the SiC

MOSFET. The voltage on the DESAT pin, VDESAT, is

determined as:

VDESAT +ǒ400 mA R1Ǔ)VD1 )ǒID RDSǓ(eq. 2)

After assigning the maximum value for ID (plus allowing

any additional design margin) R1 and ID are selected such

that VDESAT<7.5 V. Solving for R1 gives:

R1+VDESAT *VD1 *ǒID RDSǓ

400 mA(eq. 3)

In addition to setting the maximum allowable VDS

voltage, R1 also serves the dual purpose of limiting the

instantaneous current through the junction capacitance of

D1. Because the drain voltage on the SiC MOSFET sees

extremely high dV/dt, the current through the p−n junction

capacitance of D1 can become very high if R1 is not sized

appropriately. Therefore, selecting a fast, high−voltage

diode with lowest junction capacitance should be a priority.

Typical values for R1 will be near the range of

5kW<R1<10kW but this can vary according to the ID and

RDS parameters of the selected SiC MOSFET. If R1 is much

smaller than 5 kW, the instantaneous current into the DESAT

pin can be hundreds of milliamps, which is problematic to

the 400 mA internal DESAT current source. Conversely, if

R1 is much larger than 10 kW, a RC delay ensues as a product

of R1 and the junction capacitance of D1. The delay can be

on the order of few ms, resulting in an additional delay time

responding to an over current condition.

5 V Bias (V5V)

This is the bypass capacitor pin for the internal 5 V bias

rail powering the control circuitry. The recommended

capacitor value is 2.2 mF. At least a 1 mF, good−quality,

high−frequency, ceramic capacitor should be placed in close

proximity to the pin. A smaller ceramic capacitor value such

as 100 nF will assure stability but may result in a 500 mV

overshoot on the 5 V rail during start−up. The 5 V rail starts

to rise approximately 30 ms after VDD is applied. Once the

7 V threshold is exceeded at the VDD pin, the 5 V rail is

enabled. The V5V pin can source up to 10 mA making it

suitable for use as a low power bias supply for housekeeping

circuits such as open collector pull−up, optocoupler or

digital isolator bias.

NCP51705

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Applications Information – High−Side Gate Drive Example

Many high−voltage switching applications use power

topologies that include high−side, low−side gate drive

schemes. Some well known examples include converter

topologies such as: LLC, half−bridge and full−bidge. The

NCP51705 can be applied in half−bridge (or full−bridge)

power topologies such as the one shown in Figure 40.

High−voltage applications tend to prefer isolated drivers for

both, the high−side and low−side gate drive. This implies the

need for two digital isolators. In addition to providing

electrical safety and galvanic isolation, the digital isolator

assigned to the high−side gate driver, serves the dual purpose

of level shifting the IN+ PWM input signal. Since the

low−side drive is ground referenced, the digital isolator

dedicated to the low−side gate drive is not level shifted and

therefore only serves the purpose of electrical safety and

galvanic isolation. In this simplified example, IN+

(non−inverting PWM logic) and IN− (active enable) are the

only two signals sourced from the digital controller and

XEN is read back from the NCP51705. XEN can be used as

the timing information basis for developing gate drive

timing, cross conduction prevention, dead−time adjustment

and fault detection. The V5V from the NCP51705 can be

used to power the secondary side of each digital isolator as

shown Figure 40.

Digital Controller

Isolation

Boundary

ENABLE

PWM_HS

XEN_HS

PWM_LS

XEN_LS

FAULT _HS

FAULT _LS

Digital

Isolators

ISOLATOR BIAS

CONTROLLER BIAS (3.3 V or 5 V) 20 V BIAS (isolated)

20 V BIAS (isolated)

Figure 40. NCP51705 Half−Bridge Gate Drive

NCP51705

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PCB Guideline

NCP51705

(Top View )

PGND

IN+

IN−

XEN

VCH

C+

PGND

VEE

OUTSNK

OUTSRC

UVSET

V5V

VDD

OUTSRC

PGND

OUTSNK

VEE VDD

SGND

C−

SVDD

VEESET

DESAT

Figure 41. Recommend PCB drawing

First of all, to optimize operation of SiC gate driving

should be minimize influence of the parasitic inductance and

capacitance on the layout. The following should be

considered before beginning a PCB layout using the

NCP51705.

•The SiC driver should be locate as close as possible to

the SiC MOSFET.

•VDD, SVDD, V5V, Charge Pump and VEE capacitor

should be locate as close as possible to the device.

•When the VEESET = GND, the VEE should be as

close as possible to the PGND trace.

•Driver input and DESAT should not going close to the

high dV/dT traces. It can cause abnormal operation by

significant noise.

•If the device operates in the high temperature condition,

use thermal via distribution from exposed pad to the

other layer to make the thermal resistance as low as

possible. In this case, do not connect the thermal pad to

SGND or PGND.

•Use wide traces for OUTSRC, OUTSNK and VEE

related with main gate driving path.

NCP51705

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PACKAGE DIMENSIONS

QFN24, 4x4, 0.5P

CASE 485L

ISSUE B

ÉÉ

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30 MM

FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

SEATING

PLANE

0.15 C

PIN 1

REFEENCE

2X 0.15 C

0.08 C

0.10 C

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D4.00 BSC

D2 2.70 2.90

E4.00 BSC

E2 2.70 2.90

e0.50 BSC

L0.30 0.50

24X

e/2

0.10 B

0.05

DETAIL A

ALTERNATE

CONSTRUCTIONS

ÉÉÉ

ÇÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

ÇÇ

TOP VIEW

SIDE VIEW

DETAIL B

BOTTOM VIEW

DETAIL A SOLDERING FOOTPRINT

DIMENSIONS: MILLIMETERS

2.90

4.30

0.50

0.55

0.32

24X

PITCH

2.90

RECOMMENDED

NOTE 4 A1

24X

NOTE 3

L1 0.05 0.15

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