INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT283 4-bit binary full adder with fast carry Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 CIN + (A1 + B1) + 2(A2 + B2) + +4(A3 + B3) + 8(A4 + B4) = = 1 + 22 + 43 + 84 + 16COUT FEATURES * High-speed 4-bit binary addition * Cascadable in 4-bit increments Where (+) = plus. * Fast internal look-ahead carry Due to the symmetry of the binary add function, the "283" can be used with either all active HIGH operands (positive logic) or all active LOW operands (negative logic); see function table. In case of all active LOW operands the results 1 to 4 and COUT should be interpreted also as active LOW. With active HIGH inputs, CIN must be held LOW when no "carry in" is intended. Interchanging inputs of equal weight does not affect the operation, thus CIN, A1, B1 can be assigned arbitrarily to pins 5, 6, 7, etc. * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT283 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. See the "583" for the BCD version. The 74HC/HCT283 add two 4-bit binary words (An plus Bn) plus the incoming carry. The binary sum appears on the sum outputs (1 to 4) and the out-going carry (COUT) according to the equation: QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V CIN to 1 16 15 ns CIN to 2 18 21 ns CIN to 3 20 23 ns CIN to 4 23 27 ns An or Bn to n 21 25 ns CIN to COUT 20 23 ns An or Bn to COUT 20 24 ns 3.5 3.5 pF 88 92 pF CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V December 1990 HCT 2 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 4, 1, 13, 10 1 to 4 sum outputs 5, 3, 14, 12 A1 to A4 A operand inputs 6, 2, 15, 11 B1 to B4 B operand inputs 7 CIN carry input 8 GND ground (0 V) 9 COUT carry output 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 Fig.4 Functional diagram. FUNCTION TABLE PINS CIN A1 A2 A3 A4 B1 B2 B3 B4 1 2 3 4 COUT logic levels L L H L H H L L H H H L L H active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 (3) active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 (4) Note 1. H = HIGH voltage level L = LOW voltage level 2. example 1001 1010 ----10011 3. for active HIGH, example = (9 + 10 = 19) 4. for active LOW, example = (carry + 6 + 5 = 12) December 1990 4 EXAMPLE(2) Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CIN to 1 52 19 15 160 32 27 200 40 34 240 48 41 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CIN to 2 58 21 17 180 36 31 225 45 38 270 54 46 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CIN to 3 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CIN to 4 74 27 22 230 46 39 290 58 49 345 69 59 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay An or Bn to n 69 25 20 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CIN to COUT 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay An or Bn to COUT 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 December 1990 6 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CIN B2, A2, A1 B1 1.50 1.00 0.40 B4, A4, A3, B3 0.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay CIN to 1 18 31 39 47 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to 2 25 43 54 65 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to 3 27 46 58 69 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to 4 31 53 66 80 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to n 29 49 61 74 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CIN to COUT 27 46 58 69 ns 4.5 Fig.6 tPHL/ tPLH propagation delay An or Bn to COUT 28 48 60 72 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 December 1990 7 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 AC WAVEFORMS APPLICATION INFORMATION Fig.7 3-bit adder. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the inputs (CIN, An, Bn) to the outputs (n, COUT) propagation delays and the output transition times. Fig.8 2-bit and 1-bit adder. Fig.9 5-input encoder. Notes to Figs 7 to 10 Figure 7 shows a 3-bit adder using the "283". Tying the operand inputs of the fourth adder (A3, B3) LOW makes 3 dependent on, and equal to, the carry from the third adder. Based on the same principle, Figure 8 shows a method of dividing the "283" into a 2-bit and 1-bit adder. The third stage adder (A2, B2, 2) is used simply as means of transferring the carry into the fourth stage (via A2 and B2) and transferring the carry from the second stage on 2. Note that as long as long as A2 and B2 are the same, HIGH or LOW, they do not influence 2. Similarly, when A2 and B2 are the same, the carry into the third stage does not influence the carry out of the third stage. Figure 9 shows a method of implementing a 5-input encoder, where the December 1990 Fig.10 5-input majority gate. inputs are equally weighted. The outputs 0, 1 and 2 produce a binary number equal to the number inputs (I1 to I5) that are HIGH. Figure 10 shows a method of implementing a 5-input majority gate. When three or more inputs (I1 to I5) are HIGH, the output M5 is HIGH. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 8