TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 * * * * * (TOP VIEW) I I I I I I I I I I I GND Functionally Equivalent, but Faster Than Existing 24-Pin PLD Circuits Preload Capability on Output Registers Simplifies Testing DEVICE I INPUTS 3-STATE O OUTPUTS REGISTERED Q OUTPUTS I/O PORT S PAL20L8 14 2 0 6 PAL20R4 12 0 4 (3-state buffers) 4 PAL20R6 12 0 6 (3-state buffers) 2 PAL20R8 12 0 8 (3-state buffers) 0 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I O I/O I/O I/O I/O I/O I/O O I I (TOP VIEW) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability 24 2 TIBPAL20L8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High) Security Fuse Prevents Duplication 1 I I I NC VCC I O * TIBPAL20L8' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE High-Performance Operation: fmax (no feedback) TIBPAL20R' -7C Series . . . 100 MHz TIBPAL20R' -10M Series . . . 62.5 MHz fmax (internal feedback) TIBPAL20R' -7C Series . . . 100 MHz TIBPAL20R' -10M Series . . . 62.5 MHz fmax (external feedback) TIBPAL20R' -7C Series . . . 74 MHz TIBPAL20R' -10M Series . . . 50 MHz Propagation Delay TIBPAL20L8-7C Series . . . 7 ns Max TIBPAL20L8-10M Series . . . 10 ns Max I I I NC I I I 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I/O I/O I/O NC I/O I/O I/O I I GND NC I I O * NC - No internal connection Pin assignments in operating mode description These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space. All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence. The TIBPAL20' C series is characterized from 0C to 75C. The TIBPAL20' M series is characterized for operation over the full military temperature range of -55C to 125C. These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 (TOP VIEW) (TOP VIEW) 24 23 22 21 20 19 18 17 16 15 14 13 VCC I I/O I/O Q Q Q Q I/O I/O I OE I I I NC I I I 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 (TOP VIEW) (TOP VIEW) VCC I I/O Q Q Q Q Q Q I/O I OE I I I NC I I I 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 (TOP VIEW) (TOP VIEW) VCC I Q Q Q Q Q Q Q Q I OE I I I NC I I I 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 NC Pin assignments in operating mode 2 POST OFFICE BOX 655303 OE I Q 24 23 22 21 20 19 18 17 16 15 14 13 I I GND NC 1 2 3 4 5 6 7 8 9 10 11 12 VCC I Q TIBPAL20R8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE I I CLK NC TIBPAL20R8' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE CLK I I I I I I I I I I GND - No internal connection * DALLAS, TEXAS 75265 Q Q Q NC Q Q Q OE I I/O 24 23 22 21 20 19 18 17 16 15 14 13 I I GND NC 1 2 3 4 5 6 7 8 9 10 11 12 VCC I I/O TIBPAL20R6' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE I I CLK NC TIBPAL20R6' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE CLK I I I I I I I I I I GND I/O Q Q NC Q Q I/O OE I I/O 1 2 3 4 5 6 7 8 9 10 11 12 I I GND NC CLK I I I I I I I I I I GND VCC I I/O TIBPAL20R4' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE I I CLK NC TIBPAL20R4' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE Q Q Q NC Q Q Q TIBPAL20L8-7C, TIBPAL20R4-7C TIBPAL20L8-10M, TIBPAL20R4-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 functional block diagrams (positive logic) TIBPAL20L8' & 40 X 64 20 x I 14 20 6 20 EN 1 7 O 7 O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 6 TIBPAL20R4' OE CLK EN 2 C1 & 40 X 64 20 x I 12 1 8 I=0 2 Q 1D 8 Q 8 Q 8 Q 20 4 4 20 EN 1 7 I/O 7 I/O 7 I/O 7 I/O 4 4 denotes fused inputs POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 functional block diagrams (positive logic) TIBPAL20R6' OE CLK EN 2 C1 & 40 X 64 20 x I 12 1 8 I=0 2 Q 1D 8 Q 8 Q 8 Q 8 Q 8 Q 20 6 2 20 EN 1 7 I/O I/O 7 2 6 TIBPAL20R8' OE CLK EN 2 C1 & 40 X 64 20 x I 12 8 1 I=0 2 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 20 8 20 8 denotes fused inputs 4 Q 1D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL20L8-7C TIBPAL20L8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 logic diagram (positive logic) I 1 Increment 0 I 4 8 12 16 20 24 28 32 2 36 39 23 I First Fuse Numbers I I I I I I I I I 3 4 5 6 7 8 9 10 0 40 80 120 160 200 240 280 22 320 360 400 440 480 520 560 600 21 640 680 720 760 800 840 880 920 20 960 1000 1040 1080 1120 1160 1200 1240 19 1280 1320 1360 1400 1440 1480 1520 1560 18 1600 1640 1680 1720 1760 1800 1840 1880 17 1920 1960 2000 2040 2080 2120 2160 2200 16 2240 2280 2320 2360 2400 2440 2480 2520 15 14 11 13 O I/O I/O I/O I/O I/O I/O O I I Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TIBPAL20R4-7C TIBPAL20R4-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 logic diagram (positive logic) CLK 1 Increment 0 I 4 8 12 16 20 24 28 32 36 39 2 23 I First Fuse Numbers I I I I I I I I I 3 4 5 6 7 8 9 10 0 40 80 120 160 200 240 280 22 320 360 400 440 480 520 560 600 21 640 680 720 760 800 840 880 920 I=0 1D 960 1000 1040 1080 1120 1160 1200 1240 I=0 1D 1280 1320 1360 1400 1440 1480 1520 1560 I=0 1D 1600 1640 1680 1720 1760 1800 1840 1880 I=0 1D I/O Q C1 19 Q C1 18 Q C1 17 Q C1 1920 1960 2000 2040 2080 2120 2160 2200 16 2240 2280 2320 2360 2400 2440 2480 2520 15 11 14 13 Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages. 6 20 I/O POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I/O I/O I OE TIBPAL20R6-7C TIBPAL20R6-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 logic diagram (positive logic) CLK 1 Increment 0 I 4 8 12 16 20 24 28 32 36 39 2 23 I First Fuse Numbers I I I I I I I I I 3 4 5 6 7 8 9 10 0 40 80 120 160 200 240 280 22 320 360 400 440 480 520 560 600 I=0 1D 640 680 720 760 800 840 880 920 I=0 1D 960 1000 1040 1080 1120 1160 1200 1240 I=0 1D 1280 1320 1360 1400 1440 1480 1520 1560 I=0 1D 1600 1640 1680 1720 1760 1800 1840 1880 I=0 1D 1920 1960 2000 2040 2080 2120 2160 2200 I=0 1D 21 I/O Q C1 20 Q C1 19 Q C1 18 Q C1 17 Q C1 16 Q C1 2240 2280 2320 2360 2400 2440 2480 2520 15 11 14 13 Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I/O I OE 7 TIBPAL20R8-7C TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 logic diagram (positive logic) CLK 1 Increment 0 I 4 8 12 16 20 24 28 32 36 39 2 23 I First Fuse Numbers I I I I I I I I I 3 4 5 6 7 8 9 10 0 40 80 120 160 200 240 280 I=0 1D 320 360 400 440 480 520 560 600 I=0 1D 640 680 720 760 800 840 880 920 I=0 1D 960 1000 1040 1080 1120 1160 1200 1240 I=0 1D 1280 1320 1360 1400 1440 1480 1520 1560 I=0 1D 1600 1640 1680 1720 1760 1800 1840 1880 I=0 1D 1920 1960 2000 2040 2080 2120 2160 2200 I=0 1D 2240 2280 2320 2360 2400 2440 2480 2520 I=0 1D Q C1 21 Q C1 20 Q C1 19 Q C1 18 Q C1 17 Q C1 16 Q C1 15 Q C1 11 14 13 Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages. 8 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I OE TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle. recommended operating conditions MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage (see Note 2) High-level output current - 3.2 mA IOL fclock Low-level output current 24 mA 100 MHz High-level input voltage (see Note 2) 2 0.8 Clock frequency 0 High 5 Low 5 V tw Pulse duration, clock (see Note 2) tsu th Setup time, input or feedback before clock 7 ns Hold time, input or feedback after clock 0 ns ns TA Operating free-air temperature 0 25 75 C fclock, tw, tsu, and th do not apply for TIBPAL20L8'. NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT -0.8 - 1.5 V VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = - 18 mA IOH = - 3.2 mA VOL IOZH IOZL VCC = 4.75 V, VCC = 5.25 V, IOL = 24 mA VO = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.4 V VI = 5.5 V VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V IOS ICC VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V VI = 0, Ci f = 1 MHz, pF f = 1 MHz, VI = 2 V VO = 2 V 5 Co 6 pF Cclk f = 1 MHz, VCLK = 2 V 6 pF II IIH IIL 2.4 3.2 0.3 - 30 Outputs open V 0.5 V 100 A -100 A 100 A 25 A -80 -250 A -70 -130 mA 150 210 mA switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER FROM (INPUT) fmax TO (OUTPUT) TEST CONDITION without feedback 100 with internal feedback (counter configuration) 100 with external feedback 74 1 or 2 outputs switching TYP MAX UNIT MHz 3 5.5 7 R1 = 200 , 3 6 7.5 Q R2 = 390 , 2 4 6.5 ns CLK Feedback input See Figure 6 3 ns OE Q 4 7.5 ns OE Q 4 7.5 ns I, I/O O, I/O 6 9 ns I, I/O O, I/O 6 9 ns tpd I, I/O tpd tpd# CLK ten tdis ten tdis tsk(o)|| MIN O, I/O 8 outputs switching Skew between registered outputs 0.5 ns ns All typical values are at VCC = 5 V, TA = 25C. I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. See section for fmax specifications. # This parameter applies to TIBPAL20R4' and TIBPAL20R6' only (see Figure 4 for illustration) and is calculated from the measured fmax with internal feedback in the counter configuration. || This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs are switching in the same direction. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current -2 mA IOL fclock Low-level output current 12 mA 62.5 MHz High-level input voltage 2 Clock frequency 0 tw Pulse duration, clock (see Note 2) tsu th Setup time, input or feedback before clock High 8 Low 8 Hold time, input or feedback after clock ns 10 ns 0 ns TA Operating free-air temperature -55 25 125 C fclock, tw, tsu, and th do not apply for TIBPAL20L8'. NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V, II = - 18 mA IOH = - 2 mA VOL IOZH IOZL VCC = 4.5 V, VCC = 5.5 V, IOL = 12 mA VO = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VO = 0.4 V VI = 5.5 V II I/O ports IIH MIN 2.4 TYP MAX UNIT -0.8 - 1.5 V 3.2 0.3 V 0.5 V 20 A - 0.1 mA 1 mA 100 A VCC = 5.5 V, VI = 2.7 V IIL IOS VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 0.5 V ICC VCC = 5.5 V, VI = 0, Outputs open OE = VIH Ci f = 1 MHz, pF f = 1 MHz, VI = 2 V VO = 2 V 5 Co 6 pF Cclk f = 1 MHz, VCLK = 2 V 6 pF All others 25 - 30 - 0.08 - 0.25 mA -70 - 130 mA 140 220 mA switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax FROM (INPUT) TO (OUTPUT) TEST CONDITION MIN without feedback 62.5 with internal feedback (counter configuration) 62.5 with external feedback TYP MAX UNIT MHz 50 I, I/O O, I/O R1 = 390 , 1 6 10 ns CLK Q R2 = 750 , 1 4 10 ns CLK Feedback input See Figure 6 5 ns ten tdis OE Q 1 4 10 ns OE Q 1 4 10 ns ten tdis I, I/O O, I/O 1 6 12 ns I, I/O O, I/O 1 6 10 ns tpd tpd tpd# All typical values are at VCC = 5 V, TA = 25C. I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. See section for fmax specifications. fmax with external feedback is not production tested but is calculated from the equation found in the fmax specification section. # This parameter applies to TIBPAL20R4' and TIBPAL20R6' only (see Figure 4 for illustration) and is calculated from the measured fmax with internal feedback in the counter configuration. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. preload procedure for registered outputs (see Figure 1 and Note 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5 volts and Pin 1 at VIL, raise Pin 13 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH Pin 13 VIL td tsu tw td VIH Pin 1 VIL VIH Registered I/O Input VOH Output VIL VOL Figure 1. Preload Waveforms NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 power-up reset (see Figure 2) Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. VCC 5V 4V tpd (600 ns TYP, 1000 ns MAX) VOH Active Low Registered Output 1.5 V VOL tsu VIH CLK 1.5 V 1.5 V VIL tw This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. Figure 2. Power-Up Reset Waveforms 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 fmax SPECIFICATIONS fmax without feedback, see Figure 3 In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th). However, the minimum fmax is determined by the minimum clock period (tw high + tw low). 1 1 Thus, f max without feedback or (t t ). (t whigh t wlow) su h + ) ) CLK LOGIC ARRAY C1 1D tsu + th or tw high + tw low Figure 3. fmax Without Feedback fmax with internal feedback, see Figure 4 This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop. 1 Thus, f max with internal feedback (t su t CLK to FB) . pd + ) * * Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array. CLK LOGIC ARRAY C1 1D tsu tpd CLK - to - FB Figure 4. fmax With Internal Feedback POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 fmax SPECIFICATIONS fmax with external feedback, see Figure 5 This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tsu + tpd CLK-to-Q). 1 Thus, f max with external feedback (t su t CLK to Q). pd + ) * * CLK LOGIC ARRAY NEXT DEVICE C1 1D tsu tpd CLK - to - Q tsu Figure 5. fmax With External Feedback 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 1.5 V 1.5 V tw th (3.5 V) [3 V] Data Input 1.5 V (3.5 V) [3 V] (0.3 V) [0] In-Phase Output VOH 1.5 V VOL tpd tpd 1.5 V VOH 1.5 V VOL (3.5 V) [3 V] 1.5 V Waveform 1 S1 Closed (see Note B) tdis 1.5 V 3.3 V VOL +0.5 V VOL tdis ten Waveform 2 S1 Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V (0.3 V) [0] ten tpd 1.5 V 1.5 V (0.3 V) [0] Output Control (low-level enabling) 1.5 V tpd 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V (3.5 V) [3 V] Low-Level Pulse 1.5 V (0.3 V) [0] Input 1.5 V (0.3 V) [0] (0.3 V) [0] tsu Out-of-Phase Output (see Note D) (3.5 V) [3 V] High-Level Pulse (3.5 V) [3 V] Timing Input VOH 1.5 V VOH -0.5 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 10 MHz, tr and tf 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated inparentheses ( ). For M suffix, use the voltage levels indicated in brackets [ ]. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 6. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE - AIR TEMPERATURE PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 8 220 7 Propagation Delay Time - ns I CC - Supply Current - mA 200 180 160 140 6 tPHL (I, I/O to O, I/O) 5 tPLH (I, I/O to O, I/O) 4 tPHL (CLK to Q) 3 tPLH (CLK to Q) TA = 25 C CL = 50 pF R1 = 200 R2 = 390 1 Output Switching 2 120 1 100 -75 -50 75 100 -25 0 25 50 TA - Free - Air Temperature - C 0 4.5 125 5.25 4.75 5 VCC - Supply Voltage - V Figure 7 Figure 8 PROPAGATION DELAY TIME vs FREE - AIR TEMPERATURE PROPAGATION DELAY TIME vs LOAD CAPACITANCE 8 16 7 VCC = 5 V TA = 25 C R1 = 200 R2 = 390 1 Output Switching 14 Propagation Delay Time - ns Propagation Delay Time - ns tPHL (I, I/O to O, I/O) 6 tPLH (I, I/O to O, I/O) 5 4 tPHL (CLK to Q) 3 2 1 0 -75 tPLH (CLK to Q) VCC = 5 V CL = 50 pF R1 = 200 R2 = 390 1 Output Switching 12 10 8 tPLH (CLK to Q) tPHL (CLK to Q) 6 tPHL (I, I/O to O, I/O) 4 tPLH (I, I/O to O, I/O) 2 0 -50 75 100 -25 0 25 50 TA - Free - Air Temperature - C 125 0 Figure 9 18 5.5 100 500 200 300 400 CL - Load Capacitance - pF Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 600 TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS005D - D3307, OCTOBER 1989 - REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS POWER DISSIPATION vs FREQUENCY 8 - BIT COUNTER MODE PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING - Skew Between Outputs Switching - ns 1000 900 TA = 0 C TA = 25 C 800 TA = 80 C 700 t skew P - Power Dissipation - mW D VCC = 5 V 600 0.8 VCC = 5 V TA = 25 C R1 = 200 R2 = 390 CL = 50 pF 8-Bit Counter 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 4 10 40 100 2 3 F - Frequency - MHz 4 5 6 7 Number of Outputs Switching Figure 11 8 Figure 12 PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING 8 7 Propagation Delay Time - ns tPHL (I, I/O to O, I/O) 6 tPLH (I, I/O to O, I/O) 5 tPHL (CLK to Q) 4 3 tPLH (CLK to Q) 2 VCC = 5 V TA = 25 C CL = 50 pF R1 = 200 R2 = 390 1 0 0 1 2 3 4 5 6 Number of Outputs Switching 7 8 Figure 13 Outputs switching in the same direction (t PLH compared to tPLH/tPHL to tPHL) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-87671153A ACTIVE LCCC FK 28 1 TBD 5962-8767115KA ACTIVE CFP W 24 1 TBD 1 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type N / A for Pkg Type 5962-8767115LA ACTIVE CDIP JT 24 TBD A42 5962-87671163A OBSOLETE LCCC FK 28 TBD Call TI Call TI 5962-8767116KA OBSOLETE CFP W 24 TBD Call TI Call TI 5962-8767116LA OBSOLETE CDIP JT 24 Call TI Call TI 5962-87671173A ACTIVE LCCC FK 28 1 TBD 5962-8767117KA ACTIVE CFP W 24 1 TBD 5962-8767117LA ACTIVE CDIP JT 24 1 TBD 5962-87671183A ACTIVE LCCC FK 28 1 TBD 5962-8767118KA ACTIVE CFP W 24 1 TBD TBD 5962-8767118LA ACTIVE CDIP JT 24 1 TBD TIBPAL20L8-10MFKB ACTIVE LCCC FK 28 1 TBD TIBPAL20L8-10MJTB ACTIVE CDIP JT 24 1 TBD 1 POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type N / A for Pkg Type TIBPAL20L8-10MWB ACTIVE CFP W 24 TBD A42 TIBPAL20L8-7CFN OBSOLETE PLCC FN 28 TBD Call TI Call TI TIBPAL20L8-7CNT OBSOLETE PDIP NT 24 TBD Call TI Call TI TIBPAL20R4-10MFKB ACTIVE LCCC FK 28 1 TBD TIBPAL20R4-10MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type TIBPAL20R4-10MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type TIBPAL20R4-7CFN OBSOLETE PLCC FN 28 TBD Call TI Call TI Call TI Call TI TBD POST-PLATE N / A for Pkg Type TIBPAL20R4-7CNT OBSOLETE PDIP NT 24 TIBPAL20R6-10MFKB ACTIVE LCCC FK 28 1 TBD TIBPAL20R6-10MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type TIBPAL20R6-10MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type TIBPAL20R6-7CFN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM TIBPAL20R6-7CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU TIBPAL20R8-10MFKB OBSOLETE LCCC FK 28 TBD Call TI Call TI TIBPAL20R8-10MJTB OBSOLETE CDIP JT 24 TBD Call TI Call TI TIBPAL20R8-10MWB OBSOLETE CFP W 24 TBD Call TI Call TI TIBPAL20R8-7CFN ACTIVE PLCC FN 28 37 TBD CU TIBPAL20R8-7CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU POST-PLATE N / A for Pkg Type N / A for Pkg Type Level-1-220C-UNLIM N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A - OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MCFP007 - OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30 TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCER004A - JANUARY 1995 - REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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