SN74ALS841, SN74AS841A . . . DW OR NT PACKAGE
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS842 . . . DW OR NT PACKAGE
(TOP VIEW)
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•3-State Buffer-Type Outputs Drive Bus
Lines Directly
•Bus-Structured Pinout
•Provide Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
•Buffered Control Inputs to Reduce
dc Loading Effects
•Power-Up High-Impedance State
•Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
These 10-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ten latches are transparent D-type latches.
The SN74ALS841 and SN74AS841A have
noninverting data (D) inputs. The SN74ALS842
has inverting D inputs.
A buffered output-enable (OE) input places the ten
outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive provide
the capability to drive bus lines without interface or
pullup components.
OE does not affect the internal operation of the latches. Previously stored data can be retained or new data can
be entered while the outputs are off.
The SN74ALS841, SN74AS841A, and SN74ALS842 are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN74ALS841, SN74AS841A
INPUTS OUTPUT
OE LE D Q
L H H H
LHL L
LLX Q
0
HXX Z
SN74ALS842
INPUTS OUTPUT
OE LE D Q
L H H L
LHL H
LLX Q
0
HXX Z
logic symbols†
EN
1
7
6D 8
7D 9
8D 10
9D
1D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D 4
3D 5
4D 6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
C1
13
LE
11
10D 10Q
14
SN74ALS841, SN74AS841A
EN
1
7
8
9
10
1D
2
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
4
5
6
2Q
22
3Q
21
4Q
20
5Q
19
OE
C1
13
LE
11 10Q
14
SN74ALS842
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
1D
OE
2
1
13
1Q
23
LE
1D
To Nine Other Channels
C1
SN74ALS841, SN74AS841A
1D
OE
2
1
13
1Q
23
LE
1D
To Nine Other Channels
C1
SN74ALS842
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN74ALS841, SN74ALS842 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN74ALS841
SN74ALS842 UNIT
MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –2.6 mA
IOL Low-level output current 24 mA
twPulse duration, LE high 20 ns
tsu Setup time, data before LE↓10 ns
thHold time, data after LE↓5 ns
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS SN74ALS841
SN74ALS842 UNIT
MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VOH
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2
V
V
OH VCC = 4.5 V, IOH = –2.6 mA 2.4 3.2
V
VOL
VCC =45V
IOL = 12 mA 0.25 0.4
V
V
OL
V
CC =
4
.
5
V
IOL = 24 mA 0.35 0.5
V
IOZH VCC = 5.5 V, VO = 2.7 V 20 µA
IOZL VCC = 5.5 V, VO = 0.4 V –20 µA
IIVCC = 5.5 V, VI = 7 V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.1 mA
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 19 30
SN74ALS841 VCC = 5.5 V Outputs low 38 62
ICC
Outputs disabled 23 40
mA
I
CC Outputs high 20 35
mA
SN74ALS842 VCC = 5.5 V Outputs low 48 74
Outputs disabled 27 44
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN74ALS841
MIN MAX
tPLH
D
Q
213
ns
tPHL
D
Q
2 13
ns
tPLH
LE
Q
721
ns
tPHL
LE
Q
8 26
ns
tPZH
OE
Q
212
ns
tPZL
OE
Q
212
ns
tPHZ
OE
Q
2 10
ns
tPLZ
OE
Q
212
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN74ALS842
MIN MAX
tPLH
D
Q
418
ns
tPHL
D
Q
3 13
ns
tPLH
LE
Q
827
ns
tPHL
LE
Q
6 20
ns
tPZH
OE
Q
212
ns
tPZL
OE
Q
212
ns
tPHZ
OE
Q
1 10
ns
tPLZ
OE
Q
212
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN74AS841A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN74AS841A
UNIT
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –24 mA
IOL Low-level output current 48 mA
twPulse duration, LE high 4 ns
tsu Setup time, data before LE↓2.5 ns
thHold time, data after LE↓2.5 ns
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN74AS841A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2
VOH
VCC =45V
IOH = –15 mA 2.4 3.2 V
V
CC =
4
.
5
V
IOH = –24 mA 2
VOL VCC = 4.5 V, IOL = 48 mA 0.35 0.5 V
IOZH VCC = 5.5 V, VO = 2.7 V 50 µA
IOZL VCC = 5.5 V, VO = 0.4 V –50 µA
IIVCC = 5.5 V, VI = 7 V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.5 mA
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 36 60
ICC VCC = 5.5 V Outputs low 58 94 mA
Outputs disabled 56 93
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN74AS841A
MIN MAX
tPLH
D
Q
16.5
ns
tPHL
D
Q
1 10.5
ns
tPLH
LE
Q
212
ns
tPHL
LE
Q
2 12
ns
tPZH
OE
Q
214
ns
tPZL
OE
Q
216
ns
tPHZ
OE
Q
1 8
ns
tPLZ
OE
Q
1 8
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74ALS841DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN74ALS841DWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN74ALS841DWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN74ALS841NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
SN74ALS841NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
SN74ALS842DW OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available
SN74ALS842NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available
SN74AS841ADW OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available
SN74AS841ADWR OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available
SN74AS841ANT OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2010
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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