1. General description
The 74HC4053-Q1 00; 74HCT4053-Q100 is a h igh-speed Si-gate CMOS device and is p in
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74HC4053-Q100; 74HCT4053-Q100 is triple 2-channel analog
multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer
has two independen t inputs/outpu ts (nY0 and n Y1), a common input/output (nZ) a nd three
digital select inputs (Sn). With E LOW, one of the two switches is selected
(low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the
high-impedance OFF-state, independe nt of S1 to S3.
VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053-Q100, and 4.5 V to 5.5 V for
74HCT4053-Q100. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between
VCC as a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
80 (typical) at VCC VEE =4.5V
70 (typical) at VCC VEE =6.0V
60 (typical) at VCC VEE =9.0V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
CDM AEC-Q100-011 revision B exceeds 1000 V
Multiple package options
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Rev. 2 — 22 November 2012 Product data sheet
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 2 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1. Ordering information
Type number Package
Tempe rature range Name Description Version
74HC4053D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT4053D-Q100
74HC4053PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT4053PW-Q100
74HC4053BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5 3.5 0.85 mm
SOT763-1
74HCT4053BQ-Q100
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 3 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
5. Functional diagram
Fig 1. Functional di agram
001aak341
LOGIC
LEVEL
CONVERSION
11
16
VCC
13 1Y1
S1
LOGIC
LEVEL
CONVERSION
DECODER
LOGIC
LEVEL
CONVERSION
12 1Y0
14 1Z
1 2Y1
2 2Y0
15 2Z
3 3Y1
5 3Y0
43Z
10
S2
9
87
VEE
GND
S3
6
E
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aae125
1Y0 12
1Y1
S1
13
11
S210
S39
6E
2Y0 2
2Y1 1
3Y0 5
3Y1 3
3Z 4
2Z 15
1Z 14
001aae126
6EN
11 #
#
#
MUX/DMUX 12
13
× 0
1
0/1
0
1
14
10 2
1
15
9 5
3
4
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 4 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
Fig 4. Schematic diagram (on e sw itc h)
001aad544
from
logic
VCC
VEE
VEE
VCC
VCC
VEE
Y
Z
VCC
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
74HC4053-Q100
74HCT4053-Q100
2Y1 VCC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
GND S3
aaa-003164
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-003165
VEE S2
ES1
3Y0 1Y0
3Z 1Y1
3Y1 1Z
2Y0 2Z
GND
S3
2Y1
VCC
Transparent top view
710
611
512
413
314
215
8
9
1
16
terminal 1
index area
VCC(1)
74HC4053-Q100
74HCT4053-Q100
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 5 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 package: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
E6 enable input (active LOW)
VEE 7 supply voltage
GND 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 common output or input
VCC 16 supply voltage
Table 3. Function table [1]
Inputs Channel on
ESn
LLnY0 to nZ
L H nY1 to nZ
H X switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +11.0 V
IIK input clamping current VI<0.5 V or VI>V
CC +0.5V - 20 mA
ISK switch clamping current VSW <0.5 V or VSW >V
CC +0.5V - 20 mA
ISW switch current 0.5 V < VSW <V
CC +0.5V - 25 mA
IEE supply current - 20 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2] - 500 mW
P power dissipation per switch - 100 mW
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 6 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5. Recommended operating con ditions
Symbol Parameter Conditions 74HC4053-Q100 74HCT4053-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage see Figure 7
and Figure 8
VCC GND 2.0 5.0 10.0 4.5 5.0 5.5 V
VCC VEE 2.0 5.0 10.0 2.0 5.0 10.0 V
VIinput voltage GND - VCC GND - VCC V
VSW switch voltage VEE -V
CC VEE -V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall
rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC =6.0V - - 83 - - - ns/V
VCC = 10.0 V - - 31 - - - ns/V
Fig 7. Guaranteed ope rating area a s a function of th e
supply voltages for 74HC4053-Q100 Fig 8. Guaranteed operating area as a function of the
supply voltages for 74HCT4053-Q100
VCC − VEE (V)
0108462
001aad545
4
6
2
8
10
0
operating area
VCC − GND
(V)
VCC − VEE (V)
0108462
001aad546
4
6
2
8
10
0
VCC − GND
(V)
operating area
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 7 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
10. Static characteristics
Table 6. RON resistance per switch for 74HC4053-Q100 and 74HCT4053-Q100
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4053-Q100: VCC
GND or VCC
VEE = 2.0V, 4.5V, 6.0V and 9.0V.
For 74HCT4053-Q100: VCC
GND = 4.5 V and 5.5 V, VCC
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
RON(peak) ON resistance (peak) Vis =V
CC to VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A-100180
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A-90160
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A-70130
RON(rail) ON resistance (rail) Vis =V
EE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] -150-
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A-80140
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A-70120
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A-60105
Vis =V
CC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] -150-
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A-90160
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A-80140
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A-65120
RON ON resistance mismatch
between channels Vis =V
CC to VEE
VCC = 2.0 V; VEE = 0 V [1] ---
VCC = 4.5 V; VEE = 0 V - 9 -
VCC = 6.0 V; VEE = 0 V - 8 -
VCC = 4.5 V; VEE = 4.5 V - 6 -
Tamb =40 Cto+85C
RON(peak) ON resistance (peak) Vis =V
CC to VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --225
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --200
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --165
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 8 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
[1] When supply voltages (VCC VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
2 V, only use these devices for transmitting digital signals.
RON(rail) ON resistance (rail) Vis =V
EE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --175
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --150
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --130
Vis =V
CC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --200
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --175
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --150
Tamb =40 C to +125 C
RON(peak) ON resistance (peak) Vis =V
CC to VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --270
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --240
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --195
RON(rail) ON resistance (rail) Vis =V
EE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --210
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --180
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --160
Vis =V
CC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A[1] ---
VCC = 4.5 V; VEE = 0 V; ISW = 1000 A --240
VCC = 6.0 V; VEE = 0 V; ISW = 1000 A --210
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --180
Table 6. RON resistance per switch for 74HC4053-Q100 an d 74HCT4053-Q100 …continued
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4053-Q100: VCC
GND or VCC
VEE = 2.0V, 4.5V, 6.0V and 9.0V.
For 74HCT4053-Q100: VCC
GND = 4.5 V and 5.5 V, VCC
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 9 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Vis =0Vto(V
CC VEE). Vis =0Vto(V
CC VEE).
(1) VCC =4.5V
(2) VCC =6V
(3) VCC =9V
Fig 9. Test circuit for measuring RON Fig 10. Typical RON as a function of input voltage Vis
V
001aah826
nYn
Snfrom select
input nZ
GND VEE
VCC
Vis Isw
Vsw
Vis (V)
0 9.07.23.6 5.41.8
mnb047
50
70
30
90
110
10
RON
(Ω)
(1)
(2)
(3)
RON Vsw
Isw
---------
=
Table 7. Static characteristics for 74HC4053-Q100
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input
voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VCC = 9.0 V 6.3 4.7 - V
VIL LOW-level input
voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VCC = 9.0 V - 4.3 2.7 V
IIinput leakage current VEE = 0 V; VI=V
CC or GND
VCC = 6.0 V - - 0.1 A
VCC = 10.0 V - - 0.2 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 0.1 A
all channels - - 0.1 A
IS(ON) ON-state leakage
current VI=V
IH or VIL; VSW=V
CC VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12 --0.1 A
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 10 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
ICC supply current VEE = 0 V; VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 6.0 V - - 8.0 A
VCC = 10.0 V - - 16.0 A
CIinput capacitance - 3.5 - pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ - 8 - pF
Tamb =40 Cto+85C
VIH HIGH-level input
voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input
voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VCC = 9.0 V - - 2.7 V
IIinput leakage current VEE = 0 V; VI=V
CC or GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 1.0 A
all channels - - 1.0 A
IS(ON) ON-state leakage
current VI=V
IH or VIL; VSW=V
CC VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12 --1.0 A
ICC supply current VEE = 0 V; VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 6.0 V - - 80.0 A
VCC = 10.0 V - - 160.0 A
Tamb =40 C to +125 C
VIH HIGH-level input
voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input
voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VCC = 9.0 V - - 2.7 V
Table 7. Static characteristics for 74HC4053-Q100 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 11 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
IIinput leakage current VEE = 0 V; VI=V
CC or GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 1.0 A
all channels - - 1.0 A
IS(ON) ON-state leakage
current VI=V
IH or VIL; VSW=V
CC VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12 --1.0 A
ICC supply current VEE = 0 V; VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 6.0 V - - 160.0 A
VCC = 10.0 V - - 320.0 A
Table 7. Static characteristics for 74HC4053-Q100 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Static characteristics for 74HCT4053-Q100
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V; VEE = 0 V - - 0.1 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 0.1 A
all channels - - 0.1 A
IS(ON) ON-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 12 --0.1 A
ICC supply current VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 5.5 V; VEE = 0 V - - 8.0 A
VCC = 5.0 V; VEE = 5.0 V - - 16.0 A
ICC additional supply
current per input; VI=V
CC 2.1 V ; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - 50 180 A
CIinput capacitance - 3.5 - pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ - 8 - pF
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 12 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Tamb =40 Cto+85C
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V - - 0.8 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 1.0 A
all channels - - 1.0 A
IS(ON) ON-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 12 --1.0 A
ICC supply current VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 5.5 V; VEE = 0 V - - 80.0 A
VCC = 5.0 V; VEE = 5.0 V - - 160.0 A
ICC additional supply
current per input; VI=V
CC 2.1 V ; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - - 225 A
Tamb =40 C to +125 C
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V - - 0.8 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 11
per channel - - 1.0 A
all channels - - 1.0 A
IS(ON) ON-state leakage
current VCC = 10.0 V; VEE = 0 V; VI=V
IH or VIL;
VSW=V
CC VEE; see Figure 12 --1.0 A
ICC supply current VI=V
CC or GND; Vis =V
EE or VCC;
Vos =V
CC or VEE
VCC = 5.5 V; VEE = 0 V - - 160.0 A
VCC = 5.0 V; VEE = 5.0 V - - 320.0 A
ICC additional supply
current per input; VI=V
CC 2.1 V ; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - - 245 A
Table 8. Static characteristics for 74HCT4053-Q100 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 13 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Vis = VCC and Vos = VEE.
Vis = VEE and Vos = VCC.
Fig 11. Test circuit for measuring OFF-state current
Vis = VCC and Vos = open-circuit.
Vis = VEE and Vos = open-circuit.
Fig 12. Test circuit for measuring ON-state current
Isw
A
001aah828
nYn
Sn
HIGH
from select
input nZ
GND V
EE
V
CC
Vis
Vos
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 14 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9. Dynamic characteristics for 74HC4053-Q100
GND = 0 V; tr=t
f=6ns; C
L= 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay Vis to Vos; RL= ; see Figure 13 [1]
VCC = 2.0 V; VEE = 0 V - 15 60 ns
VCC = 4.5 V; VEE =0 V - 5 12 ns
VCC = 6.0 V; VEE =0 V - 4 10 ns
VCC = 4.5 V; VEE =4.5 V - 4 8 ns
ton turn-on time E to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE = 0 V - 60 220 ns
VCC = 4.5 V; VEE = 0 V - 20 44 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 17 - ns
VCC = 6.0 V; VEE = 0 V - 16 37 ns
VCC = 4.5 V; VEE =4.5 V - 15 31 ns
Sn to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE = 0 V - 75 220 ns
VCC = 4.5 V; VEE = 0 V - 25 44 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 21 - ns
VCC = 6.0 V; VEE = 0 V - 20 37 ns
VCC = 4.5 V; VEE =4.5 V - 15 31 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE = 0 V - 63 210 ns
VCC = 4.5 V; VEE = 0 V - 21 42 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 18 - ns
VCC = 6.0 V; VEE = 0 V - 17 36 ns
VCC = 4.5 V; VEE =4.5 V - 15 29 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE = 0 V - 60 210 ns
VCC = 4.5 V; VEE = 0 V - 20 42 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 17 - ns
VCC = 6.0 V; VEE = 0 V - 16 36 ns
VCC = 4.5 V; VEE =4.5 V - 15 29 ns
CPD power dissipation
capacitance per switch; VI = GND to VCC [4] -36- pF
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 15 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Tamb =40 Cto+85C
tpd propagation delay Vis to Vos; RL= ; see Figure 13 [1]
VCC = 2.0 V; VEE =0 V - - 75 ns
VCC = 4.5 V; VEE =0 V - - 15 ns
VCC = 6.0 V; VEE =0 V - - 13 ns
VCC = 4.5 V; VEE =4.5 V - - 10 ns
ton turn-on time E to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE =0 V - - 275 ns
VCC = 4.5 V; VEE =0 V - - 55 ns
VCC = 6.0 V; VEE =0 V - - 47 ns
VCC = 4.5 V; VEE =4.5 V - - 39 ns
Sn to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE =0 V - - 275 ns
VCC = 4.5 V; VEE =0 V - - 55 ns
VCC = 6.0 V; VEE =0 V - - 47 ns
VCC = 4.5 V; VEE =4.5 V - - 39 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE =0 V - - 265 ns
VCC = 4.5 V; VEE =0 V - - 53 ns
VCC = 6.0 V; VEE =0 V - - 45 ns
VCC = 4.5 V; VEE =4.5 V - - 36 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE =0 V - - 265 ns
VCC = 4.5 V; VEE =0 V - - 53 ns
VCC = 6.0 V; VEE =0 V - - 45 ns
VCC = 4.5 V; VEE =4.5 V - - 36 ns
Tamb =40 C to +125 C
tpd propagation delay Vis to Vos; RL= ; see Figure 13 [1]
VCC = 2.0 V; VEE =0 V - - 90 ns
VCC = 4.5 V; VEE =0 V - - 18 ns
VCC = 6.0 V; VEE =0 V - - 15 ns
VCC = 4.5 V; VEE =4.5 V - - 12 ns
Table 9. Dynamic characteristics for 74HC4053-Q100 …continued
GND = 0 V; tr=t
f=6ns; C
L= 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 16 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
[1] tpd is the same as tPHL and tPLH.
[2] ton is the same as tPZH and tPZL.
[3] toff is the same as tPHZ and tPLZ.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2fiN + {(CL+C
sw) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
{(CL+C
sw) VCC2 fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
ton turn-on time E to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE =0 V - - 330 ns
VCC = 4.5 V; VEE =0 V - - 66 ns
VCC = 6.0 V; VEE =0 V - - 56 ns
VCC = 4.5 V; VEE =4.5 V - - 47 ns
Sn to Vos; RL=; see Figure 14 [2]
VCC = 2.0 V; VEE =0 V - - 330 ns
VCC = 4.5 V; VEE =0 V - - 66 ns
VCC = 6.0 V; VEE =0 V - - 56 ns
VCC = 4.5 V; VEE =4.5 V - - 47 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE =0 V - - 315 ns
VCC = 4.5 V; VEE =0 V - - 63 ns
VCC = 6.0 V; VEE =0 V - - 54 ns
VCC = 4.5 V; VEE =4.5 V - - 44 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 2.0 V; VEE =0 V - - 315 ns
VCC = 4.5 V; VEE =0 V - - 63 ns
VCC = 6.0 V; VEE =0 V - - 54 ns
VCC = 4.5 V; VEE =4.5 V - - 44 ns
Table 9. Dynamic characteristics for 74HC4053-Q100 …continued
GND = 0 V; tr=t
f=6ns; C
L= 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 17 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Table 10. Dynamic characteristics for 74HCT4053-Q100
GND = 0 V; tr=t
f=6ns; C
L= 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay Vis to Vos; RL=; see Figure 13 [1]
VCC = 4.5 V; VEE =0 V - 5 12 ns
VCC = 4.5 V; VEE =4.5 V - 4 8 ns
ton turn-on time E to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE = 0 V - 27 48 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 23 - ns
VCC = 4.5 V; VEE =4.5 V - 16 34 ns
Sn to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE = 0 V - 25 48 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 21 - ns
VCC = 4.5 V; VEE =4.5 V - 16 34 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE = 0 V - 24 44 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 20 - ns
VCC = 4.5 V; VEE =4.5 V - 15 31 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE = 0 V - 22 44 ns
VCC = 5.0 V; VEE =0 V; C
L = 15 pF - 19 - ns
VCC = 4.5 V; VEE =4.5 V - 15 31 ns
CPD power dissipation
capacitance per switch; VI = GND to VCC 1.5 V [4] -36- pF
Tamb =40 Cto+85C
tpd propagation delay Vis to Vos; RL=; see Figure 13 [1]
VCC = 4.5 V; VEE =0 V --15ns
VCC = 4.5 V; VEE =4.5 V - - 10 ns
ton turn-on time E to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE =0 V --60ns
VCC = 4.5 V; VEE =4.5 V - - 43 ns
Sn to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE =0 V --60ns
VCC = 4.5 V; VEE =4.5 V - - 43 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE =0 V --55ns
VCC = 4.5 V; VEE =4.5 V - - 39 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE =0 V --55ns
VCC = 4.5 V; VEE =4.5 V - - 39 ns
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 18 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
[1] tpd is the same as tPHL and tPLH.
[2] ton is the same as tPZH and tPZL.
[3] toff is the same as tPHZ and tPLZ.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2fiN + {(CL+C
sw) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
{(CL+C
sw) VCC2 fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
Tamb =40 C to +125 C
tpd propagation delay Vis to Vos; RL=; see Figure 13 [1]
VCC = 4.5 V; VEE =0 V --18ns
VCC = 4.5 V; VEE =4.5 V - - 12 ns
ton turn-on time E to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE =0 V --72ns
VCC = 4.5 V; VEE =4.5 V - - 51 ns
Sn to Vos; RL=1 k; see Figure 14 [2]
VCC = 4.5 V; VEE =0 V --72ns
VCC = 4.5 V; VEE =4.5 V - - 51 ns
toff turn-off time E to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE =0 V --66ns
VCC = 4.5 V; VEE =4.5 V - - 47 ns
Sn to Vos; RL=1 k; see Figure 14 [3]
VCC = 4.5 V; VEE =0 V --66ns
VCC = 4.5 V; VEE =4.5 V - - 47 ns
Table 10. Dynamic characteristics for 74HCT4053-Q100 …continued
GND = 0 V; tr=t
f=6ns; C
L= 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Fig 13. Inpu t (Vis) to output (Vos) p ropagation delays
001aad555
tPLH tPHL
50 %
50 %
Vis input
Vos output
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 19 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
For 74HC4053-Q100: VM=0.5 VCC.
For 74HCT4053-Q100: VM=1.3V.
Fig 14. Turn-on and turn-off times
001aad556
t
PLZ
t
PHZ
switch OFF switch ON
switch ON
V
os
output
V
os
output
E, Sn inputs V
M
V
I
0 V
90 %
10 %
t
PZL
t
PZH
50 %
50 %
Definitions for test circuit; see Table 11:
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
CL= load capacitance including jig and probe capacitance.
RL= load resistance.
S1 = Test selection switch.
Fig 15. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae382
V
CC
V
CC
open
GND
V
EE
V
I
V
os
DUT
CL
RT
RLS1
PULSE
GENERATOR
V
is
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 20 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
[1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.
[2] VI values:
a) For 74HC4053-Q100: VI = VCC
b) For 74HCT4053-Q100: VI = 3 V
11.1 Additional dynamic characteristics
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ).
[2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ).
Table 11. Test da ta
Test Input Load S1 position
VIVis tr, tfCLRL
at fmax other[1]
tPHL, tPLH [2] pulse < 2 ns 6 ns 50 pF 1 kopen
tPZH, tPHZ [2] VCC < 2 ns 6 ns 50 pF 1 kVEE
tPZL, tPLZ [2] VEE < 2 ns 6 ns 50 pF 1 kVCC
Table 12. Additional dynamic characteristics
Recommended conditions and typical values; GND = 0 V; Tamb =25
C; CL=50pF.
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
dsin sine-wave distortion fi= 1 kHz; R L=10k; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V ; VEE =2.25 V - 0.04 - %
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE =4.5 V - 0.02 - %
fi=10kHz; R
L=10k; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V ; VEE =2.25 V - 0.12 - %
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE =4.5 V - 0.06 - %
iso isolation (OFF-state) RL= 600 ; fi= 1 MHz; see Figure 17
VCC = 2.25 V; VEE =2.25 V [1] -50 - dB
VCC = 4.5 V; VEE =4.5 V [1] -50 - dB
Xtalk crosstalk between two switches/multiplexers;
RL= 600 ; fi= 1 MHz; see Figure 18
VCC = 2.25 V; VEE =2.25 V [1] -60 - dB
VCC = 4.5 V; VEE =4.5 V [1] -60 - dB
Vct crosstalk voltage peak-to-peak val ue between control and any
switch. RL=600; fi= 1 MHz; E or Sn square
wave between VCC and GND; tr=t
f=6ns;
see Figure 19
VCC = 4.5 V; VEE =0 V - 110 - mV
VCC = 4.5 V; VEE =4.5 V - 220 - mV
f(3dB) 3 dB frequency response RL=50; see Figure 20
VCC = 2.25 V; VEE =2.25 V [2] -160- MHz
VCC = 4.5 V; VEE =4.5 V [2] -170- MHz
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 21 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Fig 16. Test circuit for measuring sine-wave distortion
dB
001aah829
nYn/nZ
10 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
VCC = 4.5 V; GND = 0 V; VEE =4.5 V; RL= 600 ; RS=1k.
a. Test circuit
b. Isolation (OFF-state) as a function of frequency
Fig 17. Test circuit for measuring isol ati on (OFF-state)
dB
001aah871
nYn/nZ
0.1 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
001aae332
fi (kHz)
10 105106
104
102103
−60
−40
−80
−20
0
αiso
(dB)
−100
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 22 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers
dB
001aah873
nYn/nZ Vos
nZ/nYn
CL
RL
RL
Sn
GNDVEE
VCC
nYn/nZ
0.1 μF
Vis nZ/nYn
CL
RL
RL
Sn
GNDVEE
VCC
Fig 19. Test circuit for measuring crosstalk between control input and any switch
oscilloscope
001aah913
nYn
Vct
nZ
2RL2RL
2RL2RL
Sn, E
GNDVEE
VCC
G
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 23 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
VCC = 4.5 V; GND = 0 V; VEE =4.5 V; RL=50; RS=1k.
a. Test circuit
b. Typical frequency response
Fig 20. Test circuit for frequency response
dB
001aah829
nYn/nZ
10 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
001aad551
f (kHz)
10 105106
104
102103
−1
1
−3
3
5
Vos
(dB)
−5
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 24 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
12. Package outline
Fig 21. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 25 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Fig 22. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 26 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Fig 23. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 27 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
MIL Military
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4053_Q100 v.2 20121122 Product data sheet - 74HC_HCT4053_Q100 v.1
Modifications: •CDM added to features.
74HC_HCT4053_Q100 v.1 20120720 Product data sheet - -
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 28 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whet her the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 29 of 30
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 22 November 2012
Document identifier: 74HC_HCT4053_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14
11.1 Additional dynamic characteristics . . . . . . . . . 20
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16 Contact information. . . . . . . . . . . . . . . . . . . . . 29
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30