CY7C0452V18/0451V18/0450V18 CY7C0431V18/0430V18 PRELIMINARY QuadPortTM Datapath Switching Element (DSE) Family Features * The QuadPortTM Datapath Switching Element (DSE) allows four independent ports of access for data path management and switching. * Synchronous pipelined device -- 128K x 40 (5 Mb) CY7C0452V18 -- 64K x 40 (2 Mb) CY7C0451V18 -- Counter-Interrupt flags to indicate terminal count -- Block Retransmit Capability * -- 32K x 40 (1 Mb) CY7C0450V18 * * * * * -- 128K x 20 (2 Mb) CY7C0431V18 * * * * * * Simple array partitioning (except CY7C0452V18) -- Internal mask register for burst counter control -- 64K x 20 (1 Mb) CY7C0430V18 Clock operation up to 167 MHz High Bandwidth up to 27 Gbps LVTTL and SSTL2 I/O standard for I/O LVPECL differential clock inputs Impedance matching on data outputs -- Counter and mask register readback on address lines Dual Chip Enables on all ports for easy depth expansion (except CY7C0452V18) Separate byte select controls on all ports BGA package (676 balls, 27 x 27 mm, 1.0 mm pitch) Commercial and Industrial temperature ranges IEEE 1149.1 JTAG boundary scan 1.8V Supply Voltage -- Active = 1300 mA (maximum) -- Standby = 500 mA (maximum) QuadPort DSE Applications PORT 1 PORT 3 PORT 2 PORT 4 BUFFERED SWITCH PORT 2 PORT 1 PORT 3 PORT 4 REDUNDANT DATA MIRROR PORT 1 PORT 2 PORT 4 PORT 3 DATA PATH AGGREGATOR Cypress Semiconductor Corporation Document #: 38-06065 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised August 2, 2002 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Pin Configuration 676 Ball Grid Array (BGA) (CY7C0451V18)[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A VSS AIO P1 RWB P1 VDD C VDD C VDD A P1 VDD A P1 VDD VDD VDD A P1 VDD A P1 VDD A P1 VDD A P1 VDD A P4 VDD A P4 VDD A P4 VDD A P4 VDD VDD VDD A P4 VDD A P4 VDD C VDD C RWB P4 25 26 AIO P4 VSS A B DIO P1 B2B P1 B3B P1 MKL DB P1 RETX B P1 CNTRDB P1 WRP 0B P1 VDD VDD CNTI NTB P1 A2 P1 A7 P1 A12 P1 A12 P4 A7 P4 A2 P4 CNTI NTB P4 VDD VDD WRP 0B P4 CNTRDB P4 RETX B P4 MKL DB P4 B3B P4 B2B P4 DIO P4 B C B0B P1 B1B P1 CE1 P1 CE0B P1 CNTRST B P1 CNTL DB P1 CNTI NCB P1 MKR DB P1 NC INTB P1 A3 P1 A8 P1 A13 P1 A13 P4 A8 P4 A3 P4 INTB P4 NC MKR DB P4 CNTI NCB P4 CNTL DB P4 CNTRST B P4 CE0B P4 CE1 P4 B1B P4 B0B P4 C D VDD Q P1 DQ0 P1 DQ1 P1 DQ2 P1 DQ3 P1 DQ4 P1 VSS TRST NC REA DYB P1 A4 P1 A9 P1 A14 P1 A14 P4 A9 P4 A4 P4 REA DYB P4 NC NC VSS DQ4 P4 DQ3 P4 DQ2 P4 DQ1 P4 DQ0 P4 VDD Q P4 D E VDD Q P1 DQ5 P1 DQ6 P1 DQ7 P1 DQ8 P1 DQ9 P1 VSS TMS TDI A0 P1 A5 P1 A10 P1 A15 P1 A15 P4 A10 P4 A5 P4 A0 P4 NC VSS VSS DQ9 P4 DQ8 P4 DQ7 P4 DQ6 P4 DQ5 P4 VDD Q P4 E F VDD Q P1 DQ10 P1 DQ11 P1 DQ12 P1 DQ13 P1 DQ14 P1 VSS TCK TDO A1 P1 A6 P1 A11 P1 NC NC A11 P4 A6 P4 A1 P4 VSS VSS VSS DQ14 P4 DQ13 P4 DQ12 P4 DQ11 P4 DQ10 P4 VDD Q P4 F G VDD Q P1 DQ15 P1 DQ16 P1 DQ17 P1 DQ18 P1 DQ19 P1 VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ19 P4 DQ18 P4 DQ17 P4 DQ16 P4 DQ15 P4 VDD Q P4 G H VDD VDD VDD C ZQ P1 OEB P1 C+ P1 VSS VSS VSS REFA P1 REFA P1 REFA P1 REFA P1 REFA P4 REFA P4 REFA P4 REFA P4 VSS VSS VSS C+ P4 OEB P4 ZQ P4 VDD C VDD VDD H J VDD VDD VDD Q P1 VDD DOFF B P1 CP1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CP4 DOFF B P4 VDD VDD Q P4 VDD VDD J K VDD Q P1 DQ20 P1 DQ21 P1 DQ22 P1 DQ23 P1 DQ24 P1 VSS REF Q P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P4 VSS DQ24 P4 DQ23 P4 DQ22 P4 DQ21 P4 DQ20 P4 VDD Q P4 K L VDD Q P1 DQ25 P1 DQ26 P1 DQ27 P1 DQ28 P1 DQ29 P1 VSS REF Q P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P4 VSS DQ29 P4 DQ28 P4 DQ27 P4 DQ26 P4 DQ25 P4 VDD Q P4 L M VDD Q P1 DQ30 P1 DQ31 P1 DQ32 P1 DQ33 P1 DQ34 P1 VSS REF Q P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P4 VSS DQ34 P4 DQ33 P4 DQ32 P4 DQ31 P4 DQ30 P4 VDD Q P4 M N VDD Q P1 DQ35 P1 DQ36 P1 DQ37 P1 DQ38 P1 DQ39 P1 VSS REF Q P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P4 VSS DQ39 P4 DQ38 P4 DQ37 P4 DQ36 P4 DQ35 P4 VDD Q P4 N P VDD Q P2 DQ35 P2 DQ36 P2 DQ37 P2 DQ38 P2 DQ39 P2 VSS REF Q P2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P3 VSS DQ39 P3 DQ38 P3 DQ37 P3 DQ36 P3 DQ35 P3 VDD Q P3 P R VDD Q P2 DQ30 P2 DQ31 P2 DQ32 P2 DQ33 P2 DQ34 P2 VSS REF Q P2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P3 VSS DQ34 P3 DQ33 P3 DQ32 P3 DQ31 P3 DQ30 P3 VDD Q P3 R T VDD Q P2 DQ25 P2 DQ26 P2 DQ27 P2 DQ28 P2 DQ29 P2 VSS REF Q P2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P3 VSS DQ29 P3 DQ28 P3 DQ27 P3 DQ26 P3 DQ25 P3 VDD Q P3 T U VDD Q P2 DQ20 P2 DQ21 P2 DQ22 P2 DQ23 P2 DQ24 P2 VSS REF Q P2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF Q P3 VSS DQ24 P3 DQ23 P3 DQ22 P3 DQ21 P3 DQ20 P3 VDD Q P3 U V VDD VDD VDD Q P2 VDD DOFF B P2 CP2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CP3 DOFF B P3 VDD VDD Q P3 VDD VDD V W VDD VDD VDD C ZQ P2 OEB P2 C+ P2 VSS VSS VSS REFA P2 REFA P2 REFA P2 REFA P2 REFA P3 REFA P3 REFA P3 REFA P3 VSS VSS VSS C+ P3 OEB P3 ZQ P3 VDD C VDD VDD W Y VDD Q P2 DQ15 P2 DQ16 P2 DQ17 P2 DQ18 P2 DQ19 P2 VSS MRS TB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ19 P3 DQ18 P3 DQ17 P3 DQ16 P3 DQ15 P3 VDD Q P3 Y AA VDD Q P2 DQ10 P2 DQ11 P2 DQ12 P2 DQ13 P2 DQ14 P2 VSS NC NC A1 P2 A6 P2 A11 P2 NC NC A11 P3 A6 P3 A1 P3 VSS VSS VSS DQ14 P3 DQ13 P3 DQ12 P3 DQ11 P3 DQ10 P3 VDD Q P3 AA AB VDD Q P2 DQ5 P2 DQ6 P2 DQ7 P2 DQ8 P2 DQ9 P2 VSS NC NC A0 P2 A5 P2 A10 P2 A15 P2 A15 P3 A10 P3 A5 P3 A0 P3 VSS VSS VSS DQ9 P3 DQ8 P3 DQ7 P3 DQ6 P3 DQ5 P3 VDD Q P3 AB AC VDD Q P2 DQ0 P2 DQ1 P2 DQ2 P2 DQ3 P2 DQ4 P2 VSS NC NC REA DYB P2 A4 P2 A9 P2 A14 P2 A14 P3 A9 P3 A4 P3 REA DYB P3 NC VSS VSS DQ4 P3 DQ3 P3 DQ2 P3 DQ1 P3 DQ0 P3 VDD Q P3 AC AD B0B P2 B1B P2 CE1 P2 CE0B P2 CNTRST B P2 CNTL DB P2 CNTI NCB P2 MKR DB P2 NC INTB P2 A3 P2 A8 P2 A13 P2 A13 P3 A8 P3 A3 P3 INTB P3 NC MKR DB P3 CNTI NCB P3 CNTL DB P3 CNTRST B P3 CE0B P3 CE1 P3 B1B P3 B0B P3 AD AE DIO P2 B2B P2 B3B P2 MKL DB P2 RETX B P2 CNTRDB P2 WRP 0B P2 VDD VDD CNTI NTB P2 A2 P2 A7 P2 A12 P2 A12 P3 A7 P3 A2 P3 CNTI NTB P3 VDD VDD WRP 0B P3 CNTRDB P3 RETX B P3 MKL DB P3 B3B P3 B2B P3 DIO P3 AE AF VSS AIO P2 RWB P2 VDD C VDD C VDD A P2 VDD A P2 VDD VDD VDD A P2 VDD A P2 VDD A P2 VDD A P2 VDD A P3 VDD A P3 VDD A P3 VDD A P3 VDD VDD VDD A P3 VDD A P3 VDD C VDD C RWB P3 AIO P3 VSS AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Note: 1. B Following a Pin name represents an active LOW signal. For example, B0B P1 = B0 P1. Document #: 38-06065 Rev. ** Page 2 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSPIN A1 VSS B19 VDD A2 AIO P1 B20 WRP0B P4 A3 RWB P1 B21 CNTRDB P4 A4 VDDC B22 RETXB P4 A5 VDDC B23 MKLDB P4 A6 VDDA P1 B24 B3B P4 A7 VDDA P1 B25 B2B P4 A8 VDD B26 DIO P4 A9 VDD C1 B0B P1 A10 VDDA P1 C2 B1B P1 A11 VDDA P1 C3 CE1 P1 A12 VDDA P1 C4 CE0B P1 A13 VDDA P1 C5 CNTRSTB P1 A14 VDDA P4 C6 CNTLDB P1 A15 VDDA P4 C7 CNTINCB P1 A16 VDDA P4 C8 MKRDB P1 A17 VDDA P4 C9 NC A18 VDD C10 INTB P1 A19 VDD C11 A3 P1 A20 VDDA P4 C12 A8 P1 A21 VDDA P4 C13 A13 P1 A22 VDDC C14 A13 P4 A23 VDDC C15 A8 P4 A24 RWB P4 C16 A3 P4 A25 AIO P4 C17 INTB P4 A26 VSS C18 NC B1 DIO P1 C19 MKRDB P4 B2 B2B P1 C20 CNTINCB P4 B3 B3B P1 C21 CNTLDB P4 B4 MKLDB P1 C22 CNTRSTB P4 B5 RETXB P1 C23 CE0B P4 B6 CNTRDB P1 C24 CE1 P4 B7 WRP0B P1 C25 B1B P4 B8 VDD C26 B0B P4 B9 VDD D1 VDDQ P1 B10 CNTINTB P1 D2 DQ0 P1 B11 A2 P1 D3 DQ1 P1 B12 A7 P1 D4 DQ2 P1 B13 A12 P1 D5 DQ3 P1 B14 A12 P4 D6 DQ4 P1 B15 A7 P4 D7 VSS B16 A2 P4 D8 TRST B17 CNTINTB P4 D9 NC VDD D10 READYB P1 B18 Document #: 38-06065 Rev. ** CY7C0451V18 Page 3 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSPIN CY7C0451V18 D11 A4 P1 F3 DQ11 P1 D12 A9 P1 F4 DQ12 P1 D13 A14 P1 F5 DQ13 P1 D14 A14 P4 F6 DQ14 P1 D15 A9 P4 F7 VSS D16 A4 P4 F8 TCK D17 READYB P4 F9 TDO D18 NC F10 A1 P1 D19 NC F11 A6 P1 D20 VSS F12 A11 P1 D21 DQ4 P4 F13 NC D22 DQ3 P4 F14 NC D23 DQ2 P4 F15 A11 P4 D24 DQ1 P4 F16 A6 P4 D25 DQ0 P4 F17 A1 P4 D26 VDDQ P4 F18 VSS E1 VDDQ P1 F19 VSS E2 DQ5 P1 F20 VSS E3 DQ6 P1 F21 DQ 14 P4 E4 DQ7 P1 F22 DQ13 P4 E5 DQ8 P1 F23 DQ12 P4 E6 DQ9 P1 F24 DQ11 P4 E7 VSS F25 DQ10 P4 E8 TMS F26 VDDQ P4 E9 TDI G1 VDDQ P1 E10 A0 P4 G2 DQ15 P1 E11 A5 P1 G3 DQ16 P1 E12 A10 P1 G4 DQ17 P1 E13 A15 P1 G5 DQ18 P1 E14 A15 P4 G6 DQ19 P1 E15 A10 P4 G7 VSS E16 A5 P4 G8 NC E17 A0 P1 G9 VSS E18 NC G10 VSS E19 VSS G11 VSS E20 VSS G12 VSS E21 DQ9 P4 G13 VSS E22 DQ8 P4 G14 VSS E23 DQ7 P4 G15 VSS E24 DQ6 P4 G16 VSS E25 DQ5 P4 G17 VSS E26 VDDQ P4 G18 VSS F1 VDDQ P1 G19 VSS F2 DQ10 P1 G20 VSS Document #: 38-06065 Rev. ** Page 4 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSPIN CY7C0451V18 G21 DQ19 P4 J13 VSS G22 DQ18 P4 J14 VSS G23 DQ17 P4 J15 VSS G24 DQ16 P4 J16 VSS G25 DQ15 P4 J17 VSS G26 VDDQ P4 J18 VSS H1 VDD J19 VSS H2 VDD J20 VSS H3 VDDC J21 C- P4 H4 ZQ P1 J22 DOFFB P4 H5 OEB P1 J23 VDD H6 C+ P1 J24 VDDQ P4 H7 VSS J25 VDD H8 VSS J26 VDD H9 VSS K1 VDD1 P1 H10 VREFA P1 K2 DQ20 P1 H11 VREFA P1 K3 DQ21 P1 H12 VREFA P1 K4 DQ22 P1 H13 VREFA P1 K5 DQ23 P1 H14 VREFA P4 K6 DQ24 P1 H15 VREFA P4 K7 VSS H16 VREFA P4 K8 VREFQ P1 H17 VREFA P4 K9 VSS H18 VSS K10 VSS H19 VSS K11 VSS H20 VSS K12 VSS H21 C+ P4 K13 VSS H22 OEB P4 K14 VSS H23 ZQ P4 K15 VSS H24 VDDC K16 VSS H25 VDD K17 VSS H26 VDD K18 VSS J1 VDD K19 VREFQ P4 J2 VDD K20 VSS J3 VDDQ P1 K21 DQ24 P4 J4 VDD K22 DQ23 P4 J5 DOFFB P1 K23 DQ22 P4 J6 C- P1 K24 DQ21 P4 J7 VSS K25 DQ20 P4 J8 VSS K26 VDDQ P4 J9 VSS L1 VDDQ P1 J10 VSS L2 DQ25 P1 J11 VSS L3 DQ26 P1 J12 VSS L4 DQ27 P1 Document #: 38-06065 Rev. ** Page 5 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSPIN CY7C0451V18 L5 DQ28 P1 M23 DQ32 P4 L6 DQ29 P1 M24 DQ31 P4 L7 VSS M25 DQ30 P4 L8 VREFQ P1 M26 VDDQ P4 L9 VSS N1 VDDQ P1 L10 VSS N2 DQ35 P1 L11 VSS N3 DQ36 P1 L12 VSS N4 DQ37 P1 L13 VSS N5 DQ38 P1 L14 VSS N6 DQ39 P1 L15 VSS N7 VSS L16 VSS N8 VREFQ P1 L17 VSS N9 VSS L18 VSS N10 VSS L19 VREFQ P4 N11 VSS L20 VSS N12 VSS L21 DQ29 P4 N13 VSS L22 DQ28 P4 N14 VSS L23 DQ27 P4 N15 VSS L24 DQ26 P4 N16 VSS L25 DQ25 P4 N17 VSS L26 VDDQ P4 N18 VSS M1 VDDQ P1 N19 VREFQ P4 M2 DQ30 P1 N20 VSS M3 DQ31 P1 N21 DQ39 P4 M4 DQ32 P1 N22 DQ38 P4 M5 DQ33 P1 N23 DQ37 P4 M6 DQ34 P1 N24 DQ36 P4 M7 VSS N25 DQ35 P4 M8 VREFQ P1 N26 VDDQ P4 M9 VSS P1 VDDQ P2 M10 VSS P2 DQ35 P2 M11 VSS P3 DQ36 P2 M12 VSS P4 DQ37 P2 M13 VSS P5 DQ38 P2 M14 VSS P6 DQ39 P2 M15 VSS P7 VSS M16 VSS P8 VREFQ P2 M17 VSS P9 VSS M18 VSS P10 VSS M19 VREFQ P4 P11 VSS M20 VSS P12 VSS M21 DQ34 P4 P13 VSS M22 DQ33 P4 P14 VSS Document #: 38-06065 Rev. ** Page 6 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSPIN CY7C0451V18 P15 VSS T7 VSSVSS P16 VSS T8 VREFQ P2 P17 VSS T9 VSS P18 VSS T10 VSS P19 VREFQ P3 T11 VSS P20 VSS T12 VSS P21 DQ39 P3 T13 VSS P22 DQ38 P3 T14 VSS P23 DQ37 P3 T15 VSS P24 DQ36 P3 T16 VSS P25 DQ35 P3 T17 VSS P26 VDDQ P3 T18 VSS R1 VDDQ P2 T19 VREFQ P3 R2 DQ30 P2 T20 VSS R3 DQ31 P2 T21 DQ29 P3 R4 DQ32 P2 T22 DQ28 P3 R5 DQ33 P2 T23 DQ27 P3 R6 DQ34 P2 T24 DQ26 P3 R7 VSS T25 DQ25 P3 R8 VREFQ P2 T26 VDDQ P3 R9 VSS U1 VDDQ P2 R10 VSS U2 DQ20 P2 R11 VSS U3 DQ21 P2 R12 VSS U4 DQ22 P2 R13 VSS U5 DQ23 P2 R14 VSS U6 DQ24 P2 R15 VSS U7 VSS R16 VSS U8 VREFQ P2 R17 VSS U9 VSS R18 VSS U10 VSS R19 VREFQ P3 U11 VSS R20 VSS U12 VSS R21 DQ34 P3 U13 VSS R22 DQ33 P3 U14 VSS R23 DQ32 P3 U15 VSS R24 DQ31 P3 U16 VSS R25 DQ30 P3 U17 VSS R26 VDDQ P3 U18 VSS T1 VDDQ P2 U19 VREFQ P3 T2 DQ25 P2 U20 VSS T3 DQ26 P2 U21 DQ24 P3 T4 DQ27 P2 U22 DQ23 P3 T5 DQ28 P2 U23 DQ22 P3 T6 DQ29 P2 U24 DQ21 P3 Document #: 38-06065 Rev. ** Page 7 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) CY7C0451V18 VSSPIN CY7C0451V18 U25 DQ20 P3 W17 VREFA P3 U26 VDDQ P3 W18 VSS V1 VDD W19 VSS V2 VDD W20 VSS V3 VDDQ P2 W21 C+ P3 V4 VDD W22 OEB P3 V5 DOFFB P2 W23 ZQ P3 V6 C- P2 W24 VDDC V7 VSS W25 VDD V8 VSS W26 VDD VSSPIN V9 VSS Y1 VDDQ P2 V10 VSS Y2 DQ15 P2 V11 VSS Y3 DQ16 P2 V12 VSS Y4 DQ17 P2 V13 VSS Y5 DQ18 P2 V14 VSS Y6 DQ19 P2 V15 VSS Y7 VSS V16 VSS Y8 MRSTB V17 VSS Y9 VSS V18 VSS Y10 VSS V19 VSS Y11 VSS V20 VSS Y12 VSS V21 C- P3 Y13 VSS V22 DOFFB P3 Y14 VSS V23 VDD Y15 VSS V24 VDDQ P3 Y16 VSS V25 VDD Y17 VSS V26 VDD Y18 VSS W1 VDD Y19 VSS W2 VDD Y20 VSS W3 VDDC Y21 DQ19 P3 W4 ZQ P2 Y22 DQ18 P3 W5 OEB P2 Y23 DQ17 P3 W6 C+ P2 Y24 DQ16 P3 W7 VSS Y25 DQ15 P3 W8 VSS Y26 VDDQ P3 W9 VSS AA1 VDDQ P2 W10 VREFA P2 AA2 DQ10 P2 W11 VREFA P2 AA3 DQ11 P2 W12 VREFA P2 AA4 DQ12 P2 W13 VREFA P2 AA5 DQ13 P2 W14 VREFA P3 AA6 DQ14 P2 W15 VREFA P3 AA7 VSS W16 VREFA P3 AA8 NC Document #: 38-06065 Rev. ** Page 8 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) CY7C0451V18 VSSPIN CY7C0451V18 AA9 NC AC1 VDDQ P2 AA10 A1 P2 AC2 DQ0 P2 VSSPIN AA11 A6 P2 AC3 DQ1 P2 AA12 A11 P2 AC4 DQ2 P2 AA13 NC AC5 DQ3 P2 AA14 NC AC6 DQ4 P2 AA15 A11 P3 AC7 VSS AA16 A6 P3 AC8 NC AA17 A1 P3 AC9 NC AA18 VSS AC10 READYB P2 AA19 VSS AC11 A4 P2 AA20 VSS AC12 A9 P2 AA21 DQ 14 P3 AC13 A14 P2 AA22 DQ13 P3 AC14 A14 P3 AA23 DQ12 P3 AC15 A9 P3 AA24 DQ11 P3 AC16 A4 P3 AA25 DQ10 P3 AC17 READYB P3 AA26 VDDQ P3 AC18 NC AB1 VDDQ P2 AC19 VSS AB2 DQ5 P2 AC20 VSS AB3 DQ6 P2 AC21 DQ4 P3 AB4 DQ7 P2 AC22 DQ3 P3 AB5 DQ8 P2 AC23 DQ2 P3 AB6 DQ9 P2 AC24 DQ1 P3 AB7 VSS AC25 DQ0 P3 AB8 NC AC26 VDDQ P3 AB9 NC AD1 B0B P2 AB10 A0 P2 AD2 B1B P2 AB11 A5 P2 AD3 CE1 P2 AB12 A10 P2 AD4 CE0B P2 AB13 A15 P2 AD5 CNTRSTB P2 AB14 A15 P3 AD6 CNTLDB P2 AB15 A10 P3 AD7 CNTINCB P2 AB16 A5 P3 AD8 MKRDB P2 AB17 A0 P3 AD9 NC AB18 VSS AD10 INTB P2 AB19 VSS AD11 A3 P2 AB20 VSS AD12 A8 P2 AB21 DQ9 P3 AD13 A13 P2 AB22 DQ8 P3 AD14 A13 P3 AB23 DQ7 P3 AD15 A8 P3 AB24 DQ6 P3 AD16 A3 P3 AB25 DQ5 P3 AD17 INTB P3 AB26 VDDQ P3 AD18 NC Document #: 38-06065 Rev. ** Page 9 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 Table 1. 676 BGA Pin Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 AD19 MKRDB P3 AF11 VDDA P2 AD20 CNTINCB P3 AF12 VDDA P2 AD21 CNTLDB P3 AF13 VDDA P2 AD22 CNTRSTB P3 AF14 VDDA P3 AD23 CE0B P3 AF15 VDDA P3 AD24 CE1 P3 AF16 VDDA P3 AD25 B1B P3 AF17 VDDA P3 AD26 B0B P3 AF18 VDD AE1 DIO P2 AF19 VDD AE2 B2B P2 AF20 VDDA P3 AE3 B3B P2 AF21 VDDA P3 AE4 MKLDB P2 AF22 VDDC AE5 RETXB P2 AF23 VDDC AE6 CNTRDB P2 AF24 RWB P3 AE7 WRP0B P2 AF25 AIO P3 AE8 VDD AF26 VSS AE9 VDD AE10 CNTINTB P2 AE11 A2 P2 AE12 A7 P2 AE13 A12 P2 AE14 A12 P3 AE15 A7 P3 AE16 A2 P3 AE17 CNTINTB P3 AE18 VDD AE19 VDD AE20 WRP0B P3 AE21 CNTRDB P3 AE22 RETXB P3 AE23 MKLDB P3 AE24 B3B P3 AE25 B2B P3 AE26 DIO P3 AF1 VSS AF2 AIO P2 AF3 RWB P2 AF4 VDDC AF5 VDDC AF6 VDDA P2 AF7 VDDA P2 AF8 VDD AF9 VDD AF10 VDDA P2 Document #: 38-06065 Rev. ** Functional Description The CY7C0452V18/0451V18/0450V18/0431V18/0430V18 is a family of synchronous true four-ported Datapath Switching Element (DSE), up to 27 Gb/s and 5 Mb density. All four ports may be clocked at independent frequencies from one another. Writes and reads are permitted simultaneously from all four ports to the switch array. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same location is not allowed. The QuadPort DSE family can be clocked with synchronous, pipelined accesses up to 167 MHz. Clock to data valid as low as tCD = 3.5 ns. Registers on control, address and data lines allow for minimal set-up and hold time. The QuadPort DSE family supports a burst counter for block transfers of data. The QuadPort DSE also supports features such as: impedance matching, memory block retransmit capability, counter address readback, and mask address readback. Burst Counter Operation Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will self-increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Counter enable inputs are provided to block the external address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with an external address when the port's Counter Load pin (CNTLD) is asserted LOW. When the port's Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-toHIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset Page 10 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 (CNTRST) is used to reset the unmasked portion of burst counter. A counter-mask register is used to control the counter wrap. The counter and mask register operations are described in more detail in the following sections. The counter or mask register values can be read back on the bidirectional address lines by activating CNTRD or MKRD, respectively. Block Retransmit Retransmit is a feature that allows the reread of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal "mirror register" is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it will wrap back to the initial value stored in this "mirror register". If WRP = 0 the unmasked bits will wrap to zero. The mirror register value will be loaded into the counter when RETX is asserted LOW. When WRP = 1 the unmasked bit can wrap to mirror register. If the counter is continuously configured in increment mode, it will increment again to its maximum value and wraps back to the value initially stored into the "mirror register," thus allowing the access of the same data repeatedly without the need for any external logic. Programmable I/Os Each port will have two strapping pins that are used to select the I/O standard used by data and address/control. S0 will set the I/O standard for data and S1 will set the I/O standard for address and control. Either LVTTL or SSTL2 Class 1 I/Os will be selected as shown. I/O Standard Strapping Codes traces on the PCB cause these effects. These mismatches cause reflections on the board, which can dramatically impact a system's ability to transmit data. One of the most common ways used to solve this problem is to place terminating resistors on each trace on the board. These resistor nets ensure that the impedance of the device's I/O matches the traces on the board. This approach, though, can have a huge impact on the amount of board space required in a system. The QuadPort DSE solves both problems by allowing the designer to set the impedance of the I/O driver to match the impedance of the on board traces. Each port of the QuadPort DSE has a Variable Impedance Sense (VIS) circuit. The circuit sets the output impedance for the DQ bus. The calibration circuit has one input called ZQ. A calibrating resistor (RQ) is connected between ZQ and ground. The value of RQ must be 5X the value of the intended line impedance driven by the QuadPort DSE. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 500. When MRST is asserted LOW, the VIS control circuitry is reset and Ready is deasserted. When MRST is released, the VIS circuit begins the process of matching the DQ output impedance to 0.2*RQ. Ready will be asserted within 1024 cycles of each port's respective clock. Each port's DQ output impedance is guaranteed to be in the correct range when its Ready output is asserted LOW. The output impedance is adjusted to account for drifts in supply voltage and temperature every 1024 port clock cycles thereafter. The user may also choose to disable variable impedance matching by connecting ZQ directly to VDD. When VIS is disabled, The DQ output impedance will be less-than equal 75. Variable Impedance Parameters Parameter Minimum Maximum Units Tolerance Strapping Pin Value I/O Standard Selected RQ Value 175 500 2% 0 LVTTL 35 100 15% 1 SSTL2 Output Impedance Reset Time NA 1024 cycles NA Update Time NA 1024 cycles NA Variable Impedance Sense Another problem that is often encountered in high-speed digital design is what is commonly known as transmission line effects. Impedance mismatches between devices and the Document #: 38-06065 Rev. ** Page 11 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Port 1 Operation-Control Logic Blocks[2, 3] READY DOFF B0P1 B1P1 B2P1 Reset Logic MRST B3P1 Port-1 Control Logic R/WP1 OEP1 CE0P1 CE1P1 TMS TCK TDI TRST JTAG Controller TDO DIOP1 AIOP1 C-P1 C+P1 I/O0P1-I/O39P1 Port 1 I/O 40 ZQP1 A0P1-A15P1 Port 4 Logic Blocks[4] 16 MKLDP1 CNTLDP1 CNTINCP1 CNTRDP1 MKRDP1 CNTRSTP1 WRPP1 RETXP1 INTP1 CNTINTP1 Port 1 Counter/ Mask Reg/ Address Decode Port 1 Port 4 QuadPort DSE Array 5/2/1 Meg 128/64/32Kx40 128/64Kx20 Port 2 Port 2 Logic Blocks[4] Port 3 Port 3 Logic Blocks[4] Notes: 2. CY7C0431/0430V18 (x 20) has 20 I/O pins instead of 40. 3. CY7C0452/0431V18 (128K) have 17 address bits instead of 16. CY7C0451/0430V18 (64K) have 16 address bits. CY7C0450V18 (32K) has 15 address bits instead of 16. 4. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. Document #: 38-06065 Rev. ** Page 12 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Pin Definitions Port 1 Port 2 VDDA P1 VDDA P2 VDDQ P1 VDDQ P2 Port 3 Port 4 Description VSS Ground supply for the core, address/control, data, or clock. VDD Power supply for the core. The user must ensure that VDD ramps simultaneously or ahead of all other device power supplies. VDDA P3 VDDA P4 Power supply for address/control I/O on port x VDDQ P3 VDDQ P4 Power supply for data I/O on port x VDDC Power supply for clock I/O VREFA P1 VREFA P2 VREFA P3 VREFA P4 Pins must be connected to I/O reference voltage if using SSTL I/O on address/control on port x VREFQ P1 VREFQ P2 VREFQ P3 VREFQ P4 Pins must be connected to I/O reference voltage if using SSTL I/O on data on port x A0P1-A15P1[3]. A0P2-A15P2[3]. A0P3-A15P3[3]. A0P4-A15P4[3]. Address Input/Output DQ0P1- DQ39P1[2] DQ0P2- DQ39P2[2] DQ0P3- DQ39P3[2] DQ0P4- DQ39P4[2] Data Bus Input/Output C+P1 C+P2 C+P3 C+P4 Positive Clock Input. C+ is used to capture synchronous inputs to the device. This input can be free running or strobed. Maximum clock input rate is fMAX. C-P1 C-P2 C-P3 C-P4 Negative Clock Input. C- is used to capture synchronous inputs to the device and must be equal to C frequency. This input can be free running or strobed. Maximum clock input rate is fMAX. DIOP1 DIOP2 DIOP3 DIOP4 Data Pin I/O Standard Select Input. This pin will select the I/O standard of the data pins. A HIGH signal will select the pins to switch at SSTL2 levels. A LOW signal will select the pins to switch at LVTTL levels. The pins must be strapped to either VCC or VSS upon power-up. AIOP1 AIOP2 AIOP3 AIOP4 Address/Control Pin I/O Standard Select Input. This pin will select the I/O standard of the address and control pins. A HIGH signal will select the pins to switch at SSTL2 levels. A LOW signal will select the pins to switch at LVTTL levels. The pins must be strapped to either VCC or VSS upon power-up. B0P1 B0P2 B0P3 B0P4 Byte 0 Select Input. Asserting this signal LOW enables read and write operations to byte 0. For read operations both the B0 and OE signals must be asserted to drive output data on the lower byte of the data pins. B1P1 B1P2 B1P3 B1P4 B2P1[5] B3P1[5] B2P[5]2 B3P2[5] B2P3[5] B3P3[5] B2P4 CE0P1,CE1P1 CE0P2,CE1P2 OEP1 R/WP1 Byte 1 Select Input. Same function as B0, but to byte 1. [5] Byte 2 Select Input. Same function as B0, but to byte 2. B3P4[5] Byte 3 Select Input. Same function as B0, but to byte 3. CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. To select any port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). OEP2 OEP3 OEP4 Output Enable Input. This signal must be asserted LOW to enable the I/O data lines during read operations. OE is asynchronous input. R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW to write to the QuadPort memory array. For read operations, assert this pin HIGH. Note: 5. Not available for CY7C0431/0430V18 (x 20) Document #: 38-06065 Rev. ** Page 13 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Pin Definitions (continued) Port 1 Port 2 Port 3 Port 4 MRST Description Master Reset Input. This is one signal for all Ports. MRST is an asynchronous input. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation must be performed at power-up. CNTRSTP1[6] CNTRSTP2[6] CNTRSTP3[6] CNTRSTP4[6] Counter Reset Input. Asserting this signal LOW resets the unmasked portion of the burst address counter of its respective port to zero. CNTRST is second to MRST in priority with respect to counter and mask register operations. MKLDP1[6] MKLDP2[6] MKLDP3[6] MKLDP4[6] Mask Register Load Input. Asserting this signal LOW loads the mask register with the external address available on the address lines. MKLD operation has higher priority over CNTLD operation. CNTLDP1[6] CNTLDP2[6] CNTLDP3[6] CNTLDP4[6] Counter Load Input. Asserting this signal LOW loads the burst counter with the external address present on the address pins. CNTINCP1[6] CNTINCP2[6] CNTINCP3[6] CNTINCP4[6] Counter Increment Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of C. CNTRDP1[6] CNTRDP2[6] CNTRDP3[6] CNTRDP4[6] Counter Readback Input. When asserted LOW, the internal address value of the counter will be read back on the address lines. During CNTRD operation, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask register readback operation. Counter readback operation is independent of port chip enables. If address readback operation occurs with chip enables active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will be three-stated. MKRDP1[6] MKRDP2[6] MKRDP3[6] MKRDP4[6] Mask Register Readback Input. When asserted LOW, the value of the mask register will be readback on address lines. During mask register readback operation, all counter and MKLD inputs must be HIGH (see Counter and Mask Register Operations truth table). Mask register readback operation is independent of port chip enables. DQ is three-stated regardless of the chip enables. When the internal counter is driven to the address pins, the DQ pins are three-stated. CNTINTP1[6] CNTINTP2[6] CNTINTP3[6] CNTINTP4[6] Counter Interrupt Flag Output. Flag is asserted LOW for one clock cycle when the counter reaches maximum count. INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communications between all four ports. The upper four memory locations can be used for message passing. Example of operation: INTP4 is asserted LOW when another port writes to the mailbox location of Port 4. Flag is cleared when Port 4 reads the contents of its mailbox. The same operation is applicable to Ports 1, 2, and 3. WRPP1[6] WRPP2[6] WRPP3[6] WRPP4[6] When the burst counter reaches the maximum count, the unmasked bits will wrap to 0 if WRP is asserted LOW. Otherwise, the counter will be loaded with the contents of the mirror register. RETXP1[6] RETXP2[6] RETXP3[6] RETXP4[6] When RETX is asserted LOW the burst counter is loaded with the contents of the mirror register. Note: 6. Not available on CY7C0452V18 Document #: 38-06065 Rev. ** Page 14 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Pin Definitions (continued) Port 1 Port 2 Port 3 Port 4 Description ZQP1 ZQP2 ZQP3 ZQP4 Output Impedance Matching Input. This input is used to adjust the device data outputs impedance to match the system data bus impedance. Output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. The acceptable resistor values for RQ is 175 to 500. Alternately, this pin can be connected directly to VDD, which disables impedance matching. This pin cannot be connected directly to VSS or left floating. READYP1 READYP2 READYP3 READYP4 Output pin indicates the port is ready for operation. The DLL has been properly locked to the clock input signals. The DLL requires 1024 cycles to lock following a master reset operation. DOFFP1 DOFFP2 DOFFP3 DOFFP4 DLL off input pin disables the integrated Delay Locked Loop circuit for the port. DOFF can be toggled LOW then HIGH to reset the DLL for the associated port. That port will require 1024 cycles for the DLL to relock, but the other 3 ports are unaffected. TRST Document #: 38-06065 Rev. ** JTAG Port Reset TCK JTAG Test Clock Input. This can be CLK of any port or an external clock connected to the JTAG TAP. TDI JTAG Test Data Input. This is the only data input. TDI inputs will shift data serially in to the selected register. TDO JTAG Test Data Output. This is the only data output. TDO transitions occur on the falling edge of TCK. TDO normally three-stated except when captured data is shifted out of the JTAG TAP. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Page 15 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 DC Input Voltage for SSTL2 ..........................-0.3V to + 2.7V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage (HBM) ................................ >2200V Storage Temperature ................................ -40C to + 125C Static Discharge Voltage (CDM) .................................. >750V Ambient Temperature with Power Applied............................................ -40C to + 125C Latch-Up Current ..................................................... >200 mA Supply Voltage to Ground Potential .............. -0.5V to + 1.9V DC Voltage Applied to Outputs in High Z State for LVTTL ................ -0.3V to + 3.9V Operating Ranges Range DC Input Voltage........................................... -0.3V to + 3.9V DC Voltage Applied to Outputs in High Z State for SSTL2................ -0.3V to + 2.7V Commercial Industrial Ambient Temperature VDD 0C to +70C 1.8V 5% -40C to +85C 1.8V 5% Current Characteristics Over the Operating Range CY7C0452V18/0451V18/0450V18/0431V18/0430V18 -167 Parameter -133 -100 Description Typ. Max. Typ. Max. Typ. Max. Unit ICC Core Operating Current (VDD = Max., IOUT = 0 mA) Outputs Disabled, CE = VIL, f = fmax 900 1300 700 1100 500 900 mA ISB Core Standby Current (4 Ports CMOS Level, 0 active) CE1-4 VIH, f = 0 200 500 150 500 100 500 mA ICCQ I/O Operating Current per port (VDDQ = Max, no external load, f = fmax) 32 40 29 36 26 32 mA ISBQ I/O Standby Current per port (VDDQ = Max, (no external load, f = 0) OR Outputs Disabled 12 20 12 20 12 20 mA ICCA Address/ Control Operating Current per port (VDDA = Max, no external load, f = fmax) 24 30 22 27 20 24 mA ISBA Address/Control Standby Current per port (VDDA = Max, no external load, f = 0) 12 15 12 15 12 15 mA ICCC Clock / JTAG Operating Current Total (VDDC = Max, f = fmax) 8 10 8 10 8 10 mA ISBC Clock / JTAG Standby Current Total (VDDC = Max, CE1-4 VIH) 8 10 8 10 8 10 mA Document #: 38-06065 Rev. ** Page 16 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Electrical Characteristics CY7C0452V18/0451V18/0450V18/0431V18/ 0430V18 Parameter VDDQ/A I/O Type Description Min. Max. Unit 2.3 2.7 V SSTL2-Class 1 Supply Voltage VREF Reference Voltage 1.15 1.35 V VTT Termination Voltage VREF - 0.04 VREF + 0.04 V VIH Input High Voltage VREF + 0.18 VDDQ + 0.3 V VIL Input Low Voltage (VDDQ = 2.3V-2.7V) -0.3 VREF - 0.18 V 100 A IOZ Output Leakage Current -100 IOH Output Source Current (VDDQ = 2.3V) -7.6 mA IOL Output Sink Current (VDDQ = 2.3V) 7.6 mA Supply Voltage 3.0 3.6 V VIH LVTTL Input High Voltage 2.0 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VOH Output High Voltage (IOH = -8 mA) 2.4 VOL Output Low Voltage (IOL = 8 mA) IOZ Output Leakage Current VDDQ/A VDDC LVPECL (Clocks only) V 0.4 V -100 100 A 3.0 3.6 V Supply Voltage Input High Voltage VDD - 1.2 VDD - 0.85 V VIL Input Low Voltage VDD - 1.85 VDD - 1.45 V VIDIF Input Differential Voltage 600 1000 mV VIH JTAG TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH1 Output HIGH Voltage IOH = -8.0 mA VOL1 Output LOW Voltage IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage Min. Max. Unit 2.4 V 0.4 V 2.0 V 0.8 V Capacitance Parameter Description CIN (ALL PINS) Input Capacitance COUT (ALL PINS) Output Capacitance CIN (C PINS) Input Capacitance Document #: 38-06065 Rev. ** Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF 15 pF Page 17 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 AC Test Load Z0 = 50 R = 50 OUTPUT Z0 = 50 R = 50 5 pF OUTPUT C [7] MEASURE POINT Z0 = 50 R = 50 VTH = 1.5V OUTPUT VTH = 1.5V 5 pF (a) Normal Load (LVTTL) VTH = 3.3V Z0 = 50 R = 50 (b) Three-state Delay OUTPUT RS = 25 C [7] VTT = 0.5 * VDDQ 3.0V GND 90% 10% 90% 10% (a) Normal Load (SSTL2 Class 1) tf = 1.6 ns tr= 1.6 ns 1.5V LVTTL INPUTS 50 TDO Z0 = 50 VIHmin(AC) = VREF + 0.35V VREF = 1.25V VILmax(AC) = VREF - 0.35V VSWING (MAX) C = 20 pF = 1.5V deltaT GND (c) TAP Load deltaT SLEW = (VIHMIN(AC) - VILMAX(AC))/deltaT = 1.0 V/ns SSTL2 INPUTS LVPECL Input Waveform VDD_CLK VIH(MAX) VIH(MIN) 90% 90% VIDIF VIL(MAX) 10% 10% VIL(MIN) VSS_CLK tr / tf tr = Rise Time <= 0.6 ns tf = Fall Time <= 0.6 ns All timing referenced to C+ and C- crossing LVPECL INPUTS Note: 7. Test Conditions: C = 10 pF. Document #: 38-06065 Rev. ** Page 18 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Characteristics Over the Commercial/Industrial Operating Range CY7C0452V18/0451V18/0450V18/0431V18/0430V18 Parameter -167 qualifier Description Min. -133 Max. Min. Max. Min. 133 Max. Unit fMAX Maximum Operating Frequency tCYC Clock Cycle Time 6 7.5 10 ns tCH Clock HIGH Time 2.7 3.4 4.0 ns tCL Clock LOW Time 2.7 tR Clock Rise Time 0.6 0.6 0.6 ns tF Clock Fall Time 0.6 0.6 0.6 ns tSD Input Data Set-up Time tHD Input Data Hold Time 0.7 0.7 0.7 ns tSWRP WRP0 Set-up Time 1.9 2.3 3.0 ns tHWRP WRP0 Hold Time 0.7 0.7 0.7 ns tSRT RETX Set-up Time 1.9 2.3 3.0 ns tHRT RETX Hold Time 0.7 0.7 0.7 ns tSA Address Set-up Time 1.9 2.3 3.0 ns tHA Address Hold Time 0.7 0.7 0.7 ns tSB Byte Set-up Time 1.9 2.3 3.0 ns tHB Byte Hold Time 0.7 0.7 0.7 ns tSC Chip Enable Set-up Time 1.9 2.3 3.0 ns tHC Chip Enable Hold Time 0.7 0.7 0.7 ns tSW R/W Set-up Time 1.9 2.3 3.0 ns tHW R/W Hold Time 0.7 0.7 0.7 ns tSCLD CNTLD Set-up Time 1.9 2.3 3.0 ns tHCLD CNTLD Hold Time 0.7 0.7 0.7 ns tSCINC CNTINC Set-up Time 1.9 2.3 3.0 ns tHCINC CNTINC Hold Time 0.7 0.7 0.7 ns tSCRD CNTRD Set-up Time 1.9 2.3 3.0 ns tHCRD CNTRD Hold Time 0.7 0.7 0.7 ns tSRST CNTRST Set-up Time 1.9 2.3 3.0 ns tHRST CNTRST Hold Time 0.7 0.7 0.7 ns tSMLD MKLD Set-up Time 1.9 2.3 3.0 ns tHMLD MKLD Hold Time 0.7 0.7 0.7 ns tSMRD MKRD Set-up Time 1.9 2.3 3.0 ns tHMRD MKRD Hold Time 0.7 tOE Output Enable to Data Valid tOLZ Output Enable to Low Z 1.0 tOHZ Output Enable to High Z 1.0 tCA Clock to Counter Addr. Readback Valid tAC Address Output Hold After Clock HIGH 1.0 tCKHZA Clock High to Address Output High Z 1.0 Document #: 38-06065 Rev. ** 167 -100 3.4 1.9 4.0 2.3 1.0 6.0 5.5 1.0 7.5 1.0 ns 8.5 1.0 1.0 6.0 ns 0.7 6.5 1.0 5.5 ns 3.0 0.7 5.5 100 ns 8.5 10 1.0 7.5 1.0 ns ns ns ns 10.0 ns Page 19 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Characteristics Over the Commercial/Industrial Operating Range (continued) CY7C0452V18/0451V18/0450V18/0431V18/0430V18 Parameter -167 qualifier Description Min. -133 Max. Min. -100 Max. Min. Max. Unit tCKLZA Clock High to Address Output Low Z tCM Clock to Master Register Readback Valid 6.0 7.5 10 ns 3.5 4.0 4.5 ns 1.0 1.0 1.0 ns tCD with DLL Clock to DQ Valid tDC with DLL DQ/A Output Hold After Clock HIGH 1.0 1.0 1.0 ns tCKLZ with DLL Clock High to DQ/A Output Low Z 0.5 1.0 1.0 ns tCKHZ with DLL Clock High to DQ/A Output High Z 0.5 tCD2 no DLL Clock to DQ Valid (DOFF=0) tDC2 no DLL DQ/A Output Hold After Clock HIGH (DOFF=0) 1.0 tCKHZ2 no DLL Clock HIGH to DQ/A Output High Z (DOFF=0) 1.0 tCKLZ2 no DLL Clock HIGH to DQ/A Output Low Z (DOFF=0) 1.0 1.0 1.0 ns tCCS Clock to Clock Set-up Time 5.0 6.5 9.0 ns tSCINT Clock to CNTINT LOW 4.7 6 7 ns tRCINT Clock to CNTINT HIGH 4.7 6 7 ns tSINT Clock to INT LOW 7.5 9 10 ns tRINT Clock to INT HIGH 7.5 9 10 ns tRS Master Reset Pulse Width 24 30 40 ns tRSR Master Reset Recovery Time 18 22.5 30 ns tRSF Master Reset to Outputs Inactive/High Z tRDY Master Reset Release to Port Ready fJTAG JTAG TAP Controller Frequency tTCYC TCK Cycle Time tTH TCK High Time 40 40 40 ns tTL TCK Low Time 40 40 40 ns tTMSS TMS Set-Up to TCK Rise 10 10 10 ns tTMSH TMS Hold to TCK Rise 10 10 10 ns tTDIS TDI Set-Up to TCK Rise 10 10 10 ns tTDIH TDI Hold to TCK Rise 10 10 10 ns tTDOV TCK Low to TDO Valid tTDOX TCK Low to TDO Invalid 0 0 0 ns tTRS TRST Pulse Width 24 30 40 ns Document #: 38-06065 Rev. ** 3.5 1.0 4.7 4.0 1.0 4.7 1.0 6.0 1.0 4.5 ns 7.0 ns 1.0 6.0 1.0 ns 7.0 ns 18 22.5 30 ns 1024 1024 1024 Cycles 10 10 10 MHz 100 100 20.0 100 20 ns 20.0 ns Page 20 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 JTAG Timing and Switching Waveforms tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Document #: 38-06065 Rev. ** Page 21 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms Master Reset[8, 9, 10] tCYC tCL tCH C+ tCHCH tCL tCH C- tRS tRSR MRST tRSF tRDY READY DQ39:0[2] A16:0[3] CNTINT INT tS[9] All Control Inputs INACTIVE ACTIVE tTRS TRST Notes: 8. A master reset cycle is required after power-up 9. The parameter tS represents the set-up time required for each input 10. At power up, TRST must be asserted low for at least tTRS to ensure the TAP controller is in the Test-Logic-Reset state. Document #: 38-06065 Rev. ** Page 22 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Read Cycle[6, 7, 13] tCYC tCH tCL C+ tCHCH tCH tCHC tCL C- tSW tHW tSA tHA R/W A16:0[3] An An+1 An+2 An+3 tDC DQ39:0[2] Qx-3 Qx-2 An+4 An+5 tCD Qx-1 Qx Qn Qn+1 Write Cycle[11, 14] tCYC tCH tCL tCHCH tCH C+ tCL tCHCH C- tSW tHW tSA tHA R/W A16:0[3] An An+1 An+2 tSD DQ39:0[2] Dn Dn+1 An+3 An+4 Dn+3 Dn+4 tHD Dn+2 Notes: 11. An is the address for location n. Dn is data written to location n. Qn is the data read from location n. 12. There are 3 cycles of latency for data to reach the DQ bus in response to a read instruction 13. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X 14. CE0 = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, OE = CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 23 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Bank Select Read During Depth Expansion[11, 15, 16] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0(B1)[3] An An+1 tHA An+2 tSC An+3 An+4 An+5 An+6 tHC CE0(B1) tCD DQ39:0(B1) [2] tCKLZ Qn tSA A16:0(B2)[3] tCKHZ An An+1 tHA An+2 tSC Qn+2 An+3 An+4 An+5 An+6 tHC CE1(B2) tDC DQ39:0(B2) [2] Qx3 Qx-2 Qx-1 tCKHZ Qx tCD tCKLZ Qn+1 Notes: 15. B1 represents Bank #1 and B2 represents Bank #2. Each bank consists of one QuadPort DSE device. A(B1) = A(B2) 16. CE0(B2) = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1(B1) = R/W = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 24 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Bank Select Write During Depth Expansion[11, 15, 17] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0(B1) [3] An An+1 tHA An+2 tSC tHC tSD tHD An+3 An+4 An+5 An+6 Dn+3 Dn+4 Dn+5 Dn+6 An+3 An+4 An+5 An+6 Dn+3 Dn+4 Dn+5 Dn+6 CE0(B1) DQ39:0(B1)[2] Dn Dn+1 Dn+2 tSA A16:0(B2)[3] An An+1 tHA An+2 tSC tHC tSD tHD CE1(B2) [2] DQ39:0(B2) Dn Dn+1 Dn+2 Note: 17. CE0(B2) = OE = B3 = B2 = B1 = B0 = R/W = CNTLD = VIL, MRST = CE1(B1) = CNTRST = MKLD = VIH,CNTINC = RETX = WRP0 = CNTRD = MKRD= X Document #: 38-06065 Rev. ** Page 25 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Read-to-Write (OE = VIL)[11, 12, 18, 19, 20, 21] tCYC tCH tCL C+ tCHCH tCHCH tCH tCL C- tSA A16:0 tHA [3] tSA Ax An tSW tHA An+1 tHW An+2 tSW tHW tSD tHD R/W tDC [2] DQ39:0 Qx-4 tCD Qx-3 tCKHZ Qx-2 Qx-1 Qx Dn Dn+1 Dn+2 Read-to-Write (OE Controlled)[11, 12, 22, 23, 24] tCYC tCH tCL C+ tCHCH tCHCH tCH tCL C- tSA A16:0 tHA [3] tSA Ax+2 Ax+3 tSW Ax+4 An An+1 An+2 tHW tHA An+3 An+4 tSW tHW tSD tHD R/W OE tDC [2] DQ39:0 Qx-2 tCD Qx-1 tOH Qx Dn Dn+1 Dn+2 Dn+3 Dn+4 Notes: 18. When OE = VIL, the last read operation is allowed to complete before the DQ bus is three-stated and the user is allowed to drive write data. 19. Four dummy writes should be issued to accomplish bus turnaround. The fifth write instruction is the first valid write. 20. The address should be held constant during the four dummy writes and first valid write instruction to avoid data corruption. 21. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X 22. OE should be deasserted and tOHZ allowed to elapse before the first write operation is issued. 23. Any read scheduled to complete after OE is asserted will be preempted. 24. CE0 = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 26 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Byte Enable Write[11, 25] tCYC tCH tCL C+ tCHCH tCHCH tCH tCL C- tSW tHW R/W A16:0[3] An tSD tHD tCD DQ39:30[2,5] 0x000 0x3FF 0x155 0x155 DQ29:20[2,5] 0x000 0x3FF 0x155 0x3FF DQ19:10[2] 0x000 0x3FF 0x2AA 0x2AA DQ9:0[2] 0x000 0x3FF 0x2AA 0x000 tSB tHB B3[5] B2[5] B1 B0 Note: 25. CE0 = OE = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 27 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Byte Enable Read[11, 26] tCYC tCH tCL C+ tCHCH tCHCH tCH tCL C- tSW tHW R/W A16:0[3] An tSD [2,5] DQ39:30 tHD tCKHZ 0x000 0x000 tCKLZ [2,5] DQ29:20 0x3FF 0x3FF tCD [2] DQ19:10 0x155 0x155 DQ9:0[2] 0x2AA 0x2AA tSB tHB B3[5] B2[5] B1 B0 Note: 26. CE0 = OE = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 28 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Read with Address Counter Advance[6, 11, 27] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA [3] A16:0 tHA An Internal address An tSCLD An+1 An+2 An+3 tHCLD CNTLD tSCINC tHCINC CNTINC tCD DQ39:0 [2] Qx-2 Qx-1 Qx tDC Qn Qn+1 Qn+2 Note: 27. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = R/W = CNTRST = MKLD = RETX = VIH, WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 29 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Write with Address Counter Advance[6, 11, 28] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0[3] tHA An Internal address An tSCL An+1 An+2 An+3 tHCLD CNTLD tSCINC tHCINC CNTINC tSD DQ39:0[2] Dn Dn+1 tHD Dn+2 Dn+2 Dn+3 Dn+4 Dn+5 Note: 28. CE0 = B3 = B2 = B1 = B0 = R/W = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, OE = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 30 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Counter Reset[6, 11, 29, 30, 31] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0[3] tHA OX1755 0X17550 Internal address tSCLD 0X17551 0X17000 0X17001 0X17002 tHCLD CNTLD tSCINC tHCINC CNTINC tSRST tHRST CNTRST tSW tHW R/W tCD DQ39:0[2] tDC Q17550 Q17551 Q17000 Notes: 29. Only umasked bits of the burst counter are reset in response to a CNTRST operation. MASK = 0x00FFF. 30. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, R/W = WRP0 = CNTRD = MKRD = X 31. MASK = 0x00FFF. Document #: 38-06065 Rev. ** Page 31 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Counter Interrupt (WRP = VIH)[6, 11, 31, 32, 31, 33, 34, 35, 36, 37, 38] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0[3] tHA OX17FFC Internal address tSCLD 0X17FFC 0X17FFD 0X17FFE 0X17FFF 0X17FFC tHCLD CNTLD tSCINC tHCINC CNTNC tSCINT tRCINT CNTINT tSW tHW R/W tCD DQ39:0[2] tDC Q17FFC Q17FFD Q17FFE Notes: 32. The internal burst counter reaches its maximum count when each bit is either masked or equal to 1. 33. Each port has a mirror register that loads the external address value in response to a CNTLD operation. 34. All bits of the mirror register are reset to 0 in response to a MRST operation. 35. Unmasked bits of the mirror register are reset to 0 in response to a CNTRST operation. 36. The value in the mirror register is unaffected by all other burst counter operations including CNTINC. 37. When WRP0 = VIH, the internal burst counter is loaded with the contents of the mirror register on the cycle after COUNT = maximum count. 38. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 32 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Counter Interrupt (WRP = VIL)[6, 11, 31, 32, 39, 40] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0[3] tHA OX17FFC 0X17FFC Internal address tSCLD 0X17FFD 0X17FFE 0X17FFF 0X17000 tHCLD CNTLD tSCINC tHCINC CNTNC tSCINT tRCINT CNTINT tSW tHW R/W tCD DQ39:0[2] Q17FFC Q17FFD Q17FFE tDC Notes: 39. When WRP0 = VIL, the unmasked bits of the burst counter are reset to 0 on the cycle after COUNT = maximum count. 40. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 33 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Forced Retransmit[6, 11, 31, 32, 33, 34, 35, 36, 41, 42] tCYC tCH tCL C+ tCHCH tCH tCL tCHCH C- tSA A16:0[3] tHA An Internal address tSCLD An An+1 An+2 An An+1 tHCLD CNTLD tSCINC tHCINC CNTINC tSRT tHRT RETX tSW tHW R/W tCD DQ39:0[2] tDC Qn Qn+1 Qn+2 Notes: 41. When RETX= VIL, the value in the mirror register is loaded to the burst counter regardless of the counter's current value. 42. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = VIH, WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 34 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Load and Read Address Counter[6, 11, 43] tCY tCH tCL C+ tCHC tCH tCL tCHCH C- tSA A16:0 [3] tHA tCKLZ An tSCLD tCKHZ An+1 tHCLD tCA2 CNTLD tSCIN tHCINC CNTINC tSCR tHCRD CNTRD R/W tCD [2] DQ39:0 tDC Qn tCKHZ Qn+1 tCKLZ Qn+1 Note: 43. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, WRP0 = MKRD = X Document #: 38-06065 Rev. ** Page 35 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Load and Read Mask Register[6, 11, 44] tCY tCH tCL C+ tCH tCL C- tSA A16:0 [3] tHA tCKLZ 0x17FF tSMLD tCKHZ 0x17FFC tHMLD tCA2 MKLD tSM- tHM- MKRD R/W tCKHZ tCKLZ tCKHZ tCKLZ [2] DQ39:0 Note: 44. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = CNTLD = CNTINC = RETX = CNTRD = VIH, WRP0 = X Document #: 38-06065 Rev. ** Page 36 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Mailbox Interrupt[11, 45, 46, 47, 48] tCYC tCH tCL C+(P1) tCHC tCH tCL tCHCH C-(P1) tHA A16:0(P1) [3] 0x1FFF R/W(P1) tHD tSD [2] DQ39:0(P1) D1FFFE tSINT tRINT INT(P2) tCH tCL C+(P2) tCHC tCH tCL tCHCH C-(P2) tSA A16:0(P2) [3] tHA 0x1FFFE tSW tHW R/W(P2) tCD [2] DQ39:0(P2) tDC Q1FFFE Notes: 45. Port 1 Mailbox Address = 0x1FFFF, Port 2 Mailbox Address = 0x1FFFE, Port 3 Mailbox Address = 0x1FFFD, Port Mailbox Address = 0x1FFFC 46. There is one cycle of latency between writing a mailbox location and the INT flag being asserted LOW. 47. There is one cycle of latency between reading a mailbox location and the INT flag being deasserted HIGH. 48. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 37 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Switching Waveforms (continued) Port 1 Write to Port 2 Read[11, 49, 50, 51] tCYC tCH tCL C+(P1) tCHCH tCH tCL tCHCH C-(P1) tSA A16:0(P1) [3] tHA An tSW tHW tSD tHD R/W(P1) DQ39:0(P1) [2] Dn tCCS tCH tCL C+(P2) tCHCH tCH tCL tCHCH C-(P2) tSA A16:0(P2)[3] tHA An tSW tHW R/W(P2) tCD DQ39:0(P2)[2] tDC Qn Notes: 49. If tCCS is not allowed to elapse between the write on Port 1 and the Read on Port 2, the data resulting from the read operation is indeterminate. 50. This waveform applies to write to read operations on any two ports. 51. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X Document #: 38-06065 Rev. ** Page 38 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 2. Read/Write and Enable Operation (Any Port)[52, 53, 54] Inputs OE C Outputs CE0 CE1 R/W I/O0-I/O39 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN Write L L H H DOUT Read L H X High-Z H X Operation Outputs Disabled Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[6, 52, 55, 56] C MRST CNTRST MKLD CNTLD RETX CNTINC CNTRD MKRD Mode Operation X L X X X X X X X Master Reset Counter/Address Register Reset and Mask Register Set (resets entire chip as per reset state table) H L X X X X X X Reset Counter/Address Register Reset H H L X X X X X Load Load of Address Lines into Mask Register H H H L X X X X Load Load of Address Lines into Counter/Address Register H H H H L X X X H H H H H L X X Increment Counter Increment H H H H H H L X Readback Readback Counter on Address Lines H H H H H H H L Readback Readback Mask Register on Address Lines H H H H H H H H Hold ReLoad address from Mask Register Transmit Counter Hold Notes: 52. "X" = "Don't Care," "H" = VIH, "L" = VIL. 53. OE is an asynchronous input signal. 54. When CE changes state, deselection and read happen after one cycle of latency. 55. CE0 = OE = VIL; CE1 = R/W = VIH. 56. Counter operation and mask register operation are independent of Chip Enables. Document #: 38-06065 Rev. ** Page 39 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Master Reset READY Outputs The QuadPort DSE has a global asynchronous master reset input, MRST. A complete device reset can be initiated at any time by asserting MRST LOW. A master reset cycle is required at power-up. MRST must remain asserted for at least tRS. Additionally, MRST should not be released until all power supplies are fully ramped and all port clocks are stable. Asserting MRST will have the following effects: The QuadPort DSE output circuitry includes some advanced features that enhance the user's interface to the DQ bus. Each port includes an on-board DLL that is used to reduce all output timing parameters. Each port also has a VIS circuit that matches the DQ output driver impedance to one fifth of an external calibration resistor (0.2 * RQ). The user can use the VIS circuit to match the output driver impedance to the board trace impedance, which eliminates the requirement for external series match resistors. Both the DLL and VIS circuits require a calibration period. Calibration cannot start before the supplies for each port have ramped and the clock inputs are stable. Both the DLL and VIS circuits are reset when MRST is asserted. Calibration of both circuits starts when MRST is released. 1. Ready is deasserted (driven HIGH). 2. All DQ and address are three-stated. (No effect on JTAG/TAP signals) 3. The internal burst counter for each port is reset to all 0s. 4. The internal mirror register for each port is reset to all 0s. 5. The internal mask register for each port is set to all 1s (fully unmasked state). 6. All pipeline control registers will be set to an inactive state. 7. All mailbox and burst counter interrupts will be deasserted (driven HIGH). 8. The control circuitry for the internal delay-locked-loops (DLLs) and variable impedance sense (VIS) circuitry for all ports will be reset. The circuitry for each port includes a delay-lock-loop (DLL) and variable impedance sense (VIS). The DLL and VIS circuits require a fully ramped power supply and stable clock to operate correctly. Releasing MRST is a signal to QuadPort DSE that all power supplies have fully ramped and all port clocks are stable. At this time the DLL lock sequence and VIS matching procedure will commence. Each port's READY signal will be asserted (LOW) when the DLL is locked and output impedance matched to 0.2 * RQ. READY will be asserted within 1024 clock cycles of MRST's release. Releasing MRST has the following effects: 1. DLL circuit starts lock procedure. 2. VIS circuit starts matching output impedance. 3. READY for each port is asserted within 1024 clock cycles of the clock for the respective port. If both the DLL and VIS circuitry for a port are disabled (DOFF = 0 and VIS = VCC), then the port's READY is asserted within 2 clock cycles. The following operation commences independent of the READY output state. 4. Data and address outputs remain in three-state, but the three-state control passes to the control pipeline. 5. The burst counter is released from reset. 6. The mirror register is released from reset. 7. The mask register is released from preset. 8. External control inputs are allowed to latch into the control pipeline. When either the DLL or VIS circuits are enabled, the device will not be fully functional until the calibration period has elapsed. This is indicated to the user by the READY output for each port. When MRST is asserted (LOW), READY is deasserted (HIGH). READY will not be asserted until both the DLL and VIS circuits have completed calibration. READY is guaranteed to be asserted within 1024 clock cycles after MRST is released. Any operation that results in data being driven to the DQ bus is prohibited before READY is asserted. All other operations are allowed during the period between the release of MRST and the assertion of READY. The DLL circuit can be disabled by asserting DOFF. The VIS can be disabled by connection the ZQ input to VDD. If both circuits are disabled when MRST is asserted, READY will be asserted within two clock cycles after MRST is released. Interrupts The upper four memory locations may be used for message passing and permit communications between ports. Table 4 shows the interrupt operation for all ports. For the 2-Meg QuadPort DSE, the highest memory location FFFF is the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is the mailbox for Port 3, and FFFC is the mailbox for Port 4. Table 4 shows that in order to set Port 1 INTP1 flag, a write by any other port to address FFFF will assert INTP1 LOW. A read of FFFF location by Port 1 will reset INTP1 HIGH. When one port writes to the other port's mailbox, the Interrupt flag (INT) of the port that the mailbox belongs to is asserted LOW. The Interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. Each port can read the other port's mailbox without resetting the interrupt. If an application does not require message passing, INT pins should be treated as no-connect and should be left floating. When two ports or more write to the same mailbox at the same time INT will be asserted but the contents of the mailbox are not guaranteed to be valid. 9. All mailbox and burst counter interrupts are released from preset. Document #: 38-06065 Rev. ** Page 40 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 4. Interrupt Operation Example[57] Port 1 Function Port 2 Port 3 Port 4 A0P1-15P1 INTP1 A0P2-15P2 INTP2 A0P3-15P3 INTP3 A0P4-15P4 INTP4 X L FFFF X FFFF X FFFF X Reset Port 1 INTP1 Flag FFFF H X X X X X X Set Port 2 INTP2 Flag FFFE X X L FFFE X FFFE X X X FFFE H X X X X FFFD X FFFD X X L FFFD X X X X X FFFD H X X FFFC X FFFC X FFFC X X L X X X X X X FFFC H Set Port 1 INTP1 Flag Reset Port 2 INTP2 Flag Set Port 3 INTP3 Flag Reset Port 3 INTP3 Flag Set Port 4 INTP4 Flag Reset Port 4 INTP4 Flag Note: 57. During Master Reset the control signals will be set to a deselected read state: CE0i = B1i = B2i = B3i = B4i = R/Wi = MKLDi = MKRDi = CNTRDi = CNTRSTi = CNTLDi = CNTINCi = VIH; CE1i = VIL. The "i" suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals. Document #: 38-06065 Rev. ** Page 41 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Address Counter Control Operations[6] Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port's burst counter is loaded with the port's Counter Load pin (CNTLD). When the port's Counter Increment (CNTINC) is asserted, the address counter will increment on each transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. Depending on the mask register state, the counter can address the entire memory array and will loop back to start. Counter Reset (CNTRST) is used to reset the Burst Counter (the Mask Register value is unaffected, the unmasked bits are reset). When using the counter in readback mode, the Read back Register CNTRD MKRD internal address value of the counter will be read back on the address lines when the Counter Readback Signal (CNTRD) is asserted. Figure 1 provides a block diagram of the readback operation. Table 3 lists control signals required for counter operations. The signals are listed based on their priority. For example, Master Reset takes precedence over Counter Reset, and Counter Load has lower priority than Mask Register Load (described below). All counter operations are independent of Chip Enables (CE0 and CE1).The read back address can be either of the burst counter or the mask register based on the levels of Counter Read signal (CNTRD) and Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 3. Counter read has a higher priority than mask read. Addr. Read Back QuadPort MKLD = 1 Mask Register Bidirectional Address Lines WRP = 1 RETX = 1 CNTINC = 1 DSE Array Counter/ Address Register CNTLD = 1 CNTRST = 1 CLK Figure 1. Counter and Mask Register Read Back on Address Lines Document #: 38-06065 Rev. ** Page 42 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Counter-Mask Register Example: Load Counter-Mask Register = 3F CNTINT H 0 0 0s 215 214 H X X Xs 215 214 Max Address Register H X X L X X 215 214 1 1 1 1 Mask Register bit-0 Counter Address X 0 0 1 0 0 0 26 25 24 23 22 21 20 Xs 215 214 Max + 1 Address Register 1 26 25 24 23 22 21 20 Blocked Address Load Address Counter = 8 0 1 X 1 1 1 1 1 Address Counter bit-0 1 26 25 24 23 22 21 20 Xs X 0 0 0 0 0 0 26 25 24 23 22 21 20 Figure 2. Programmable Counter-Mask Register Operation[58] The burst counter has a mask register that controls when and where the counter wraps. An interrupt flag (CNTINT) is asserted for one clock cycle when the unmasked portion of the counter address reaches maximum count (all 1s). The example in Figure 2 shows the counter mask register loaded with a mask value of 003F unmasking the first 6 bits with bit "0" as the LSB and bit "15" as the MSB. The maximum value the mask register can be loaded with is FFFF. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of XXX8. The "blocked" addresses (in this case, the 6th address through the 15th address) are loaded with an address but do not increment once loaded. The counter address will start at address XXX8. With CNTINC asserted LOW, the counter will increment its internal address value till it reaches the mask register value of 3F and wraps around the memory block to location XXX0. Therefore, the counter uses the mask-register to define wrap-around point. The mask register of a port is loaded when MKLD (mask register load) for that port is LOW. When MKRD is LOW, the value of the mask register can be read out on the address lines in a manner similar to the counter read back operation (see Table 3 for required conditions). When the burst counter is loaded with an address higher than the mask register value, the higher addresses will form the masked portion of the counter address and are called blocked addresses. The blocked addresses will not be changed or affected by the counter increment operation. The only exception is mask register bit 0. It can be masked to allow the address counter to increment by two. If the mask register bit 0 is loaded with a logic value of "0," then address counter bit 0 is masked and can not be changed during counter increment operation. If the loaded value for address counter bit 0 is "0," the counter will increment by two and the address values are even. If the loaded value for address counter bit 0 is "1," the counter will increment by two and the address values are odd. This operation allows the user to achieve an 80-bit interface using any two ports, where the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of an 80-bit word in even memory locations, and the other half in odd memory locations. CNTINT will be asserted when the unmasked portion of the counter reaches its maximum count. Loading mask register bit 0 with "1" allows the counter to increment the address value sequentially. Table 3 groups the operations of the mask register with the operations of the address counter. Address counter and mask register signals are all synchronized to the port's clock C+. Master reset (MRST) is the only asynchronous signal listed on Table 3. Signals are listed based on their priority going from left column to right column with MRST being the highest. A LOW on MRST will reset the counter register to all zeros and the mask register to all ones. On the other hand, a LOW on CNTRST will only clear the address counter register to zeros and the mask register will remain unaffected. There are four operations for the counter and mask register: 1. Load operation: When CNTLD or MKLD is LOW, the address counter or the mask register is loaded with the address value presented at the address lines. This value ranges from 0 to FFFF (64K). The mask register load operation has a higher priority over the address counter load operation. Note: 58. The "X" in this diagram represents the counter upper-bits. Document #: 38-06065 Rev. ** Page 43 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 2. Increment: Once the address counter is loaded with an external address, the counter can internally increment the address value by asserting CNTINC LOW. The counter can address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to the load operation. 3. Readback: The internal value of either the burst counter or the mask register can be read out on the address lines when CNTRD or MKRD is LOW. Counter readback has higher priority over mask register readback. Counter and mask register readback have the same latency as memory READ operations, i.e., three (3) cycles. The address will be valid after tCA2 (for counter readback) or tCM2 (for mask readback) from the port's third following clock rising edge. Address readback operation is independent of the port's chip enables (CE0 and CE1). If address readback occurs while the port is enabled (chip enables active), the data lines (I/Os) will be three-stated, during the cycle the address is driven from the part. 4. Hold operation: In order to hold the value of the address counter at certain address, all signals in Table 3 have to be HIGH. This operation has the least priority. This operation is useful in many applications where wait states are needed or when the address is available few cycles ahead of data. The counter and mask register operations are totally independent of port chip enables. IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C0452/451/450/431/430V18 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-2001. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. It is composed of four input connections and one output connection required by the test logic defined by the standard. Disabling the JTAG Feature It is possible to operate the QuadPort DSE without using the JTAG feature, by setting TRST* to ground (VSS). Test Access Port (TAP) - Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Data Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram (FSM)). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Test Reset (TRSTB) This input provides for asynchronous initialization of the TAP controller. According to IEEE 1149.1-2001 the TAP controller shall be asynchronously reset to the TEST-Logic_reset controller state when a 0 logic is applied to TRSTB. TAP initialization is independent of system initialization (MRSTB). TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the QuadPort DSE test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Four-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the following JTAG/BIST Controller diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the Test Reset section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain devices. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the QuadPort DSE with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. The boundary scan register is connected to all the input and output pins on the QuadPort DSE. The boundary scan register is loaded with the contents of the QP Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring. Test Data-In (TDI) Identification (ID) Register The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the QuadPort DSE and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Test Mode Select Document #: 38-06065 Rev. ** Page 44 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 TAP Instruction Set SAMPLE/PRELOAD Sixteen different instructions are possible with the 4-bit instruction register. All combinations are listed in Table 6, Instruction Codes. Seven of these instructions (codes) are listed as RESERVED and should not be used. The other nine instructions are described in detail below. The TAP controller used in this QuadPort DSE is fully compliant to the 1149.1 convention. The TAP controller can be used to load address, data or control signals into the QuadPort DSE and can preload the Input or output buffers. The QuadPort DSE implements all of the 1149.1 instructions except INTEST. Table 6 lists all instructions. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the QuadPort DSE clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the QuadPort DSE signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. If the TAP controller goes into the Update-DR state, the sampled data will be updated. EXTEST EXTEST is a mandatory 1149.1 instruction that is to be executed whenever the instruction register is loaded with all 0s. EXTEST allows circuitry external to the QuadPort DSE package to be tested. Boundary-scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the identification register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or when-ever the TAP controller is given a test logic reset state. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all QuadPort DSE outputs into a High-Z state. Document #: 38-06065 Rev. ** BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. CLAMP The optional CLAMP instruction allows the state of the signals driven from QuadPort DSE pins to be determined from the boundary-scan register while the BYPASS register is selected as the serial path between TDI and TDO. CLAMP controls boundary cells to 1 or 0. Page 45 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Tap Controller State Diagram (FSM)[59] 1 TEST-LOGIC RESET 0 RUN_TEST/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 59. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06065 Rev. ** Page 46 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 0 Bypass Register (BYR) 3 2 1 0 Instruction Register (IR) 31 30 29 0 Identification Register (IDR) TDI 39 38 37 TDO 0 EID Register 63 62 61 Selection Circuitry (MUX) 0 VIS Register 557 0 Boundary Scan Register (BSR) TAP CONTROLLER TCK TMS TRST Document #: 38-06065 Rev. ** Page 47 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Table 5. Scan Registers Sizes Register Name Bit Size Bypass (BYR) 1 Instruction (IR) 4 Identification (IDR) 32 Electrical Identification Register (EID) 40 Variable Impedance Register (VIS) 64 Boundary Scan (BSR) 558 Table 6. Instruction Identification Codes Instruction Bypass 1111 Code Sample/Preload 1000 Extest[60] 0000 Idcode 1011 Clamp[60] 0100 [60] Highz 0111 Intest[60] 0001 Eidcode 1001 VIS 1010 Description Places the bypass register (BYR) between TDI and TDO. Captures the Input/Output ring contents. Places the boundary scan register (BSR) between TDI and TDO. Captures the Input/Output ring contents. Places the boundary scan register (BSR) between the TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Controls boundary to 1/0. Uses BYR. Places the BYR between TDI and TDO. Forces all QuadPort DSE output drivers to a High-Z state. Allows testing of the on-chip system logic while the component is assembled on the board. The test stimuli are shifted in one at a time and applied to the on-chip system logic. Loads the Electrical Identification Register (EID) with the vendor Electrical ID code and places the register between TDI and TDO. Loads the Variable Impedance Register (VIS) with the vendor VIS ID code and places the register between TDI and TDO. Note: 60. Instruction that requires a master reset after completion before using the chip in normal mode Document #: 38-06065 Rev. ** Page 48 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Ordering Information 128K x 40 1.8V Synchronous QuadPort DSE Speed (MHz) Ordering Code 167 CY7C0452V18-167BBI 133 100 Package Name Package Type Operating Range BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial CY7C0452V18-167BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial CY7C0452V18-133BBI BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial CY7C0452V18-133BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial CY7C0452V18-100BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 64K x 40 1.8V Synchronous QuadPort DSE Speed (MHz) 167 133 100 Ordering Code Package Name Package Type Operating Range CY7C0451V18-167BBI BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial CY7C0451V18-167BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial CY7C0451V18-133BBI BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial CY7C0451V18-133BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial CY7C0451V18-100BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 32K x 40 1.8V Synchronous QuadPort DSE Speed (MHz) Ordering Code Package Name Package Type Operating Range 167 CY7C0450V18-167BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 133 CY7C0450V18-133BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 100 CY7C0450V18-100BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 128K x 20 1.8V Synchronous QuadPort DSE Speed (MHz) Ordering Code Package Name Package Type Operating Range BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial CY7C0431V18-167BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial CY7C0431V18-133BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 167 CY7C0431V18-167BBI 133 100 CY7C0431V18-100BBC 64K x 20 1.8V Synchronous QuadPort DSE Speed (MHz) Ordering Code Package Name Package Type Operating Range 167 CY7C0430V18-167BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 133 CY7C0430V18-133BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial 100 CY7C0430V18-100BBC BB676 Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial Document #: 38-06065 Rev. ** Page 49 of 51 CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Package Diagram 676-Ball FBGA (27 x 27 x 1.6 mm) BB676 51-85125-*B QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06065 Rev. ** Page 50 of 51 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18 Document Title: CY7C0452V18/0451V18/0450V18/0431V18/0430V18 QuadPortTM Datapath Switching Element (DSE) Family Document Number: 38-06065 REV. ECN NO. Issue Date Orig. of Change ** 117356 08/02/02 OOR Document #: 38-06065 Rev. ** Description of Change New Data Sheet Page 51 of 51