74F381SJ - National Semiconductor

TL/F/9528

74F381 4-Bit Arithmetic Logic Unit

August 1995

74F381

4-Bit Arithmetic Logic Unit

General Description

The ’F381 performs three arithmetic and three logic opera-

tions on two 4-bit words, A and B. Two additional select

input codes force the function outputs LOW or HIGH. Carry

propagate and generate outputs are provided for use with

the ’F182 carry lookahead generator for high-speed expan-

sion to longer word lengths. For ripple expansion, refer to

the ’F382 ALU data sheet.

Features

YLow input loading minimizes drive requirements

YPerforms six arithmetic and logic functions

YSelectable LOW (clear) and HIGH (preset) functions

YCarry generate and propagate outputs for use with

carry lookahead generator

Commercial Package Package Description

Number

74F381PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line

74F381SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC

74F381SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ

Note 1: Devices also available in 13×reel. Use suffix eSCX and SJX.

Logic Symbols

TL/F/9528–3

IEEE/IEC

TL/F/9528–6

Connection Diagram

Pin Assignment for

DIP and SOIC

TL/F/9528–1

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Unit Loading/Fan Out

74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

A0–A3A Operand Inputs 1.0/3.0 20 mA/b1.8 mA

B0–B3B Operand Inputs 1.0/3.0 20 mA/b1.8 mA

S0–S2Function Select Inputs 1.0/1.0 20 mA/b0.6 mA

CnCarry Input 1.0/4.0 20 mA/b2.4 mA

GCarry Generate Output (Active LOW) 50/33.3 b1 mA/20 mA

P Carry Propagate Output (Active LOW) 50/33.3 b1 mA/20 mA

F0–F3Function Outputs 50/33.3 b1 mA/20 mA

Functional Description

Signals applied to the Select inputs S0–S2determine the

mode of operation, as indicated in the Function Select Ta-

ble. An extensive listing of input and output levels is shown

in the Truth Table. The circuit performs the arithmetic func-

tions for either active HIGH or active LOW operands, with

output levels in the same convention. In the Subtract oper-

ating modes, it is necessary to force a carry (HIGH for active

HIGH operands, LOW for active LOW operands) into the Cn

input of the least significant package.

The Carry Generate (G) and Carry Propagate (P) outputs

supply input signals to the ’F182 carry lookahead generator

for expansion to longer word length, as shown in

Figure 1

Note that an ’F382 ALU is used for the most significant

package. Typical delays for

Figure 1

are given in

Figure 2

Function Select Table

Select Operation

S0S1S2

L L L Clear

H L L B Minus A

L H L A Minus B

H H L A Plus B

LLHA

HLHA

LHHAB

H H H Preset

HeHIGH Voltage Level

LeLOW Voltage Level

FIGURE 2. 16-Bit Delay Tabulation

Path Segment Toward Output

4, OVR

Aior Bito P 7.2 ns 7.2 ns

Pito Cna(’F182) 6.2 ns 6.2 ns

Cnto F 8.1 ns Ð

Cnor Cna4, OVR Ð 8.0 ns

Total Delay 21.5 ns 21.4 ns

TL/F/9528–4

FIGURE 1. 16-Bit Lookahead Carry ALU Expansion

Logic Diagram

TL/F/9528–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Truth Table

Inputs Outputs

Function S0S1S2CnAnBnF0F1F2F3G P

CLEAR L L L X X X LLLLLL

L L L HHHHHL

L L H LHHHLL

LHLLLLLHH

B Minus A H L L L H HHHHHHL

HL LLLLLHL

H L HHHHHLL

HHLHLLLHH

HHHLLLLHL

L L L HHHHHL

L LHLLLLHH

L H L LHHHLL

A Minus B L H L L H H HHHHHL

HL LLLLLHL

HLHHLLLHH

H H L HHHHLL

HHHLLLLHL

L L LLLLLHH

L L HHHHHHL

L H L HHHHHL

A Plus B H H L L H H L H H H L L

HL LHLLLHH

HLHLLLLHL

HHLLLLLHL

H H HHHHHLL

X L LLLLLHH

X L HHHHHHH

B L LH X H L HHHHHL

XHHLLLLLL

X L LLLLLHH

X L HHHHHHH

B H L H X H L HHHHHH

X H HHHHHHL

X L LLLLLLL

XLHLLLLHH

AB LHHXHLLLLLLL

X H HHHHHHL

X L L HHHHHH

X L HHHHHHH

PRESET H H H X H L HHHHHH

X H HHHHHHL

HIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

Absolute Maximum Ratings (Note 1)

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATEÉOutput b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Commercial 0§Ctoa

70§C

Supply Voltage

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.2 V Min IIN eb

18 mA

VOH Output HIGH 74F 10% VCC 2.5 V Min IOH eb

1mA

Voltage 74F 5% VCC 2.7 IOH eb

1mA

OL Output LOW 74F 10% VCC 0.5 V Min IOL e20 mA

Voltage

IIH Input HIGH 74F 5.0 mAVIN e2.7V

Current

IBVI Input HIGH Current 74F 7.0 mA Max VIN e7.0V

Breakdown Test

ICEX Output HIGH 74F 50 mA Max VOUT eVCC

Leakage Current

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.6 mA Max VIN e0.5V (Sn)

b1.8 mA Max VIN e0.5V (An,B

)

2.4 mA Max VIN e0.5V (Cn)

IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V

ICC Power Supply Current 59 89 mA Max

AC Electrical Characteristics

74F 74F

TAea

25§CTA,V

CC eCom

Symbol Parameter VCC ea

5.0V CLe50 pF Units

CLe50 pF

Min Typ Max Min Max

tPLH Propagation Delay 2.5 8.1 12.0 2.5 13.0 ns

tPHL Cnto Fi2.5 5.7 8.0 2.5 9.0

tPLH Propagation Delay 4.0 10.4 15.0 4.0 16.0 ns

tPHL Any A or B to Any F 3.5 8.2 11.0 3.5 12.0

tPLH Propagation Delay 4.5 8.3 20.5 4.5 21.5 ns

tPHL Sito Fi4.0 8.2 15.0 4.0 16.0

tPLH Propagation Delay 3.5 6.4 10.0 3.5 11.0 ns

tPHL Aior Bito G 3.5 6.8 10.0 3.0 11.0

tPLH Propagation Delay 2.5 7.2 10.5 2.5 11.5 ns

tPHL Aior Bito P 3.5 6.5 9.5 3.5 10.5

tPLH Propagation Delay 4.0 7.8 12.0 4.0 13.0 ns

tPHL Sito G or P 4.5 10.2 13.5 4.5 14.5

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 381 S C X

Temperature Range Family Special Variations

74FeCommercial X eDevices shipped in 13×reel

Device Type Temperature Range

CeCommercial (0§Ctoa

70§C)

Package Code

PePlastic DIP

SeSmall Outline SOIC JEDEC

SJ eSmall Outline SOIC EIAJ

Physical Dimensions inches (millimeters)

20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)

NS Package Number M20B

20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)

NS Package Number M20D

74F381 4-Bit Arithmetic Logic Unit

Physical Dimensions inches (millimeters) (Continued)

20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)

NS Package Number N20A

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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