Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com SGX5V1-1.2 Copyright (c) 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ii Altera Corporation Contents Chapter Revision Dates .......................................................................... vii About This Handbook .............................................................................. ix How to Contact Altera ............................................................................................................................. ix Typographic Conventions ....................................................................................................................... ix Section I. Stratix GX Device Family Data Sheet Revision History ....................................................................................................................... Section I-2 Chapter 1. Introduction to the Stratix GX Device Data Sheet Overview ................................................................................................................................................. Features ................................................................................................................................................... High-Speed I/O Interface Functional Description ........................................................................... FPGA Functional Description .............................................................................................................. 1-1 1-1 1-4 1-5 Chapter 2. Stratix GX Transceivers Transmitter Path ............................................................................................................................... 2-5 Receiver Path ................................................................................................................................... 2-13 Loopback Modes ............................................................................................................................ 2-26 BIST (Built-In Self Test) ................................................................................................................. 2-28 Stratix GX Clocking ........................................................................................................................ 2-30 Other Transceiver Features ................................................................................................................ 2-37 Individual Power-Down & Reset for the Transmitter & Receiver .......................................... 2-37 Voltage Reference Capabilities ..................................................................................................... 2-38 Hot-Socketing Capabilities ........................................................................................................... 2-39 Applications & Protocols Supported with Stratix GX Devices ..................................................... 2-39 Stratix GX Example Application Support ................................................................................... 2-39 High-Speed Serial Bus Protocols .................................................................................................. 2-40 Chapter 3. Source-Synchronous Signaling With DPA Introduction ............................................................................................................................................ 3-1 Stratix GX I/O Banks ....................................................................................................................... 3-1 Principles of SERDES Operation .................................................................................................... 3-1 DPA Block Overview ....................................................................................................................... 3-5 DPA Operation ............................................................................................................................... 3-10 Altera Corporation iii Contents Chapter 4. Stratix GX Architecture Logic Array Blocks ................................................................................................................................ 4-1 LAB Interconnects ............................................................................................................................ 4-1 LAB Control Signals ......................................................................................................................... 4-2 Logic Elements ....................................................................................................................................... 4-3 LUT Chain & Register Chain .......................................................................................................... 4-5 addnsub Signal ................................................................................................................................. 4-5 LE Operating Modes ........................................................................................................................ 4-5 Clear & Preset Logic Control ........................................................................................................ 4-10 MultiTrack Interconnect ..................................................................................................................... 4-11 TriMatrix Memory ............................................................................................................................... 4-18 Memory Modes ............................................................................................................................... 4-19 Parity Bit Support ........................................................................................................................... 4-21 Shift Register Support .................................................................................................................... 4-21 Memory Block Size ......................................................................................................................... 4-22 Independent Clock Mode .............................................................................................................. 4-40 Input/Output Clock Mode ........................................................................................................... 4-42 Read/Write Clock Mode ............................................................................................................... 4-44 Single-Port Mode ............................................................................................................................ 4-45 Digital Signal Processing Block ......................................................................................................... 4-46 Multiplier Block .............................................................................................................................. 4-52 Adder/Output Blocks ................................................................................................................... 4-56 Modes of Operation ....................................................................................................................... 4-59 DSP Block Interface ........................................................................................................................ 4-65 PLLs & Clock Networks ..................................................................................................................... 4-68 Global & Hierarchical Clocking ................................................................................................... 4-68 Enhanced & Fast PLLs ................................................................................................................... 4-76 Enhanced PLLs ............................................................................................................................... 4-82 Fast PLLs .......................................................................................................................................... 4-93 I/O Structure ........................................................................................................................................ 4-96 Double-Data Rate I/O Pins ......................................................................................................... 4-103 External RAM Interfacing ........................................................................................................... 4-107 Programmable Drive Strength ................................................................................................... 4-110 Open-Drain Output ...................................................................................................................... 4-111 Slew-Rate Control ........................................................................................................................ 4-112 Bus Hold ........................................................................................................................................ 4-112 Programmable Pull-Up Resistor ................................................................................................ 4-113 Advanced I/O Standard Support .............................................................................................. 4-113 Differential On-Chip Termination ............................................................................................. 4-118 MultiVolt I/O Interface ............................................................................................................... 4-120 Power Sequencing & Hot Socketing ............................................................................................... 4-121 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ........................................................................ 4-122 Chapter 5. Configuration & Testing SignalTap Embedded Logic Analyzer ................................................................................................ 5-1 Configuration ......................................................................................................................................... 5-1 Operating Modes .............................................................................................................................. 5-1 iv Stratix GX Device Handbook, Volume 1 Altera Corporation Contents Configuration Schemes ................................................................................................................... Partial Reconfiguration .................................................................................................................... Remote Update Configuration Modes .......................................................................................... Stratix GX Automated Single Event Upset (SEU) Detection ........................................................... Custom-Built Circuitry .................................................................................................................... Software Interface ............................................................................................................................. Temperature-Sensing Diode ................................................................................................................ 5-2 5-3 5-3 5-7 5-8 5-8 5-8 Chapter 6. DC & Switching Characteristics Operating Conditions ........................................................................................................................... 6-1 Power Consumption ........................................................................................................................... 6-22 Timing Model ....................................................................................................................................... 6-22 Preliminary & Final Timing .......................................................................................................... 6-23 Performance .................................................................................................................................... 6-23 Internal Timing Parameters .......................................................................................................... 6-26 External Timing Parameters ......................................................................................................... 6-35 External I/O Delay Parameters .................................................................................................... 6-44 Maximum Input & Output Clock Rates ...................................................................................... 6-54 High-Speed I/O Specification ........................................................................................................... 6-58 PLL Timing ...................................................................................................................................... 6-62 DLL Jitter ............................................................................................................................................... 6-68 Chapter 7. Reference & Ordering Information Software .................................................................................................................................................. 7-1 Device Pin-Outs ..................................................................................................................................... 7-1 Ordering Information ........................................................................................................................... 7-1 Altera Corporation v Stratix GX Device Handbook, Volume 1 Contents vi Stratix GX Device Handbook, Volume 1 Altera Corporation Chapter Revision Dates The chapters in this book, Stratix GX Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Introduction to the Stratix GX Device Data Sheet Revised: February 2005 Part number: SGX51001-1.0 Chapter 2. Stratix GX Transceivers Revised: June 2006 Part number: SGX51002-1.1 Chapter 3. Source-Synchronous Signaling With DPA Revised: August 2005 Part number: SGX51003-1.1 Chapter 4. Stratix GX Architecture Revised: February 2005 Part number: SGX51004-1.0 Chapter 5. Configuration & Testing Revised: February 2005 Part number: SGX51005-1.0 Chapter 6. DC & Switching Characteristics Revised: June 2006 Part number: SGX51006-1.2 Chapter 7. Reference & Ordering Information Revised: February 2005 Part number: SGX51007-1.0 Altera Corporation vii Chapter Revision Dates viii Stratix GX Device Handbook, Volume 1 Altera Corporation About This Handbook This handbook provides comprehensive information about the Altera(R) Stratix(R) GX family of devices. How to Contact Altera Information Type Technical support For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada All Other Locations www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time Product literature www.altera.com www.altera.com Altera literature services literature@altera.com literature@altera.com Non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time FTP site ftp.altera.com ftp.altera.com Typographic Conventions Visual Cue This document uses the typographic conventions shown below. Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Altera Corporation ix Preliminary Typographic Conventions Visual Cue Italic type Stratix GX Device Handbook, Volume 1 Meaning Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. "Subheading Title" References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. * v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. w The warning indicates information that should be read prior to starting or continuing the procedure or processes r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. x Preliminary Altera Corporation Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix(R) GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions, and AC timing parameters. This section includes the following chapters: Altera Corporation Chapter 1, Introduction to the Stratix GX Device Data Sheet Chapter 2, Stratix GX Transceivers Chapter 3, Source-Synchronous Signaling With DPA Chapter 4, Stratix GX Architecture Chapter 5, Configuration & Testing Chapter 6, DC & Switching Characteristics Chapter 7, Reference & Ordering Information Section I-1 Preliminary Stratix GX Device Family Data Sheet Revision History Chapter(s) Stratix GX Device Handbook, Volume 1 The table below shows the revision history for Chapters 1 through 7. Date / Version Changes Made 1 February 2005, v1.0 Initial Release. 2 June 2006, v1.1 Updated "Serial Loopback" section. Updated Figures 2-1 through 2-3. Updated Figure 2-13. Updated Figures 2-26 and 2-27. February 2005, v1.0 Initial Release. 3 August 2005, v1.1 Added Note (3) to Figure 3-7. 4 February 2005, v1.0 Initial Release. 5 February 2005, v1.0 Initial Release. 6 June 2006, v1.2 Comments Updated "Operating Conditions" section. Updated Table 6-4. Updated note 3 in Table 6-6. Added note 12 in Table 6-7. Updated Figure 6-1. Added Figure 6-2. Updated Tables 6-13 through 6-16. 7 Section I-2 Preliminary August 2005, v1.1 Updated Tables 6-7 and 6-50. February 2005, v1.0 Initial Release. Changed VO D to VI D for receiver input voltage and refclkb input voltage in Table 6-4. Changed value for undershoot during transition from -0.5 V to -2.0 V in note 3 of Table 6-6. Changed value of VO C M from mV to V in Table 6-15. Changed unit value of W to .. Altera Corporation 1. Introduction to the Stratix GX Device Data Sheet SGX51001-1.0 Overview The Stratix(R) GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.1875 gigabits per second (Gbps). These transceivers are grouped by four-channel transceiver blocks, and are designed for low power consumption and small die size. The Stratix GX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications. Features Altera Corporation February 2005 Transceiver block features are as follows: High-speed serial transceiver channels with CDR provides 500-megabits per second (Mbps) to 3.1875-Gbps full-duplex operation Devices are available with 4, 8, 16, or 20 high-speed serial transceiver channels providing up to 127.5 Gbps of full-duplex serial bandwidth Support for transceiver-based protocols, including 10 Gigabit Ethernet attachment unit interface (XAUI), Gigabit Ethernet (GigE), and SONET/SDH Compatible with PCI Express, SMPTE 292M, Fibre Channel, and Serial RapidIO I/O standards Programmable differential output voltage (VOD), pre-emphasis, and equalization settings for improved signal integrity Individual transmitter and receiver channel power-down capability implemented automatically by the Quartus(R) II software for reduced power consumption during non-operation Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, and 20-bit wide data paths 1.5-V pseudo current mode logic (PCML) for 500 Mbps to 3.1875 Gbps Support for LVDS, LVPECL, and 3.3-V PCML on reference clocks and receiver input pins (AC-coupled) Built-in self test (BIST) Hot insertion/removal protection circuitry 1-1 Features Pattern detector and word aligner supports programmable patterns 8B/10B encoder/decoder performs 8- to 10-bit encoding and 10to 8-bit decoding Rate matcher compliant with IEEE 802.3-2002 for GigE mode and with IEEE 802-3ae for XAUI mode Channel bonding compliant with IEEE 802.3ae (for XAUI mode only) Device can bypass some transceiver block features if necessary FPGA features are as follows: 10,570 to 41,250 logic elements (LEs); see Table 1-1 Up to 3,423,744 RAM bits (427,968 bytes) available without reducing logic resources TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in-out (FIFO) buffers Up to 16 global clock networks with up to 22 regional clock networks per device region High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to eight general usage phase-locked loops (four enhanced PLLs and four fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed source-synchronous differential I/O support on up to 45 channels for 1-Gbps performance Support for source-synchronous bus standards, including 10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV, Network Packet Streaming Interface (NPSI), HyperTransportTM technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4 Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for multiple intellectual property megafunctions from Altera(R) MegaCore(R) functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for remote configuration updates Dynamic phase alignment on LVDS receiver channels 1-2 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet Table 1-1. Stratix GX Device Features EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G 10,570 25,660 41,250 4, 8 4, 8, 16 8, 20 EP1SGX10C EP1SGX10D Feature LEs Transceiver channels Source-synchronous channels 22 39 45 M512 RAM blocks (32 x 18 bits) 94 224 384 M4K RAM blocks (128 x 36 bits) 60 138 183 M-RAM blocks (4K x144 bits) 1 2 4 Total RAM bits 920,448 1,944,576 3,423,744 Digital signal processing (DSP) blocks 6 10 14 Embedded multipliers (1) 48 80 112 PLLs 4 4 8 Note to Table 1-1: (1) This parameter lists the total number of 9- x 9-bit multipliers for each device. For the total number of 18- x 18-bit multipliers per device, divide the total number of 9- x 9-bit multipliers by 2. For the total number of 36- x 36-bit multipliers per device, decide the total number of 9- x 9-bit multipliers by 8. Stratix GX devices are available in space-saving FineLine BGA(R) packages (refer to Tables 1-2 and 1-3), and in multiple speed grades (refer to Table 1-4). Stratix GX devices support vertical migration within the same package (that is, you can migrate between the EP1SGX10C and EP1SGX25C devices in the 672-pin FineLine BGA package). See the Stratix GX device pin tables for more information. Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type, to identify which I/O pins it is possible to migrate. The Quartus II software can automatically cross reference and place all pins for migration when given a device migration list. Table 1-2. Stratix GX Package Options & I/O Pin Counts (Part 1 of 2) Note (1) Device Altera Corporation February 2005 672-Pin FineLine BGA EP1SGX10C 362 EP1SGX10D 362 EP1SGX25C 455 1,020-Pin FineLine BGA 1-3 Stratix GX Device Handbook, Volume 1 High-Speed I/O Interface Functional Description Table 1-2. Stratix GX Package Options & I/O Pin Counts (Part 2 of 2) Note (1) Device 672-Pin FineLine BGA 1,020-Pin FineLine BGA 455 607 EP1SGX25D EP1SGX25F 607 EP1SGX40D 624 EP1SGX40G 624 Note to Table 1-2: (1) The number of I/O pins listed for each package includes dedicated clock pins and dedicated fast I/O pins. However, these numbers do not include high-speed or clock reference pins for high-speed I/O standards. Table 1-3. Stratix GX FineLine BGA Package Sizes Dimension 672 Pin 1,020 Pin Pitch (mm) 1.00 1.00 (mm2) 729 1,089 27 x 27 33 x 33 Area Length x width (mm x mm) Table 1-4. Stratix GX Device Speed Grades Device EP1SGX10 -5, -6, -7 EP1SGX25 -5, -6, -7 EP1SGX40 High-Speed I/O Interface Functional Description 672-Pin FineLine BGA 1,020-pin FineLine BGA -5, -6, -7 -5, -6, -7 The Stratix GX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. The channels on the right side of the device use an embedded circuit dedicated for receiving and transmitting high-speed serial data streams to and from the system board. These channels are clustered in a four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to 3.1875 Gbps of full-duplex data transmission per channel. The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1-1 shows the Stratix GX I/O blocks. The differential source-synchronous serial interface and the high-speed serial interface are described in the Stratix GX Transceivers chapter of the Stratix GX Device Handbook, Volume 1. 1-4 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet Figure 1-1. Stratix GX I/O Blocks DQST9 PLL7 DQST8 DQST7 DQST6 Note (1) DQST5 9 DQST4 PLL11 DQST3 DQST2 DQST1 DQST0 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 10 Bank 4 I/O Bank 13 (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3) Bank 2 VREF1B2 VREF2B2 VREF3B2 VREF4B2 Bank 3 (4) I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2) I/O Banks 1 and 2 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x PLL1 Bank 1 PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1 PLL5 VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 I/O Bank 17 (5) 1.5-V PCML (5) I/O Bank 16 (5) I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2) (4) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3) I/O Bank 15 (5) Bank 8 PLL8 I/O Bank 14 (5) 11 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 DQSB9 DQSB8 DQSB7 DQSB6 DQSB5 12 PLL6 Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 DQSB4 DQSB3 DQSB2 DQSB1 DQSB0 Notes to Figure 1-1: (1) (2) (3) (4) (5) Figure 1-1 is a top view of the Stratix GX silicon die. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x. For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled). FPGA Functional Description Altera Corporation February 2005 Stratix GX devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. 1-5 Stratix GX Device Handbook, Volume 1 FPGA Functional Description The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device's logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 x 9-bit multipliers, four full-precision 18 x 18-bit multipliers, or one full-precision 36 x 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix GX device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1-2 shows an overview of the Stratix GX device. 1-6 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Introduction to the Stratix GX Device Data Sheet Figure 1-2. Stratix GX Block Diagram M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards IOEs IOEs IOEs IOEs LABs LABs LABs IOEs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs M-RAM Block LABs LABs DSP Block The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 1-5 lists the resources available in Stratix GX devices. Table 1-5. Stratix GX Device Resources Device M512 RAM M4K RAM Columns/Blocks Columns/Blocks M-RAM Blocks DSP Block Columns/Blocks LAB Columns LAB Rows EP1SGX10 4 / 94 2 / 60 1 2/6 40 30 EP1SGX25 6 / 224 3 / 138 2 2 / 10 62 46 EP1SGX40 8 / 384 3 / 183 4 2 / 14 77 61 Altera Corporation February 2005 1-7 Stratix GX Device Handbook, Volume 1 FPGA Functional Description 1-8 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 2. Stratix GX Transceivers SGX51002-1.1 Transceiver Blocks Stratix(R) GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 3.1875-Gbps serial transceiver channels. Each Stratix GX transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceiver block uses the channels to deliver bidirectional point-to-point data transmissions with up to 3.1875 Gbps of data transition per channel. There are up to 20 transceiver channels available on a single Stratix GX device. Table 2-1 shows the number of transceiver channels available on each Stratix GX device. Table 2-1. Stratix GX Transceiver Channels Device Number of Transceiver Channels EP1SGX10C 4 EP1SGX10D 8 EP1SGX25C 4 EP1SGX25D 8 EP1SGX25F 16 EP1SGX40D 8 EP1SGX40G 20 Figure 2-1 shows the elements of the transceiver block, including the four channels, supporting logic, and I/O buffers. Each transceiver channel consists of a receiver and transmitter. The supporting logic contains a transmitter PLL to generate a high-speed clock used by the four transmitters. The receiver PLL within each transceiver channel generates the receiver reference clocks. The supporting logic also contains state machines to manage rate matching for XAUI and GIGE applications, in addition to channel bonding for XAUI applications. Altera Corporation June 2006 2-1 Figure 2-1. Stratix GX Transceiver Block Note (1) Receiver Channel 0 PLD Logic Array Receiver Pins Channel 0 Transmitter Channel 0 Transmitter Pins Receiver Channel 1 PLD Logic Array Receiver Pins Channel 1 Transmitter Channel 1 PLD Logic Array XAUI Receiver State Machine XAUI Transmitter State Machine Channel Aligner State Machine Receiver Channel 2 PLD Logic Array Transmitter PLL PLD Logic Array (2) Receiver Pins Channel 2 Transmitter Channel 2 Receiver Channel 3 PLD Logic Array Transmitter Pins Transmitter Pins Receiver Pins Channel 3 Transmitter Channel 3 Transmitter Pins Notes to Figure 2-1: (1) (2) Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer to the section "Receiver Path" on page 2-13. For possible transmitter PLL clock inputs, refer to the section "Transmitter Path" on page 2-5. 2-2 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Each Stratix GX transceiver channel consists of a transmitter and receiver. The transmitter contains the following: Transmitter PLL Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel to serial converter) Transmitter output buffer The receiver contains the following: Input buffer Clock recovery unit (CRU) Deserializer Pattern detector and word aligner Rate matcher and channel aligner 8B/10B decoder Receiver logic array interface You can set all the Stratix GX transceiver functions through the Quartus II software. You can set programmable pre-emphasis, programmable equalizer, and programmable VOD dynamically as well. Each Stratix GX transceiver channel is also capable of BIST generation and verification in addition to various loopback modes. Figure 2-2 shows the block diagram for the Stratix GX transceiver channel. Stratix GX transceivers provide physical coding sublayer (PCS) and physical media attachment (PMA) implementation for protocols such as 10-gigabit XAUI and GIGE. The PCS portion of the transceiver consists of the logic array interface, 8B/10B encoder/decoder, pattern detector, word aligner, rate matcher, channel aligner, and the BIST and pseudo-random binary sequence pattern generator/verifier. The PMA portion of the transceiver consists of the serializer/deserializer, the CRU, and the I/O buffers. Altera Corporation June 2006 2-3 Stratix GX Device Handbook, Volume 1 (1) 2-4 Stratix GX Device Handbook, Volume 1 To Channels 1-3 Transmitter Receiver Reference Clock Receiver Channel 0 Transmitter Reference Clock Transmitter PLL Serializer Receiver PLL Clock Recovery Unit Deserializer Word Aligner Channel Aligner 8B/10B Encoder Rate Matcher 8B/10B Decoder Byte Serializer Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO Figure 2-2. Stratix GX Transceiver ChanneL Note (1) Note to Figure 2-2: There are four transceiver channels in a transceiver block. Altera Corporation June 2006 Stratix GX Transceivers Transmitter Path This section describes the data path through the Stratix GX transmitter (see Figure 2-2). Data travels through the Stratix GX transmitter via the following modules: Transmitter PLL Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel to serial converter) Transmitter output buffer Transmitter PLL Each transceiver block has one transmitter PLL, which receives the reference clock and generates the following signals: High-speed serial clock used by the serializer Slow-speed reference clock used by the receiver Slow-speed clock used by the logic array (divisible by two for double-width mode) The INCLK clock is the input into the transmitter PLL. There is one INCLK clock per transceiver block. This clock can be fed by either the REFCLKB pin, PLD routing, or the inter-transceiver routing line. See the section "Stratix GX Clocking" on page 2-30 for more information about the intertransceiver lines. The transmitter PLL in each transceiver block clocks the circuits in the transmit path. The transmitter PLL is also used to train the receiver PLL. If no transmit channels are used in the transceiver block, the transmitter PLL can be turned off. Figure 2-3 is a block diagram of the transmitter PLL. Altera Corporation June 2006 2-5 Stratix GX Device Handbook, Volume 1 Low Speed Clock Note (1) Up Down Dedicated Local REFCLKB Inter Quad Routing (IQ1) Inter Quad Routing (IQ0) Global Clks, IO Bus, Gen Routing /2 INCLK PFD /m Charge Pump + Loop Filter VCO Clock Driver High Speed Clock Figure 2-3. Transmitter PLL Block Diagram Note to Figure 2-3: (1) The divider in the PLL divides by 4, 8, 10, 16, or 20. 2-6 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers The transmitter PLL can support up to 3.1875 Mbps. The input clock frequency for -5 and -6 speed grade devices is limited to 650 MHz if you use the REFCLKB pin or to 325 MHz if you use the other clock routing resources. For -7 speed grade devices, the maximum input clock frequency is 312.5 MHz with the REFCLKB pin, and the maximum is 156.25 MHz for all other clock routing resources. An optional PLL_LOCKED port is available to indicate whether the transmitter PLL is locked to the reference clock. The transmitter PLL has a programmable loop bandwidth that can be set to low or high. The loop bandwidth parameter can be statically set in the Quartus II software. Table 2-2 lists the adjustable parameters in the transmitter PLL. Table 2-2. Transmitter PLL Specifications Parameter Specifications Input reference frequency range 25 MHz to 650 MHz Data rate support 500 Mbps to 3.1875 Gbps Multiplication factor (W) 2, 4, 5, 8, 10, 16, or 20 (1) Bandwidth Low, high Note to Table 2-2: (1) Multiplication factors 2 and 5 can only be achieved with the use of the pre-divider on the REFCLKB pin. Transmitter Phase Compensation FIFO Buffer The transmitter phase compensation FIFO buffer resides in the transceiver block at the PLD boundary. This FIFO buffer compensates for the phase differences between the transmitter reference clock (inclk) and the PLD interface clock (tx_coreclk). The phase difference between the two clocks must be less than 360 . The PLD interface clock must also be frequency locked to the transmitter reference clock. The phase compensation FIFO buffer is four words deep and cannot be bypassed. Byte Serializer The byte serializer takes double-width words (16 or 20 bits) from the PLD interface and converts them to a single width word (8 or 10 bits) for use in the transceiver. The transmit data path after the byte serializer is single width (8 or 10 bits). The byte serializer is bypassed when single width mode (8 or 10 bits) is used at the PLD interface. Altera Corporation June 2006 2-7 Stratix GX Device Handbook, Volume 1 8B/10B Encoder The 8B/10B encoder translates 8-bit wide data + 1 control enable bit into a 10-bit encoded data. The encoded data has a maximum run length of 5. The 8B/10B encoder can be bypassed. Figure 2-4 diagrams the encoding process. Figure 2-4. Encoding Process 7 6 5 4 3 2 1 0 H G F E D C B A + ctrl 8b-10b conversion j h g f i e d c b a 9 8 7 6 5 4 3 2 1 0 MSB sent last LSB sent first Transmit State Machine The transmit state machine operates in either XAUI mode or in GIGE mode, depending on the protocol used. GIGE Mode In GIGE mode, the transmit state machines convert all idle ordered sets (/K28.5/, /Dx.y/) to either /I1/ or /I2/ ordered sets. /I1/ consists of a negative-ending disparity /K28.5/ (denoted by /K28.5/-) followed by a neutral /D5.6/. /I2/ consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines do not convert any of the ordered sets to match /C1/ or /C2/, which are the configuration ordered sets. (/C1/ and /C2/ are defined by (/K28.5/, /D21.5/) and (/K28.5/, /D2.2/), respectively.) Both the /I1/ and /I2/ ordered sets guarantee a negative-ending disparity after each ordered set. The GIGE transmit state machine can be statically disabled in the Quartus II software, even if using the GIGE protocol mode. 2-8 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers XAUI Mode The transmit state machine translates the XAUI XGMII code group to the XAUI PCS code group. Table 2-3 shows the code conversion. Table 2-3. Code Conversion XGMII TXC XGMII TXD PCS Code-Group Description 0 00 through FF Dxx.y Normal data 1 07 K28.0 or K28.3 or K28.5 Idle in ||I|| 1 07 K28.5 Idle in ||T|| 1 9C K28.4 Sequence 1 FB K27.7 Start 1 FD K29.7 Terminate 1 FE K30.7 1 See IEEE 802.3 See IEEE 802.3 reserved code reserved code groups groups Reserved code groups 1 Other value Invalid XGMII character Error K30.7 The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically randomized based on a PRBS7 pattern with an x7+x6+1 polynomial. The /K28.3/ (/A/) code group is automatically generated between 16 and 31 idle code groups. The idle randomization on the /A/, /K/, and /R/ code groups are done automatically by the transmit state machine. Serializer (Parallel-to-Serial Converter) The serializer converts the parallel 8-bit or 10-bit data into a serial stream, transmitting the LSB first. The serialized stream is then fed to the transmit buffer. Figure 2-5 is a diagram of the serializer. Altera Corporation June 2006 2-9 Stratix GX Device Handbook, Volume 1 Figure 2-5. Serializer 10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Serial data out (to output buffer) Low-speed parallel clock High-speed serial clock Transmit Buffer The Stratix GX transceiver buffers support the 1.5-V pseudo current mode logic (PCML) I/O standard at a rate up to 3.1875 Gbps, across up to 40 inches of FR4 trace, and across 2 connectors. Additional I/O standards, LVDS, 3.3-V PCML, LVPECL, can be supported when AC coupled. The common mode of the output driver is 750 mV. The output buffer, as shown in Figure 2-6, consists of a programmable output driver and a programmable pre-emphasis circuit. 2-10 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-6. Output Buffer Serializer Output Buffer Programmable Pre-Emphasis Programmable Termination Programmable Output Driver Output Pins Programmable Output Driver The programmable output driver can be set to drive out 400 to 1,600 mV. Table 2-4 shows the available settings for each termination value. The VOD can be dynamically or statically set. The output driver requires either internal or external termination at the source. Table 2-4. Programmable VOD (Differential) Termination Setting () Note (1) VO D Setting (mV) 100 400, 800, 1000, 1200, 1400, 1600 120 480, 960, 1200, 1440 150 600, 1200, 1500 Note to Table 2-4: (1) Altera Corporation June 2006 VOD differential is measured as VA - VB (see Figure 2-7). 2-11 Stratix GX Device Handbook, Volume 1 Figure 2-7. VOD Differential Single-Ended Waveform Positive Channel (p) = VOH VID Negative Channel (n) = VOL VCM Ground Differential Waveform (VID (Differential) = 2 x VID (single-ended)) VID p-n=0V VID Programmable Pre-Emphasis The programmable pre-emphasis module controls the output driver to boost the high frequency components, to compensate for losses in the transmission medium, as shown in Figure 2-8. The pre-emphasis can be dynamically or statically set. There are five possible pre-emphasis settings (1 through 5), with 5 being the highest and 0 being no pre-emphasis. Figure 2-8. Programmable Pre-Emphasis Model VPP VS VCM VS(p-p) VPP(p-p) Bit Time 2-12 Stratix GX Device Handbook, Volume 1 Bit Time Altera Corporation June 2006 Stratix GX Transceivers Pre-emphasis percentage is defined as VPP/VS - 1, where VPP is the differential emphasized voltage (peak-to-peak) and VS is the differential steady-state voltage (peak-to-peak). Programmable Transmitter Termination The programmable termination can be statically set in the Quartus II software. The values are 100 , 120 , 150 , and off. Figure 2-9 shows the setup for programmable termination. Figure 2-9. Programmable Transmitter Termination 50, 60, or 75 9 VCM Programmable Output Driver Receiver Path This section describes the data path through the Stratix GX receiver (refer to Figure 2-2 on page 2-4). Data travels through the Stratix GX receiver via the following modules: Input buffer Clock Recovery Unit (CRU) Deserializer Pattern detector and word aligner Rate matcher and channel aligner 8B/10B decoder Receiver logic array interface Receiver Input Buffer The Stratix GX receiver input buffer supports the 1.5-V PCML I/O standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS, 3.3-V PCML, and LVPECL can be supported when AC coupled. The common mode of the input buffer is 1.1 V. The receiver can support Stratix GX-to-Stratix GX DC coupling. Altera Corporation June 2006 2-13 Stratix GX Device Handbook, Volume 1 Figure 2-10 shows a diagram of the receiver input buffer, which contains: Programmable termination Programmable equalizer Figure 2-10. Receiver Input Buffer Programmable Termination Input Pins Programmable Equalizer Differential Input Buffer Programmable Termination The programmable termination can be statically set in the Quartus II software. Figure 2-11 shows the setup for programmable receiver termination. Figure 2-11. Programmable Receiver Termination Differential Input Buffer 50, 60, or 75 VCM 50, 60, or 75 If you use external termination, then the receiver must be externally terminated and biased to 1.1 V. Figure 2-12 shows an example of an external termination/biasing circuit. 2-14 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-12. External Termination & Biasing Circuit Receiver External Termination and Biasing Stratix GX Device VDD 50/60/75- Termination Resistance R1 C1 Receiver R1/R2 = 1K VDD x {R2/(R1 + R 2)} = 1.1 V RXIP R2 RXIN Receiver External Termination and Biasing Transmission Line Programmable Equalizer The programmable equalizer module boosts the high frequency components of the incoming signal to compensate for losses in the transmission medium. There are five possible equalization settings (0, 1, 2, 3, 4) to compensate for 0", 10", 20", 30", and 40" of FR4 trace. These settings should be interpreted loosely. The programmable equalizer can be set dynamically or statically. Receiver PLL & CRU Each transceiver block has four receiver PLLs and CRUs, each of which is dedicated to a receive channel. If the receive channel associated with a particular receiver PLL or CRU is not used, then the receiver PLL or CRU is powered down for the channel. Figure 2-13 is a diagram of the receiver PLL and CRU circuits. Altera Corporation June 2006 2-15 Stratix GX Device Handbook, Volume 1 Figure 2-13. Receiver PLL & CRU Circuit Receiver PLL / m (1) rx_locked PFD Low-Speed TX_PLL_CLK Inter Transceiver Routing (IQ2) RX CRUCLK up down up down Charge Pump and Loop Filter VCO Global Clks, IO Bus, Gen Routing Dedicated Local REFCLKB /2 rx_locktorefclk rx_freqlocked[] CRU rx_locktodata rx_riv[ ] High-speed RCVD_CLK RX_IN Low-speed RCVD_CLK Note to Figure 2-13: (1) m = 8, 10 16, or 20. The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps. The input clock frequency for -5 and -6 speed grade devices is limited to 650 MHz if you use the REFCLKB pin or 325 MHz if you use the other clock routing resources. The maximum input clock frequency for -7 speed grade devices is 312.5 MHz if you use the REFCLKB pin or 156.25 MHz with the other clock routing resources. An optional RX_LOCKED port (active low signal) is available to indicate whether the PLL is locked to the reference clock. The receiver PLL has a programmable loop bandwidth, which can be set to low, medium, or high. The loop bandwidth parameter can be statically set by the Quartus II software. Table 2-5 lists the adjustable parameters of the receiver PLL and CRU. All the parameters listed are statically programmable in the Quartus II software. Table 2-5. Receiver PLL & CRU Adjustable Parameters (Part 1 of 2) Parameter Input reference frequency range Data rate support 2-16 Stratix GX Device Handbook, Volume 1 Specifications 25 MHz to 650 MHz 500 Mbps to 3.1875 Gbps Altera Corporation June 2006 Stratix GX Transceivers Table 2-5. Receiver PLL & CRU Adjustable Parameters (Part 2 of 2) 2, 4, 5, 8, 10, 16, or 20 (1) Multiplication factor (W) PPM detector 125, 250, 500, 1,000 Bandwidth Low, medium, high Run length detector 10-bit or 20-bit mode: 5 to 160 in steps of 5 8-bit or 16-bit mode: 4 to 128 in steps of 4 Note to Table 2-5: (1) Multiplication factors 2, 4, and 5 can only be achieved with the use of the predivider on the REFCLKB port or if the CRU is trained with the low speed clock from the transmitter PLL. The CRU has a built-in switchover circuit to select whether the voltage-controlled oscillator of the PLL is trained by the reference clock or the data. The optional port rx_freqlocked monitors when the CRU is in locked to data mode. In the automatic mode, the following conditions must be met for the CRU to switch from locked to reference to locked to data mode: The CRU PLL is within the prescribed PPM frequency threshold setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU reference clock. The reference clock and CRU PLL output are phase matched (phases are within .08 UI). The automatic switchover circuit can be overridden by using the optional ports rx_lockedtorefclk and rx_locktodata. Table 2-6 shows the possible combinations of these two signals. Table 2-6. Possible Combinations of rx_lockedtorefclk & rx_locktodata rx_locktodata rx_lockedtorefclk VCO (lock to mode) 0 0 Auto 0 1 Reference CLK 1 x DATA If the rx_lockedtorefclk and rx_locktodata ports are not used, the default is auto mode. Altera Corporation June 2006 2-17 Stratix GX Device Handbook, Volume 1 Deserializer (Serial-to-Parallel Converter) The deserializer converts the serial stream into a parallel 8- or 10-bit data bus. The deserializer receives the least significant bit first. Figure 2-14 is a diagram of the deserializer. Figure 2-14. Deserializer D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 10 High-speed serial clock Low-speed parallel clock Word Aligner The word aligner aligns the incoming data based on the specific byte boundaries. The word aligner has three customizable modes of operation: bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available for the basic and SONET modes. The word aligner also has two non-customizable modes of operation, which are the XAUI and GIGE modes. Figure 2-15 shows the word aligner in bit-slip mode. 2-18 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-15. Word Aligner in Bit-Slip Mode Word Aligner Manual Alignment Mode Patterm Detector Bit-Slip Mode 10-Bit Mode 16-Bit Mode A1A2 Mode 7-Bit Mode A1A1A2A2 Mode In the bit-slip mode, the byte boundary can be modified by a barrel shifter to slip the byte boundary one bit at a time via a user-controlled bit-slip port. The bit-slip mode supports both 8-bit and 10-bit data paths operating in a single or double-width mode. The pattern detector is active in the bit-slip mode, and it detects the user-defined pattern that is specified in the MegaWizard(R) Plug-In Manager. The bit-slip mode is available only in Custom mode and SONET mode. Figure 2-16 shows the word aligner in 16-bit mode. Altera Corporation June 2006 2-19 Stratix GX Device Handbook, Volume 1 Figure 2-16. Word Aligner in 16-Bit Mode Word Aligner Manual Alignment Mode Pattern Detector 16-Bit Mode A1A2 Mode 16-Bit Mode A1A1A2A2 Mode A1A2 Mode A1A1A2A2 Mode In the 16-bit mode, the word aligner and pattern detector automatically aligns and detects a user-defined 16-bit alignment pattern. This pattern can be in the format of A1A2 or A1A1A2A2 (for the SONET protocol). The re-alignment of the byte boundary can be done via a user-controlled port. The 16-bit mode supports only the 8-bit data path in a single-width or double-width mode. The 16-bit mode is available only for the Custom mode and SONET mode. The A1A1A2A2 word alignment pattern option is available only for the SONET mode and cannot be used in the Custom mode. Figure 2-17 shows the word aligner in 10-bit mode. 2-20 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-17. Word Aligner in 10-Bit Mode Word Aligner Manual Alignment Mode Pattern Detector 10-Bit Mode 7-Bit Mode 10-Bit Mode In the 10-bit mode, the word aligner automatically aligns the user's predefined 10-bit alignment pattern. The pattern detector can detect the full 10-bit pattern or only the lower seven bits of the pattern. The word aligner and pattern detector detect both the positive and the negative disparity of the pattern. A user-controlled enable port is available for the word aligner. The 10-bit mode is available only for the Custom mode. Figure 2-18 shows the word aligner in XAUI mode. Altera Corporation June 2006 2-21 Stratix GX Device Handbook, Volume 1 Figure 2-18. Word Aligner in XAUI Mode Word Aligner Synchronization State Machines GigE Mode XAUI Mode In the XAUI and GIGE modes, the word alignment is controlled by a state machine that adheres to the IEEE 802.3ae standard for XAUI and the IEEE 802.3 standard for GIGE. The alignment pattern is predefined to be a /K28.5/ code group. The XAUI mode is available only for the XAUI protocol, and the GIGE mode is available only for the GIGE protocol. Channel Aligner The channel aligner is available only in XAUI mode and bonds all four channels within a transceiver. The channel aligner adheres to the IEEE 802.3ae, clause 48 specification for channel bonding. The channel aligner is a 16-word deep FIFO buffer with a state machine overlooking the channel bonding process. The state machine looks for an /A/ (/K28.3/) in each channel and aligns all the /A/s in the transceiver. When four columns of /A/ (denoted by //A//) are detected, the rx_channelalign port goes high, signifying that all the channels in the transceiver have been bonded. The reception of four consecutive misaligned /A/s restarts the channel alignment sequence and de-asserts rx_channelalign. Figure 2-19 shows misaligned channels before the channel aligner and the channel alignment after the channel aligner. 2-22 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-19. Before & After the Channel Aligner Lane 0 K K R A K R R K K R K R K K R A K R R K K R K K R A K R R K K R K R Lane 0 Lane 0 K Lane 0 K K R A K R R K K R K Lane 0 K K R A K R R K K R K R Lane 0 K K R A K R R K K R K R Lane 0 K K R A K R R K K R K R Lane 0 K K R A K R R K K R K R R R Rate Matcher The rate matcher, which is available only in XAUI and GIGE modes, consists of a 12-word deep FIFO buffer and a FIFO controller. The rate matcher is bypassed when the device is not in XAUI or GIGE mode. In a multi-crystal environment, the rate matcher compensates for up to a 100-ppm difference between the source and receiver clocks. GIGE Mode In the GIGE mode, the rate matcher adheres to the specifications in clause 36 of the IEEE 802.3 documentation, for idle additions or removals. The rate matcher performs clock compensation only on /I2/ ordered sets, composing a /K28.5/+ followed by a /D16.2/-. The rate matcher does not perform a clock compensation on any other ordered set combinations. An /I2/ is added or deleted automatically based on the number of words in the FIFO buffer. A 9'h19C is given at the control and data ports when the FIFO is in an overflow or underflow condition. Altera Corporation June 2006 2-23 Stratix GX Device Handbook, Volume 1 XAUI Mode In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification for clock rate compensation. The rate matcher performs clock compensation on columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted automatically based on the number of words in the FIFO buffer. 8B/10B Decoder The 8B/10B decoder converts the 10-bit encoded code group into 8-bit data and 1 control bit. The 8B/10B decoder can be bypassed. The following is a diagram of the conversion from a 10-bit encoded code group into 8-bit data + 1-bit control. Figure 2-20. 8B/10B Decoder Conversion j h g f i e d c b a 9 8 7 6 5 4 3 2 1 0 MSB received last LSB received first 8b-10b conversion Parallel data 7 6 5 4 3 2 1 0 H G F E D C B A + ctrl There are two optional error status ports available in the 8B/10B decoder, rx_errdetect and rx_disperr. Table 2-7 shows the values of the ports from a given error. These status signals are aligned with the code group in which the error occurred. Table 2-7. Error Signal Values Types of Errors rx_errdetect rx_disperr No errors 1'b0 1'b0 Invalid code groups 1'b1 1'b0 Disparity errors 1'b1 1'b1 2-24 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Receiver State Machine The receiver state machine operates in GIGE and XAUI modes. In GIGE mode, the receiver state machine replaces invalid code groups with 9'h1FE. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group. Table 2-8 shows the code conversion. The conversion adheres to the IEEE 802.3ae specification. Table 2-8. Code Conversion XGMII RXC XGMII RXD PCS code-group Description 0 00 through FF Dxx.y Normal Data 1 07 K28.0 or K28.3 or K28.5 Idle in ||I|| 1 07 K28.5 Idle in ||T|| 1 9C K28.4 Sequence 1 FB K27.7 Start 1 FD K29.7 Terminate 1 FE K30.7 Error 1 FE Invalid code group Invalid XGMII character 1 See IEEE 802.3 reserved code groups See IEEE 802.3 reserved code groups Reserved code groups Byte Deserializer The byte deserializer takes a single width word (8 or 10 bits) from the transceiver logic and converts it into double-width words (16 or 20 bits) to the phase compensation FIFO buffer. The byte deserializer is bypassed when single width mode (8 or 10 bits) is used at the PLD interface. Phase Compensation FIFO Buffer The receiver phase compensation FIFO buffer resides in the transceiver block at the programmable logic device (PLD) boundary. This buffer compensates for the phase difference between the recovered clock within the transceiver and the recovered clock after it has transferred to the PLD core. The phase compensation FIFO buffer is four words deep and cannot be bypassed. Altera Corporation June 2006 2-25 Stratix GX Device Handbook, Volume 1 Loopback Modes The Stratix GX transceiver has built-in loopback modes to aid in debug and testing. The loopback modes are set in the Stratix GX MegaWizard Plug-In Manager in the Quartus II software. Only one loopback mode can be set at any single instance of the transceiver block. The loopback mode applies to all used channels in a transceiver block. The available loopback modes are: Serial loopback Parallel loopback Reverse serial loopback Serial Loopback Serial loopback exercises all the transceiver logic except for the output buffer and input buffer. The loopback function is dynamically switchable through the rx_slpbk port on a channel by channel basis. The VOD of the output reduced. If you select 400 mV, the output is tri-stated when the serial loopback option is selected. Figure 2-21 shows the data path in serial loopback mode. Figure 2-21. Data Path in Serial Loopback Mode BIST PRBS Verifier Word Aligner Deserializer BIST Incremental Verifier Channel Aligner Rate Matcher Clock Recovery Unit Serializer Active Path Non-Active Path 8B/10B Encoder 8B/10B Decoder Byte Serializer Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO BIST Generator BIST PRBS Generator 2-26 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Parallel Loopback The parallel loopback mode exercises the digital logic portion of the transceiver data path. The analog portions are not use in the loopback path. The received data is not retimed. Figure 2-22 shows the data path in parallel loopback mode. This option is not dynamically switchable. Reception of an external signal is not possible in this mode. Figure 2-22. Data Path in Parallel Loopback Mode BIST PRBS Verifier Word Aligner Deserializer BIST Incremental Verifier Channel Aligner Rate Matcher Clock Recovery Unit Serializer Active Path Non-Active Path 8B/10B Encoder 8B/10B Decoder Byte Serializer Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO BIST Generator BIST PRBS Generator Reverse Serial Loopback The reverse serial loopback exercises the analog portion of the transceiver. This loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. Asserting rxanalogreset in reverse serial loopback mode powers down the receiver buffer and CRU, preventing data loopback. Figure 2-23 shows the data path in reverse serial loopback mode. Altera Corporation June 2006 2-27 Stratix GX Device Handbook, Volume 1 Figure 2-23. Data Path in Reverse Serial Loopback Mode BIST PRBS Verifier Deserializer Word Aligner Channel Aligner BIST Incremental Verifier Rate Matcher Clock Recovery Unit Serializer 8B/10B Encoder Active Path 8B/10B Decoder Byte Serializer Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO BIST Generator BIST PRBS Generator Non-Active Path BIST (Built-In Self Test) The Stratix GX transceiver has built-in self test modes to aid in debug and testing. The BIST modes are set in the Stratix GX MegaWizard Plug-In Manager in the Quartus II software. Only one BIST mode can be set for any single instance of the transceiver block. The BIST mode applies to all channels used in a transceiver. The following is a list of the available BIST modes: PRBS generator and verifier Incremental mode generator and verifier High-frequency generator Low-frequency generator Mixed-frequency generator Figures 2-24 and 2-25 are diagrams of the BIST PRBS data path and the BIST incremental data path, respectively. 2-28 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-24. BIST PRBS Data Path BIST PRBS Verifier Word Aligner Deserializer BIST Incremental Verifier Channel Aligner Rate Matcher Clock Recovery Unit Serializer Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO Byte Serializer 8B/10B Encoder Active Path 8B/10B Decoder BIST Generator BIST PRBS Generator Non-active Path Figure 2-25. BIST Incremental Data Path BIST PRBS Verifier Word Aligner Deserializer BIST Incremental Verifier Channel Aligner Rate Matcher Clock Recovery Unit Serializer 8B/10B Encoder Active Path 8B/10B Decoder Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO Byte Serializer BIST Generator BIST PRBS Generator Non-active Path Table 2-9 shows the BIST data output and verifier alignment pattern. Table 2-9. BIST Data Output & Verifier Alignment Pattern (Part 1 of 2) BIST Mode Output Polynomials Verifier Word Alignment Pattern PRBS 8-bit 28 - 1 x8 + x7 + x5 + x3 + 1 1000000011111111 PRBS 10-bit 210 - 1 x10 + x7 + 1 1111111111 Altera Corporation June 2006 2-29 Stratix GX Device Handbook, Volume 1 Table 2-9. BIST Data Output & Verifier Alignment Pattern (Part 2 of 2) BIST Mode Output Polynomials Verifier Word Alignment Pattern PRBS 16-bit 28 - 1 x8 + x7 + x5 + x3 + 1 1000000011111111 PRBS 20-bit 210 - 1 x10 + x7 + 1 1111111111 Incremental 10-bit K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1) 0101111100 (K28.5) Incremental 20-bit K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1) 0101111100 (K28.5) High frequency 1010101010 Low frequency 0011111000 Mixed frequency 0011111010 or 1100000101 Note to Table 2-9: (1) This output repeats. Stratix GX Clocking The Stratix GX global clock can be driven by certain REFCLKB pins, all transmitter PLL outputs, and all receiver PLL outputs. The REFCLKB pins (except for transceiver block 0 and transceiver block 4) can drive intertransceiver and global clock lines as well as feed the transmitter and receiver PLLs. The output of the transmitter PLL can only feed global clock lines and the reference clock port of the receiver PLL. Figures 2-26 and 2-27 are diagrams of the Inter-Transceiver line connections as well as the global clock connections for the EP1SGX25F and EP1SGX40G devices. For devices with fewer transceivers, ignore the information about the unavailable transceiver blocks. 2-30 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-26. EP1SGX25F Device Inter-Transceiver & Global Clock Connections Note (1) Transceiver Block 0 IQ0 IQ1 Global Clocks, I/O Bus, General Routing Transmitter PLL refclkb /2 IQ0 IQ1 IQ2 IQ2 Global Clocks, I/O Bus, General Routing 4 Receiver PLLs 4 Transceiver Block 1 IQ0 IQ1 Global Clocks, I/O Bus, General Routing Transmitter PLL refclkb (2) /2 IQ2 Global Clocks, I/O Bus, General Routing 4 Receiver PLLs 4 16 Transceiver Block 2 PLD Global Clocks IQ0 IQ1 Global Clocks, I/O Bus, General Routing Transmitter PLL refclkb (2) /2 IQ2 Global Clocks, I/O Bus, General Routing 4 Receiver PLLs 4 Transceiver Block 3 IQ0 IQ1 Global Clocks, I/O Bus, General Routing refclkb Transmitter PLL (2) /2 IQ2 Global Clocks, I/O Bus, General Routing 4 Receiver PLLs 4 Notes to Figure 2-26: (1) (2) (3) IQ lines are inter-transceiver block lines. If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed. There are four receiver PLLs in each transceiver block. Altera Corporation June 2006 2-31 Stratix GX Device Handbook, Volume 1 Figure 2-27. EP1SGX40G Device Inter-Transceiver & Global Clock Connections Note (1) Transceiver Block 0 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL refclkb /2 IQ2 Global Clks, I/O Bus, Gen Routing 4 Receiver PLLs 4 Transceiver Block 1 IQ0 IQ1 IQ2 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL refclkb (2) /2 IQ2 Global Clks, I/O Bus, Gen Routing 4 Receiver PLLs 4 PLD Global Clocks Transceiver Block 4 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL 16 refclkb /2 IQ2 Global Clks, I/O Bus, Gen Routing 4 Receiver PLLs 4 Transceiver Block 2 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL refclkb (2) /2 IQ2 Global Clks, I/O Bus, Gen Routing 4 Receiver PLLs 4 Transceiver Block 3 IQ0 IQ1 Global Clks, I/O Bus, Gen Routing TX PLL refclkb (2) /2 IQ2 Global Clks, I/O Bus, Gen Routing 4 Receiver PLLS 4 Notes to Figure 2-27: (1) (2) (3) IQ lines are inter-transceiver block lines. If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed. There are four receiver PLLs in each transceiver block. 2-32 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers The receiver PLL can also drive the fast regional, regional clocks, and local routing adjacent to the associated transceiver block. Figures 2-28 through 2-31 show which fast regional and regional clock resource can be used by the recovered clock. In the EP1SGX25 device, the receiver PLL recovered clocks from transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2 and 3 drive RCLK[7..6]. The regional clocks feed logic in their associated regions. Figure 2-28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock Connection PLD Stratix GX Transceiver Blocks Block 0 RCLK[11..10] Block 1 Block 2 RCLK[9..8] Block 3 In addition, the receiver PLL's recovered clocks can drive fast regional lines (FCLK) as shown Figure 2-29. The fast regional clocks can feed logic in their associated regions. Altera Corporation June 2006 2-33 Stratix GX Device Handbook, Volume 1 Figure 2-29. EP1SGX25 Receiver PLL Recovered Clock to Fast Regional Clock Connection PLD FCLK[1..0] Stratix GX Transceiver Blocks Block 0 Block 1 Block 2 Block 3 FCLK[1..0] In the EP1SGX40 device, the receiver PLL recovered clocks from transceivers 0 and 1 drive RCLK[1..0] while transceivers 2, 3, and 4 drive RCLK[7..6]. The regional clocks feed logic in their associated regions. 2-34 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers Figure 2-30. EP1SGX40 Receiver PLL Recovered Clock to Regional Clock Connection PLD Stratix GX Transceiver Blocks Block 0 RCLK[11..10] Block 1 Block 4 Block 2 RCLK[9..8] Block 3 Figure 2-31 shows the possible recovered clock connection to the fast regional clock resource. The fast regional clocks can drive logic in their associated regions. Altera Corporation June 2006 2-35 Stratix GX Device Handbook, Volume 1 Figure 2-31. EP1SGX40 Receiver PLL Recovered Clock to Fast Regional Clock Connection Stratix GX FCLK[1..0] Transceiver Blocks PLD Block 0 Block 1 Block 4 Block 2 Block 3 FCLK[1..0] Table 2-10 summarizes the possible clocking connections for the transceivers. Table 2-10. Possible Clocking Connections for Transceivers (Part 1 of 2) Destination Source REFCLKB Transmitter PLL Receiver PLL GCLK RCLK v v (1) v v v v v v v v v Transmitter PLL Receiver PLL GCLK v v RCLK v v FCLK v v 2-36 Stratix GX Device Handbook, Volume 1 FCLK IQ Lines v (1) Altera Corporation June 2006 Stratix GX Transceivers Table 2-10. Possible Clocking Connections for Transceivers (Part 2 of 2) Destination Source IQ lines Transmitter PLL Receiver PLL v (2) v (2) GCLK RCLK FCLK IQ Lines Notes to Table 2-10: (1) (2) REFCLKB from transceiver block 0 and transceiver block 4 does not drive the inter-transceiver lines or the GCLK lines. Inter-transceiver line 0 and inter-transceiver line 1 drive the transmitter PLL, while inter-transceiver line 2 drives the receiver PLLs. Other Transceiver Features Other important features of the Stratix GX transceivers are the power down and reset capabilities, the external voltage reference and bias circuitry, and hot swapping. Individual Power-Down & Reset for the Transmitter & Receiver Stratix GX transceivers offer a power saving advantage with their ability to shut off functions that are not needed. The device can individually reset the receiver and transmitter blocks and the PLLs. The Stratix GX device can either globally power down and reset the transmitter and receiver channels or do each channel separately. Table 2-11 shows the connectivity between the reset signals and the Stratix GX logical blocks. Altera Corporation June 2006 2-37 Stratix GX Device Handbook, Volume 1 Other Transceiver Features Power-down functions are static, in other words., they are implemented upon device configuration and programmed, through the Quartus II software, to static values. Resets can be static as well as dynamic inputs coming from the logic array or pins. v rxdigitalreset v v v v v rxanalogreset txdigitalreset v v v v Receiver Analog Circuits BIST Verifiers Receiver XAUI State Machine Receiver PLL / CRU Receiver Phase Comp FIFO Module/ Byte Deserializer Receiver 8B/10B Decoder Receiver Rate Matcher Receiver Deskew FIFO Module Receiver Word Aligner Receiver Deserializer BIST Generators Transmitter Analog Circuits Transmitter XAUI State Machine Transmitter PLL Transmitter Analog Circuits Transmitter Serializer Transmitter 8B/10B Encoder Reset Signal Transmitter Phase Compensation FIFO Module/ Byte Serializer Table 2-11. Reset Signal Map to Stratix GX Blocks v v v v pll_areset v v v v v v v v v v v v v v v v v v pllenable v v v v v v v v v v v v v v v v v v Voltage Reference Capabilities Stratix GX transceivers provide voltage reference and bias circuitry. To set-up internal bias for controlling the transmitter output drivers' voltage swing--as well as to provide voltage/current biasing for other analog circuitry--use the internal bandgap voltage reference at 0.7 V. To provide bias for internal pull-up PMOS resistors for I/O termination at the serial interface of receiver and transmitter channels (independent of power supply drift, process changes, or temperature variation) an external resistor, which is connected to the external low voltage power supply, is 2-38 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 Stratix GX Transceivers accurately tracked by the internal bias circuit. Moreover, the reference voltage and internal resistor bias current is generated and replicated to the analog circuitry in each channel. Hot-Socketing Capabilities Each Stratix GX device is capable of hot-socketing. Because Stratix GX devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Signals can be driven into Stratix GX devices before and during power-up without damaging the device. Once operating conditions are reached and the device is configured, Stratix GX devices operate according to your specifications. This feature provides the Stratix GX transceiver line card behavior, so you can insert it into the system without powering the system down, offering more flexibility. Applications & Protocols Supported with Stratix GX Devices Each Stratix GX transceiver block is designed to operate at any serial bit rate from 500 Mbps to 3.1875 Gbps per channel. The wide, data rate range allows Stratix GX transceivers to support a wide variety of standard and future protocols such as 10-Gigabit Ethernet XAUI, InfiniBand, Fibre Channel, and Serial RapidIO. Stratix GX devices are ideal for many highspeed communication applications such as high-speed backplanes, chipto-chip bridges, and high-speed serial communications standards support. Stratix GX Example Application Support Stratix GX devices can be used for many applications, including: Altera Corporation June 2006 Backplanes for traffic management and quality of service (QOS) Switch fabric applications for complete set for backplane and switch fabric transceivers Chip-to-chip applications such as: 10 Gigabit Ethernet XAUI to XGMII bridge, 10 Gigabit Ethernet XGMII to POS-PHY4 bridge, POS-PHY4 to NPSI bridge, or NPSI to backplane bridge 2-39 Stratix GX Device Handbook, Volume 1 Applications & Protocols Supported with Stratix GX Devices High-Speed Serial Bus Protocols With wide, serial data rate range, Stratix GX devices can support multiple, high-speed serial bus protocols. Table 2-12 shows some of the protocols that Stratix GX devices can support. Table 2-12. High-Speed Serial Bus Protocols Stratix GX (Gbps) (Supports up to 3.1875 Gbps) Bus Transfer Protocol SONET backplane 2.488 10 Gigabit Ethernet XAUI 3.125 10 Gigabit fibre channel 3.1875 InfiniBand 2.5 Fibre channel (1G, 2G) 1.0625, 2.125 Serial RapidIOTM 1.25, 2.5, 3.125 PCI Express 2.5 SMPTE 292M 1.485 2-40 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 3. Source-Synchronous Signaling With DPA SGX51003-1.1 Introduction Expansion in the telecommunications market and growth in Internet use requires systems to move more data faster than ever. To meet this demand, rely on solutions such as differential signaling and emerging high-speed interface standards including RapidIO, POS-PHY 4, SFI-4, or XSBI. These new protocols support differential data rates up to 1 Gbps and higher. At these high data rates, it becomes more challenging to manage the skew between the clock and data signals. One solution to this challenge is to use CDR to eliminate skew between data channels and clock signals. Another potential solution, DPA, is beginning to be incorporated into some of these protocols. The source-synchronous high-speed interface in Stratix GX devices is a dedicated circuit embedded into the PLD allowing for high-speed communications. The High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2 provides information on the high-speed I/O standard features and functions of the Stratix GX device. Stratix GX I/O Banks Stratix GX devices contain 17 I/O banks. I/O banks one and two support high-speed LVDS, LVPECL, and 3.3-V PCML inputs and outputs. These two banks also incorporate an embedded dynamic phase aligner within the source-synchronous interface (see Figure 3-8 on page 3-10). The dynamic phase aligner corrects for the phase difference between the clock and data lines caused by skew. The dynamic phase aligner operates automatically and continuously without requiring a fixed training pattern, and allows the source-synchronous circuitry to capture data correctly regardless of the channel-to-clock skew. Principles of SERDES Operation Stratix GX devices support source-synchronous differential signaling up to 1 Gbps in DPA mode, and up to 840 Mbps in non-DPA mode. Serial data is transmitted and received along with a low-frequency clock. The PLL can multiply the incoming low-frequency clock by a factor of 1 to 10. The SERDES factor J can be 8 or 10 for the DPA mode, or 4, 7, 8, or 10 for all other modes. The SERDES factor does not have to equal the clock Altera Corporation August 2005 3-1 Introduction multiplication value. The x1 and x2 operation is also possible by bypassing the SERDES. The SERDES DPA cannot support x1, x2, or x4 natively. On the receiver side, the high-frequency clock generated by the PLL shifts the serial data through a shift register (also called deserializer). The parallel data is clocked out to the logic array synchronized with the lowfrequency clock. On the transmitter side, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then transmitted out by the output buffers. There are two dedicated fast PLLs each in EP1SGX10 to EP1SGX25 devices, and four in EP1SGX40 devices. These PLLs are used for the SERDES operations as well as general-purpose use. Stratix GX Differential I/O Receiver Operation (Non-DPA Mode) You can configure any of the Stratix GX source synchronous differential input channels as a receiver channel (see Figure 3-1). The differential receiver deserializes the incoming high-speed data. The input shift register continuously clocks the incoming data on the negative transition of the high-frequency clock generated by the PLL clock (xW). The data in the serial shift register is shifted into a parallel register by the RXLOADEN signal generated by the fast PLL counter circuitry on the third falling edge of the high-frequency clock. However, you can select which falling edge of the high frequency clock loads the data into the parallel register, using the data-realignment circuit. In normal mode, the enable signal RXLOADEN loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock. You can also load data to the parallel register through the TXLOADEN signal when using the data-realignment circuit. Figure 3-1 shows the block diagram of a single SERDES receiver channel. Figure 3-2 shows the timing relationship between the data and clocks in Stratix GX devices in x10 mode. W is the low-frequency multiplier and J is the data parallelization division factor. 3-2 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA Figure 3-1. Stratix GX High-Speed Interface Deserialized in x10 Mode Receiver Circuit Serial Shift Registers RXIN+ RXIN- Parallel Registers PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 xW RXCLKIN+ RXCLKIN- Parallel Registers PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 Stratix GX Logic Array xW/J (1) Fast RXLOADEN PLL (2) TXLOADEN Notes to Figure 3-1: (1) (2) W = 1, 2, 4, 7, 8, or 10. J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA). W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers. This figure does not show additional circuitry for clock or data manipulation. Figure 3-2. Receiver Timing Diagram Internal x1 clock Internal x10 clock RXLOADEN Receiver data input n-1 n-0 9 8 7 6 5 4 3 2 1 0 Stratix GX Differential I/O Transmitter Operation You can configure any of the Stratix GX differential output channels as a transmitter channel. The differential transmitter serializes outbound parallel data. Altera Corporation August 2005 3-3 Stratix GX Device Handbook, Volume 1 Introduction The logic array sends parallel data to the SERDES transmitter circuit when the TXLOADEN signal is asserted. This signal is generated by the high-speed counter circuitry of the logic array low-frequency clock's rising edge. The data is then transferred from the parallel register into the serial shift register by the TXLOADEN signal on the third rising edge of the high-frequency clock. Figure 3-3 shows the block diagram of a single SERDES transmitter channel and Figure 3-4 shows the timing relationship between the data and clocks in Stratix GX devices in x10 mode. W is the low-frequency multiplier and J is the data parallelization division factor. Figure 3-3. Stratix GX High-Speed Interface Serialized in x10 Mode Transmitter Circuit Parallel Register PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Stratix GX Logic Array PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Serial Register TXOUT+ TXOUT- xW Fast PLL TXLOADEN Figure 3-4. Transmitter Timing Diagram Internal x1 clock Internal x10 clock TXLOADEN Receiver data input n-1 n-0 3-4 Stratix GX Device Handbook, Volume 1 9 8 7 6 5 4 3 2 1 0 Altera Corporation August 2005 Source-Synchronous Signaling With DPA DPA Block Overview Each Stratix GX receiver channel features a DPA block. The block contains a dynamic phase selector for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer shown in Figure 3-5. The dynamic phase aligner uses both the source clock and the serial data. The dynamic phase aligner automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data. Figure 3-5 shows the relationship between Stratix GX source-synchronous circuitry and the Stratix GX source-synchronous circuitry with DPA. Figure 3-5. Source-Synchronous DPA Circuitry Receiver Circuit rx_in+ rx_in- Deserializer (1) Dynamic Phase Aligner Stratix GX Logic Array 8 Deserializer (1) rx_inclock_p rx_inclock_n xW PLL x1 Note to Figure 3-5: (1) Both deserializers are identical. The deserializer operation is described in the "Principles of SERDES Operation" section. Altera Corporation August 2005 3-5 Stratix GX Device Handbook, Volume 1 Introduction Unlike the de-skew function in APEXTM 20KE and APEX 20KC devices, you do not have to use a fixed training pattern with DPA in Stratix GX devices. Table 3-1 shows the differences between source-synchronous circuitry with DPA and source-synchronous circuitry without DPA circuitry in Stratix GX devices. Table 3-1. Source-Synchronous Circuitry With & Without DPA Source-Synchronous Circuitry Feature Without DPA With DPA Data rate 300 to 840 Megabits per 300 Mbps to 1 Gbps second (Mbps) Deserialization factors 1, 2, 4, 8, 10 8, 10 Clock frequency 10 to 717 MHz 74 to 717 MHz Interface pins I/O banks 1 and 2 I/O banks 1 and 2 Receiver pins Dedicated inputs Dedicated inputs DPA Input Support Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to support differential I/O standards at speeds up to 1 Gbps with DPA (or up to 840 Mbps without DPA). Stratix GX device source-synchronous circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each with a supply voltage of 3.3 V. Refer to the High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2 for more information on these I/O standards. Transmitter pins can be either input or output pins for single-ended I/O standards. Refer to Table 3-2. Table 3-2. Bank 1 & 2 Input Pins Input Pin Type I/O Standard Receiver Pin Transmitter Pin Differential Differential Input only Output only Single ended Single ended Input only Input or output Interface & Fast PLL This section describes the number of channels that support DPA and their relationship with the PLL in Stratix GX devices. EP1SGX10 and EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices 3-6 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA have four dedicated fast PLLs for clock multiplication. Table 3-3 shows the maximum number of channels in each Stratix GX device that support DPA. Table 3-3. Stratix GX Source-Synchronous Differential I/O Resources Fast PLLs Pin Count Receiver Channels (1) EP1SGX10C 2 (3) 672 22 Device Transmitter Channels (1) Receiver & Transmitter Channel Speed (Gbps) (2) LEs 22 1 10,570 EP1SGX10D 2 (3) 672 22 22 1 10,570 EP1SGX25C 2 672 39 39 1 25,660 EP1SGX25D 2 672 39 39 1 25,660 1,020 39 39 1 25,660 EP1SGX25F 2 1,020 39 39 1 25,660 EP1SGX40D 4 (4) 1,020 45 45 1 41,250 EP1SGX40G 4 (4) 1,020 45 45 1 41,250 Notes to Table 3-3: (1) (2) (3) (4) This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of the device. Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps. One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA. Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA The receiver and transmitter channels are interleaved so that each I/O row in I/O banks 1 and 2 of the device has one receiver channel and one transmitter channel per row. Figures 3-6 and 3-7 show the fast PLL and channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40 devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations. Altera Corporation August 2005 3-7 Stratix GX Device Handbook, Volume 1 Introduction Figure 3-6. PLL & Channel Layout in EP1SGX10 & EP1SGX25 Devices Notes (1), (2) 1 Receiver 1 Transmitter 11 Rows for EP1SGX10 Devices & 19 Rows for EP1SGX25 Devices 8 1 Transmitter 1 Receiver INCLK0 Fast PLL 1 (1) INCLK1 Fast PLL 2 Eight-Phase Clock 1 Receiver 1 Transmitter 8 11 Rows for EP1SGX10 Devices & 20 Rows for EP1SGX25 Devices 1 Transmitter 1 Receiver Notes to Figure 3-6: (1) (2) Fast PLL 1 in EP1SGX10 devices does not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in non-DPA mode. 3-8 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA Figure 3-7. PLL & Channel Layout in EP1SGX40 Devices CLKIN Notes (1), (2), (3) PLL (1) 1 Receiver 1 Transmitter 22 Rows 8 1 Transmitter 1 Receiver INCLK0 Fast PLL 1 INCLK1 Fast PLL 2 Eight-Phase Clock Eight-Phase Clock 1 Receiver 1 Transmitter 8 23 Rows 1 Transmitter 1 Receiver CLKIN PLL (1) Notes to Figure 3-7: (1) (2) (3) Altera Corporation August 2005 Corner PLLs do not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in non-DPA mode. The center PLLs can only clock 20 transceivers in either direction. Using Fast PLL2, you can clock a total of 40 transceivers, 20 in each direction. 3-9 Stratix GX Device Handbook, Volume 1 Introduction DPA Operation The DPA receiver circuitry contains the dynamic phase selector, the deserializer, the synchronizer, and the data realigner (see Figure 3-8). This section describes the DPA operation, synchronization and data realignment. In the SERDES with DPA mode, the source clock is fed to the fast PLL through the dedicated clock input pins. This clock is multiplied by the multiplication value W to match the serial data rate. For information on the deserializer, see "Principles of SERDES Operation" on page 3-1. Figure 3-8. DPA Receiver Circuit DPA Receiver Circuit Stratix GX Logic Array Serial Data (1) dpll_reset Dynamic Phase Selector rxin+ rxin- Deserializer 10 Synchronizer 10 Data Realigner Parallel Clock xW Clock (1) 8 inclk+ inclk - Fast PLL GCLK x1 Clock RCLK Reset Note to Figure 3-8: (1) These are phase-matched and retimed high-speed clocks and data. The dynamic phase selector matches the phase of the high-speed clock and data before sending them to the deserializer. The fast PLL supplies eight phases of the same clock (each a separate tap from a four-stage differential VCO) to all the differential channels associated with the selected fast PLL. The DPA circuitry inside each channel locks to a phase closest to the serial data's phase and sends the retimed data and the selected clock to the deserializer. The DPA circuitry automatically performs this operation and is not something you select. Each channel's DPA circuit can independently choose a different clock phase. The data phase detection and the clock phase selection process is automatic and continuous. The eight phases of the clock give the DPA circuit a granularity of one eighth of the unit interval (UI) or 125 ps at 1 Gbps. Figure 3-9 illustrates the clocks generated by the fast PLL circuitry and their relationship to a data stream. 3-10 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA Figure 3-9. Fast PLL Clocks & Data Input Data input D0 D1 D2 D3 D4 D5 Dn Clock A Clock B Clock C Clock D Clock A' Clock B' Clock C' Clock D' Protocols, Training Pattern & DPA Lock Time The dynamic phase aligner uses a fast PLL for clock multiplication, and the dynamic phase selector for the phase detection and alignment. The dynamic phase aligner uses the high-speed clock out of the dynamic phase selector to deserialize high-speed data and the receiver's source synchronous operations. At each rising edge of the clock, the dynamic phase selector determines the phase difference between the clock and the data and automatically compensates for the phase difference between the data and clock. Altera Corporation August 2005 3-11 Stratix GX Device Handbook, Volume 1 Introduction The actual lock time for different data patterns varies depending on the data's transition density (how often the data switches between 1 and 0) and jitter characteristic. The DPA circuitry is designed to lock onto any data pattern with sufficient transition density, so the circuitry works with current and future protocols. Experiments and simulations show that the DPA circuitry locks when the data patterns listed in Table 3-4 are repeated for the specified number of times. There are other suitable patterns not shown in Table 3-4 and/or pattern lengths, but the lock time may vary. The circuit can adjust for any phase variation that may occur during operation. Table 3-4. Training Patterns for Different Protocols Protocols SPI-4, NPSI Ten 0's, ten 1's (00000000001111111111) RapidIO Four 0's, four 1's (00001111) or one 1, two 0's, one 1, four 0's (10010000) Other designs Number of Repetitions Training Pattern 256 Eight alternating 1's and 0's (10101010 or 01010101) SFI-4, XSBI Not specified Phase Synchronizer Each receiver has its own phase synchronizer. The receiver phase synchronizer aligns the phase of the parallel data from all the receivers to one global clock. The synchronizers in each channel consist of a 4-bit deep and J-bit wide FIFO buffer. The parallel clock writes to the FIFO buffer and the global clock (GCLK) reads from the FIFO buffer. The global and parallel clock inputs into the synchronizers must have identical frequencies and differ only in phase. The FIFO buffer never becomes full or empty (because the source and receive signals are frequency locked) when operating within the DPA specifications, and the operation does not require an empty/full flag or read/write enable signals. Receiver Data Realignment In DPA Mode While DPA operation aligns the incoming clock phase to the incoming data phase, it does not guarantee the parallelization boundary or byte boundary. When the dynamic phase aligner realigns the data bits, the bits may be shifted out of byte alignment, as shown in Figure 3-10. 3-12 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA Figure 3-10. Misaligned Captured Bits Correct Alignment 0 1 2 3 4 5 6 7 6 7 0 1 2 Incorrect Alignment 3 4 5 The dynamic phase selector and synchronizer align the clock and data based on the power-up of both communicating devices, and the channel to channel skew. However, the dynamic phase selector and synchronizer cannot determine the byte boundary, and the data may need to be byte-aligned. The dynamic phase aligner's data realignment circuitry shifts data bits to correct bit misalignments. The Stratix GX circuitry contains a data-realignment feature controlled by the logic array. Stratix GX devices perform data realignment on the parallel data after the deserialization block. The data realignment can be performed per channel for more flexibility. The data alignment operation requires a state machine to recognize a specific pattern. The procedure requires the bits to be slipped on the data stream to correctly align the incoming data to the start of the byte boundary. The DPA uses its realignment circuitry and the global clock for data realignment. Either a device pin or the logic array asserts the internal rx_channel_data_align node to activate the DPA data-realignment circuitry. Switching this node from low to high activates the realignment circuitry and the data being transferred to the logic array is shifted by one bit. The data realignment block cannot be bypassed. However, if the rx_channel_data_align is not turned on (through the altvlds MegaWizard Plug-In Manager), or when it is not toggled, it only acts as a register latency. A state machine and additional logic can monitor the incoming parallel data and compare it against a known pattern. If the incoming data pattern does not match the known pattern, you can activate the rx_channel_data_align node again. Repeat this process until the realigner detects the desired match between the known data pattern and incoming parallel data pattern. Altera Corporation August 2005 3-13 Stratix GX Device Handbook, Volume 1 Introduction The DPA data-realignment circuitry allows further realignment beyond what the J multiplication factor allows. You can set the J multiplication factor to be 8 or 10. However, because data must be continuously clocked in on each low-speed clock cycle, the upcoming bit to be realigned and previous n -1 bits of data are selected each time the data realignment logic's counter passes n -1. At this point the data is selected entirely from bit-slip register 3 (see Figure 3-11) as the counter is reset to 0. The logic array receives a new valid byte of data on the next divided low speed clock cycle. Figure 3-11 shows the data realignment logic output selection from data in the data realignment register 2 and data realignment register 3 based on its current counter value upon continuous request of data slipping from the logic array. Figure 3-11. DPA Data Realigner Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 D19 D9 D29 D19 D99 D89 D119 D99 D119 D109 D18 D8 D28 D18 D98 D18 D118 D98 D118 D108 D17 D7 D27 D17 D97 D87 D117 D97 D117 D107 D16 D6 D26 D16 D96 D86 D116 D96 D116 D106 One bit slipped Seven more bits slipped One more bit slipped One more bit slipped D15 D5 D25 D15 D95 D85 D115 D95 D115 D125 D14 D4 D24 D14 D94 D84 D114 D94 D114 D124 D13 D3 D23 D13 D93 D83 D113 D93 D113 D123 D12 D2 D22 D12 D92 D82 D112 D92 D112 D102 D11 D1 D21 D11 D91 D81 D111 D91 D111 D101 D10 D0 D20 D10 D90 D80 D110 D90 D110 D100 Zero bits slipped. Counter = 0 D10 is the upcoming bit to be slipped. One bit slipped. Counter = 1 D21 is the upcoming bit to be slipped. Eight bits slipped. Counter = 8 D98 is the upcoming bit to be slipped. Nine bits slipped. Counter = 9 D119 is the upcoming bit to be slipped. 10 bits slipped. Counter = 0 Real data will resume on the next byte. Use the rx_channel_data_align signal within the device to activate the data realigner. You can use internal logic or an external pin to control the rx_channel_data_align signal. To ensure the rising edge of the rx_channel_data_align signal is latched into the control logic, the rx_channel_data_align signal should stay high for at least two lowfrequency clock cycles. 3-14 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 Source-Synchronous Signaling With DPA To manage the alignment procedure, a state machine should be built in the FPGA logic array to generate the realignment signal. The following guidelines outline the requirements for this state machine. Altera Corporation August 2005 The design must include an input synchronizing register to ensure that data is synchronized to the xW/J clock. After the state machine, use another synchronizing register to capture the generated rx_channel_data_align signal and synchronize it to the xW/J clock. Because the skew in the path from the output of this synchronizing register to the PLL is undefined, the state machine must generate a pulse that is high for two W/J clock periods. To guarantee the state machine does not incorrectly generate multiple rx_channel_data_align pulses to shift a single bit, the state machine must hold the rx_channel_data_align signal low for at least three x1 clock periods between pulses. 3-15 Stratix GX Device Handbook, Volume 1 Introduction 3-16 Stratix GX Device Handbook, Volume 1 Altera Corporation August 2005 4. Stratix GX Architecture SGX51004-1.0 Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus(R) II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 4-1 shows the Stratix(R) GX LAB. Figure 4-1. Stratix GX LAB Structure Row Interconnects of Variable Speed & Length Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block Local Interconnect LAB Three-Sided Architecture--Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Column Interconnects of Variable Speed & Length LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, Altera Corporation February 2005 4-1 Logic Array Blocks M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 4-2 shows the direct link connection. Figure 4-2. Direct Link Connection Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect to right Direct link interconnect to left Local Interconnect LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal turns off the LAB-wide clock. 4-2 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [7..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 4-3 shows the LAB control signal generation circuit. Figure 4-3. LAB-Wide Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Logic Elements Altera Corporation February 2005 labclkena2 labclkena1 labclk1 labclk2 labclr2 syncload asyncload or labpre labclr1 addnsub synclr The smallest unit of logic in the Stratix GX architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 4-4. 4-3 Stratix GX Device Handbook, Volume 1 Logic Elements Figure 4-4. Stratix GX LE Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear LAB Carry-In addnsub Carry-In1 Carry-In0 Programmable Register LUT chain routing to next LE data1 data2 data3 Look-Up Table (LUT) Carry Chain Synchronous Load and Clear Logic PRN/ALD D Q ADATA Row, column, and direct link routing data4 ENA CLRN labclr1 labclr2 labpre/aload Chip-Wide Reset Asynchronous Clear/Preset/ Load Logic Row, column, and direct link routing Local Routing Clock & Clock Enable Select Register Feedback Register chain output labclk1 labclk2 labclkena1 labclkena2 Carry-Out0 Carry-Out1 LAB Carry-Out Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with 4-4 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. LUT Chain & Register Chain In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. See "MultiTrack Interconnect" on page 4-11 for more information on LUT chain and register chain connections. addnsub Signal The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A - B. The LUT computes addition, and subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. LE Operating Modes The Stratix GX LE can operate in one of the following modes: Normal mode Dynamic arithmetic mode Each mode uses LE resources differently. In each mode, eight available inputs to the LE--the four data inputs from the LAB local interconnect; carry-in0 and carry-in1 from the previous LE; the LAB carry-in from the previous carry-chain LAB; and the register chain connection-- are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset load, synchronous clear, synchronous load, and Altera Corporation February 2005 4-5 Stratix GX Device Handbook, Volume 1 Logic Elements clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Normal Mode The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 4-5). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 4-5. LE in Normal Mode sload sclear (LAB Wide) (LAB Wide) aload (LAB Wide) Register chain connection addnsub (LAB Wide) (1) data1 data2 data3 cin (from cout of previous LE) 4-Input LUT clock (LAB Wide) ena (LAB Wide) data4 aclr (LAB Wide) Register Feedback ALD/PRE ADATA Q D Row, column, and direct link routing ENA CLRN Row, column, and direct link routing Local routing LUT chain connection Register chain output Note to Figure 4-5: (1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain. 4-6 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 4-6, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1. The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals--one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation February 2005 4-7 Stratix GX Device Handbook, Volume 1 Logic Elements Figure 4-6. LE in Dynamic Arithmetic Mode LAB Carry-In sload sclear (LAB Wide) (LAB Wide) Register chain connection Carry-In0 Carry-In1 addnsub (LAB Wide) (1) data1 data2 data3 LUT LUT LUT aload (LAB Wide) ALD/PRE ADATA Q D Row, column, and direct link routing ENA CLRN Row, column, and direct link routing clock (LAB Wide) ena (LAB Wide) Local routing aclr (LAB Wide) LUT chain connection LUT Register chain output Register Feedback Carry-Out0 Carry-Out1 Note to Figure 4-6: (1) The addnsub signal is tied to the carry input for the first LE of a carry chain only. Carry-Select Chain The carry-select chain provides a very fast carry-select function between LEs in arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carryselect chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. Because the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix GX architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. Figure 4-7 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used 4-8 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture for accumulator functions. Another portion of the LUT generates carryout bits. An LAB-wide carry in bit selects which chain to use for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrixTM memory and DSP blocks. A carry chain can continue as far as a full column. Altera Corporation February 2005 4-9 Stratix GX Device Handbook, Volume 1 Logic Elements Figure 4-7. Carry Select Chain LAB Carry-In 0 1 A1 B1 LE1 A2 B2 LE2 Sum1 LAB Carry-In Carry-In0 Carry-In1 A3 B3 LE3 A4 B4 LE4 A5 B5 LE5 0 Sum2 Sum3 LUT data1 data2 Sum LUT Sum4 LUT Sum5 LUT 1 A6 B6 LE6 A7 B7 LE7 A8 B8 LE8 A9 B9 LE9 A10 B10 LE10 Sum6 Carry-Out0 Carry-Out1 Sum7 Sum8 Sum9 Sum10 LAB Carry-Out Clear & Preset Logic Control LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT-gate push-back technique. Stratix GX devices support simultaneous preset/ asynchronous load, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Stratix GX devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. 4-10 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture MultiTrack Interconnect In the Stratix GX architecture, connections between LEs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intradesign block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory within the same row. These row resources include: Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device. The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. Only one side of a M-RAM block interfaces with direct link and row interconnects. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 4-8 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and horizontal IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor Altera Corporation February 2005 4-11 Stratix GX Device Handbook, Volume 1 MultiTrack Interconnect can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 4-8. R4 Interconnect Connections Adjacent LAB can Drive onto Another LAB's R4 Interconnect C4, C8, and C16 Column Interconnects (1) R4 Interconnect Driving Right R4 Interconnect Driving Left LAB Neighbor Primary LAB (2) LAB Neighbor Notes to Figure 4-8: (1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row. The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP blocks to the right or left from a source LAB. These resources are used for fast row connections in an eight-LAB region. Every LAB has its own set of R8 interconnects to drive either left or right. R8 interconnect connections between LABs in a row are similar to the R4 connections shown in Figure 4-8, with the exception that they connect to eight LABs to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects can drive other R8 interconnects to extend their range as well as C8 interconnects for row-to-row connections. One R8 interconnect is faster than two R4 interconnects connected together. R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth 4-12 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, TriMatrix memory and DSP blocks, and horizontal IOEs. These column resources include: LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device Stratix GX devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 4-9 shows the LUT chain and register chain interconnects. Altera Corporation February 2005 4-13 Stratix GX Device Handbook, Volume 1 MultiTrack Interconnect Figure 4-9. LUT Chain & Register Chain Interconnects Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1 Register Chain Routing to Adjacent LE's Register Input LE 2 Local Interconnect LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 4-10 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and vertical IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. 4-14 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-10. C4 Interconnect Connections Note (1) C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnect Driving Down Note to Figure 4-10: (1) Each C4 interconnect can drive either up or down four rows. C8 interconnects span eight LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in Figure 4-10 with the exception that they connect to eight LABs above and below. The C8 Altera Corporation February 2005 4-15 Stratix GX Device Handbook, Volume 1 MultiTrack Interconnect interconnects can drive and be driven by all types of architecture blocks similar to C4 interconnects. C8 interconnects can drive each other to extend their range as well as R8 interconnects for column-to-column connections. C8 interconnects are faster than two C4 interconnects. C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross MRAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0]. 4-16 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-1 shows the Stratix GX device's routing scheme. Table 4-1. Stratix GX Device Routing Scheme Direct Link Interconnect v R4 Interconnect v R8 Interconnect v v v v R24 Interconnect v C4 Interconnect v C8 Interconnect v v v v v v v v v v v v v v v M4K RAM Block v v v v v v v v M-RAM Block v v Row IOE v Altera Corporation February 2005 v v v v v v v v Column IOE v v v DSP Blocks v v v v v v M512 RAM Block LE v v v C16 Interconnect v v Row IOE v Column IOE Local Interconnect DSP Blocks v M-RAM Block v Register Chain M4K RAM Block LUT Chain M512 RAM Block LE C16 Interconnect C8 Interconnect C4 Interconnect R24 Interconnect R8 Interconnect R4 Interconnect Direct Link Interconnect Local Interconnect LUT Chain Source Register Chain Destination v v v v v v v v v v v 4-17 Stratix GX Device Handbook, Volume 1 TriMatrix Memory TriMatrix Memory TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 4-2 shows the size and features of the different RAM blocks. Table 4-2. TriMatrix Memory Features (Part 1 of 2) Memory Feature Maximum performance M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits) (1) True dual-port memory M-RAM Block (4K x 144 Bits) (1) (1) v v Simple dual-port memory v v v Single-port memory v v v Shift register v v ROM v v (2) FIFO buffer v v v v v Parity bits v v v Mixed clock mode v v v Memory initialization v v Simple dual-port memory mixed width support v v v v v Byte enable True dual-port memory mixed width support Power-up conditions Outputs cleared Outputs cleared Outputs unknown Register clears Input and output registers Input and output registers Output registers Mixed-port readduring-write Unknown output/old data Unknown output/old data Unknown output 4-18 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-2. TriMatrix Memory Features (Part 2 of 2) Memory Feature Configurations M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits) 512 x1 256 x 2 128 x 4 64 x 8 64 x 9 32 x 16 32 x 18 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36 M-RAM Block (4K x 144 Bits) 64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144 Notes to Table 4-2: (1) (2) See the DC & Switching Characteristics chapter of the Stratix GX Device Handbook, Volume 1 for maximum performance information. The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix GX device must write to the dual-port memory once and then disable the write-enable ports afterwards. Memory Modes TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K and M-RAM memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 4-11 shows true dual-port memory. Figure 4-11. True Dual-Port Memory Configuration A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write Altera Corporation February 2005 4-19 Stratix GX Device Handbook, Volume 1 TriMatrix Memory occurs or just read the don't care bits. Single-port memory supports non-simultaneous reads and writes, but the q[] port outputs the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). For more information, see the TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. Figure 4-12 shows these different RAM memory port configurations for TriMatrix memory. Figure 4-12. Simple Dual-Port & Single-Port Memory Configurations Simple Dual-Port Memory data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr Single-Port Memory (1) data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr Note to Figure 4-12: (1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in x1 mode at port A and read out in x16 mode from port B. TriMatrix memory architecture can implement pipelined RAM by registering both the input and output signals to the RAM block. All TriMatrix memory block inputs are registered providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (WREN) signal derived from the global 4-20 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM WREN signal while ensuring its data and address signals meet setup and hold time specifications relative to the WREN signal. The output registers can be bypassed. Flow-through reading is possible in the simple dual-port mode of M512 and M4K RAM blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple TriMatrix memory blocks. For example, two 256 x 16-bit RAM blocks can be combined to form a 256 x 32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words available in one memory block. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic. Parity Bit Support The memory blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. You can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations. Shift Register Support You can configure embedded memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multichannel filtering, auto-correlation, and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w x m x n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w x m x n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 Altera Corporation February 2005 4-21 Stratix GX Device Handbook, Volume 1 TriMatrix Memory RAM block and 4,608 bits for the M4K RAM block. The total number of shift register outputs (number of taps n x width w) must be less than the maximum data width of the RAM block (18 for M512 blocks, 36 for M4K blocks). To create larger shift registers, the memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 4-13 shows the TriMatrix memory block in the shift register mode. Figure 4-13. Shift Register Memory Configuration w x m x n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Memory Block Size TriMatrix memory provides three different memory sizes for efficient application support. The large number of M512 blocks are ideal for designs with many shallow first-in first-out (FIFO) buffers. M4K blocks provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large 4-22 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture single block of RAM ideal for data packet storage. The different-sized blocks allow Stratix GX devices to efficiently support variable-sized memory in designs. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes. M512 RAM Block The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes: Simple dual-port RAM Single-port RAM FIFO ROM Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 x 1, 256 x 2, 128 x 4, 64 x 8 (64 x 9 bits with parity), and 32 x 16 (32 x 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 4-3 summarizes the possible M512 RAM block configurations. Table 4-3. M512 RAM Block Configurations (Simple Dual-Port RAM) Write Port Read Port 512 x 1 256 x 2 128 x 4 64 x 8 32 x 16 512 x 1 v v v v v 256 x 2 v v v v v 128 x 4 v v v 64 x 8 v v 32 x 16 v v 64 x 9 32 x 18 Altera Corporation February 2005 64 x 9 32 x 18 v v v v v v 4-23 Stratix GX Device Handbook, Volume 1 TriMatrix Memory When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See "I/O Structure" on page 4-96 for details on dedicated SERDES in Stratix GX devices. M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The eight labclk signals or local interconnect can drive the inclock, outclock, wren, rden, inclr, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, LEs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 4-14 shows the M512 RAM block control signal generation logic. The RAM blocks within Stratix GX devices have local interconnects to allow LEs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Up to 10 direct link input connections to the M512 RAM block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through 10 direct link interconnects. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 4-15 shows the M512 RAM block to logic array interface. 4-24 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-14. M512 RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation February 2005 outclocken inclocken inclock outclock outclr wren rden inclr 4-25 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Figure 4-15. M512 RAM Block LAB Row Interface C4 and C8 Interconnects R4 and R8 Interconnects 10 Direct link interconnect to adjacent LAB Direct link interconnect to adjacent LAB dataout M512 RAM Block Direct link interconnect from adjacent LAB Direct link interconnect from adjacent LAB Control Signals datain address Clocks 2 8 Small RAM Block Local Interconnect Region LAB Row Clocks M4K RAM Blocks The M4K RAM block includes support for true dual-port RAM. The M4K RAM block implements buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes: True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. 4-26 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture The memory address depths and output widths can be configured as 4,096 x 1, 2,048 x 2, 1,024 x 4, 512 x 8 (or 512 x 9 bits), 256 x 16 (or 256 x 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 4-4 and 4-5 summarize the possible M4K RAM block configurations. Table 4-4. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 1K 4 512 8 256 16 128 32 512 9 256 18 128 36 v v v v v v v v v v v v v v v v v v 256 x 16 v v v v v v 128 x 32 v v v v v v 512 x 9 v v v 256 x 18 v v v 128 x 36 v v v 4K 1 2K x 2 4K x 1 v v v 2K x 2 v v 1K x 4 v 512 x 8 Table 4-5. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18 4K x 1 v v v v v 2K x 2 v v v v v 1K x 4 v v v v v 512 x 8 v v v v v 256 x 16 v v v v v 512 x 9 v v 256 x 18 v v When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w x m x n). Altera Corporation February 2005 4-27 Stratix GX Device Handbook, Volume 1 TriMatrix Memory M4K RAM blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 4-6 summarizes the byte selection. Table 4-6. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0] datain x18 datain x36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 - [26..18] [3] = 1 - [35..27] Notes to Table 4-6: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, that is, in x16 and x32 modes. The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The eight labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 4-16. The R4, R8, C4, C8, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 4-17 shows the M4K RAM block to logic array interface. 4-28 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-16. M4K RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect alcr_a clocken_a clock_b renwe_b Local Interconnect Local Interconnect clock_a renwe_a alcr_b clocken_b Figure 4-17. M4K RAM Block LAB Row Interface C4 and C8 Interconnects Direct link interconnect to adjacent LAB R4 and R8 Interconnects 10 Direct link interconnect to adjacent LAB dataout Direct link interconnect from adjacent LAB M4K RAM Block Direct link interconnect from adjacent LAB Byte enable Control Signals Clocks address datain 8 M4K RAM Block Local Interconnect Region Altera Corporation February 2005 LAB Row Clocks 4-29 Stratix GX Device Handbook, Volume 1 TriMatrix Memory M-RAM Block The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes: True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM You cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. The memory address and output width can be configured as 64K x 8 (or 64K x 9 bits), 32K x 16 (or 32K x 18 bits), 16K x 32 (or 16K x 36 bits), 8K x 64 (or 8K x 72 bits), and 4K x 128 (or 4K x 144 bits). The 4K x 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. Mixed-width configurations are also possible, allowing different read and write widths. Tables 4-7 and 4-8 summarize the possible M-RAM block configurations: Table 4-7. M-RAM Block Configurations (Simple Dual-Port) Write Port Read Port 64K x 9 32K x 18 16K x 36 8K x 72 64K x 9 v v v v 32K x 18 v v v v 16K x 36 v v v v 8K x 72 v v v v 4K x 144 4-30 Stratix GX Device Handbook, Volume 1 4K x 144 v Altera Corporation February 2005 Stratix GX Architecture Table 4-8. M-RAM Block Configurations (True Dual-Port) Port B Port A 64K x 9 32K x 18 16K x 36 8K x 72 64K x 9 v v v v 32K x 18 v v v v 16K x 36 v v v v 8K x 72 v v v v The read and write operation of the memory is controlled by the WREN signal, which sets the ports into either read or write modes. There is no separate read enable (RE) signal. Writing into RAM is controlled by both the WREN and byte enable (byteena) signals for each port. The default value for the byteena signal is high, in which case writing is controlled only by the WREN signal. The byte enables are available for the x18, x36, and x72 modes. In the x144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Tables 4-9 and 4-10 summarize the byte selection. Table 4-9. Byte Enable for M-RAM Blocks Notes (1), (2) Altera Corporation February 2005 byteena[3..0] datain x18 datain x36 datain x72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 - [26..18] [26..18] [3] = 1 - [35..27] [35..27] [4] = 1 - - [44..36] [5] = 1 - - [53..45] [6] = 1 - - [62..54] [7] = 1 - - [71..63] 4-31 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Table 4-10. M-RAM Combined Byte Selection for x144 Mode Notes (1), (2) byteena[15..0] datain x144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] Notes to Tables 4-9 and 4-10: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, that is, in x16, x32, x64, and x128 modes. Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. All input registers--renwe, datain, address, and byte enable registers--are clocked together from either of the two clocks feeding the block. The output register can be bypassed. The eight labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 4-18. 4-32 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-18. M-RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clocken_b clocken_a clock_a clock_b renwe_b aclr_b aclr_a renwe_a One of the M-RAM block's horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side closest to the device perimeter contains the interfaces. The one exception is when two M-RAM blocks are paired next to each other. In this case, the side of the M-RAM block opposite the common side of the two blocks contains the input interface. The top and bottom sides of any M-RAM block contain data input and output interfaces to the logic array. The top side has 72 data inputs and 72 data outputs for port B, and the bottom side has another 72 data inputs and 72 data outputs for port A. Figure 4-19 shows an example floorplan for the EP1SGX40 device and the location of the M-RAM interfaces. Altera Corporation February 2005 4-33 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Figure 4-19. EP1SGX40 Device with M-RAM Interface Locations Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins. M-RAM interface to top, bottom, and side opposite of block-to-block border. DSP Blocks M512 Blocks Note (1) M-RAM Block M-RAM Block M-RAM Block M-RAM Block LABs DSP Blocks Note to Figure 4-19: (1) Device shown is an EP1SGX40 device. The number and position of M-RAM blocks varies in other devices. The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. For independent M-RAM blocks, up to 10 direct link address and control signal input connections to the M-RAM block are possible from the left adjacent LABs for M-RAM 4-34 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture blocks facing to the left, and another 10 possible from the right adjacent LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. Figures 4-20 through 4-22 show the interface between the M-RAM block and the logic array. Altera Corporation February 2005 4-35 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Figure 4-20. Left-Facing M-RAM to Interconnect Interface Notes (1), (2) M512 RAM Block Columns Row Unit Interface Allows LAB Rows to Drive Address and Control Signals to M-RAM Block LABs in Column M-RAM Boundary Column Interface Block Drives to and from C4 and C8 Interconnects B1 B2 B3 B4 B5 B6 A4 A5 A6 Port B R11 R10 R9 R8 R7 M-RAM Block R6 R5 R4 R3 R2 R1 Port A A1 A2 A3 Column Interface Block Allows LAB Columns to Drive datain and dataout to and from M-RAM Block LABs in Row M-RAM Boundary LAB Interface Blocks Notes to Figure 4-20: (1) (2) Only R24 and C16 interconnects cross the M-RAM block boundaries. The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6 orientation is clipped across the vertical axis for right-facing M-RAM blocks. 4-36 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-21. M-RAM Row Unit Interface to Interconnect C4 and C8 Interconnects R4 and R8 Interconnects M-RAM Block LAB 10 Direct Link Interconnects Up to 24 addressa addressb renwe_a renwe_b byteenaA[ ] byteenaB[ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region Altera Corporation February 2005 4-37 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Figure 4-22. M-RAM Column Unit Interface to Interconnect C4 and C8 Interconnects LAB LAB LAB M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block 12 12 datain dataout M-RAM Block 4-38 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-11 shows the input and output data signal connections for the column units (B1 to B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11). Table 4-11. M-RAM Row & Column Interface Unit Signals Altera Corporation February 2005 Unit Interface Block Input SIgnals R1 addressa[7..0] R2 addressa[15..8] R3 byte_enable_a[7..0] renwe_a R4 - R5 - R6 clock_a clocken_a clock_b clocken_b R7 - R8 - R9 byte_enable_b[7..0] renwe_b R10 addressb[15..8] Output Signals R11 addressb[7..0] B1 datain_b[71..60] dataout_b[71..60] B2 datain_b[59..48] dataout_b[59..48] B3 datain_b[47..36] dataout_b[47..36] B4 datain_b[35..24] dataout_b[35..24] B5 datain_b[23..12] dataout_b[23..12] B6 datain_b[11..0] dataout_b[11..0] A1 datain_a[71..60] dataout_a[71..60] A2 datain_a[59..48] dataout_a[59..48] A3 datain_a[47..36] dataout_a[47..36] A4 datain_a[35..24] dataout_a[35..24] A5 datain_a[23..12] dataout_a[23..12] A6 datain_a[11..0] dataout_a[11..0] 4-39 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Independent Clock Mode The memory blocks implement independent clock mode for true dualport memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 4-23 shows a TriMatrix memory block in independent clock mode. 4-40 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 (1) Altera Corporation February 2005 clockA clkenA 8 ENA D ENA D ENA D ENA D Q Q Q Q Write Pulse Generator Q Data Out Write/Read Enable Address A qA[ ] B Data In qB[ ] Q D ENA Data Out Write/Read Enable Address B Byte Enable B Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 Byte Enable A ENA D A Data In Write Pulse Generator Q Q Q Q D ENA D ENA D ENA D ENA 8 clockB clkenB wrenB addressB[ ] byteenaB[ ] dataB[ ] Figure 4-23. Independent Clock Mode wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 LAB Row Clocks Stratix GX Architecture Note (1) Note to Figure 4-23: All registers shown have asynchronous clear ports. 4-41 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Input/Output Clock Mode Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 4-24 and 4-25 show the memory block in input/output clock mode. 4-42 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 (1) Altera Corporation February 2005 clockA clkenA wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 ENA D ENA D ENA D ENA D 8 LAB Row Clocks Q Q Q Q Write Pulse Generator Q Data Out Write/Read Enable Address A ENA D A qA[ ] Data In B qB[ ] Q D ENA Data Out Write/Read Enable Address B Byte Enable B Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 Byte Enable A Data In Write Pulse Generator Q Q Q Q ENA D ENA D ENA D ENA D 8 clockB clkenB wrenB addressB[ ] byteenaB[ ] dataB[ ] Stratix GX Architecture Figure 4-24. Input/Output Clock Mode in True Dual-Port Mode Note (1) Note to Figure 4-24: All registers shown have asynchronous clear ports. 4-43 Stratix GX Device Handbook, Volume 1 TriMatrix Memory Figure 4-25. Input/Output Clock Mode in Simple Dual-Port Mode Note (1) 8 LAB Row Clocks Memory Block 256 16 512 8 1,024 4 2,048 2 4,096 1 8 data[ ] D Q ENA Data In address[ ] D Q ENA Read Address Data Out byteena[ ] D Q ENA Byte Enable wraddress[ ] D Q ENA Write Address D Q ENA Read Enable D Q ENA To MultiTrack Interconnect rden wren outclken D Q ENA inclken wrclock Write Pulse Generator Write Enable rdclock Note to Figure 4-25: (1) All registers shown except the rden register have asynchronous clear ports. Read/Write Clock Mode The memory blocks implement read/write clock mode for simple dualport memory. You can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 4-26 shows a memory block in read/write clock mode. 4-44 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-26. Read/Write Clock Mode in Simple Dual-Port Mode 8 LAB Row Clocks Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 8 data[ ] Note (1) D Q ENA Data Out address[ ] D Q ENA Read Address wraddress[ ] D Q ENA Write Address byteena[ ] D Q ENA Byte Enable D Q ENA Read Enable D Q ENA To MultiTrack Interconnect rden wren outclken inclken D Q ENA wrclock Write Pulse Generator Write Enable rdclock Note to Figure 4-26: (1) All registers shown except the rden register have asynchronous clear ports. Single-Port Mode The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 4-27. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Altera Corporation February 2005 4-45 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-27. Single-Port Mode 8 LAB Row Clocks RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 8 data[ ] D Q ENA Data Out address[ ] D Q ENA Address D Q ENA To MultiTrack Interconnect wren Write Enable outclken D Q ENA inclken inclock Write Pulse Generator outclock Digital Signal Processing Block The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these blocks have the same fundamental building block: the multiplier. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix GX devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix GX device has two columns of DSP blocks to efficiently implement DSP functions faster than LE-based implementations. Larger Stratix GX devices have more DSP blocks per column (see Table 4-12). Each DSP block can be configured to support up to: Eight 9 x 9-bit multipliers Four 18 x 18-bit multipliers One 36 x 36-bit multiplier As indicated, the Stratix GX DSP block can support one 36 x 36-bit multiplier in a single DSP block. This is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but 4-46 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture the capabilities for dynamic and mixed sign multiplications are handled differently. The following list provides the largest functions that can fit into a single DSP block. 1 36 x 36-bit unsigned by unsigned multiplication 36 x 36-bit signed by signed multiplication 35 x 36-bit unsigned by signed multiplication 36 x 35-bit signed by unsigned multiplication 36 x 35-bit signed by dynamic sign multiplication 35 x 36-bit dynamic sign by signed multiplication 35 x 36-bit unsigned by dynamic sign multiplication 36 x 35-bit dynamic sign by unsigned multiplication 35 x 35-bit dynamic sign multiplication when the sign controls for each operand are different 36 x 36-bit dynamic sign multiplication when the same sign control is used for both operands This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions. Figure 4-28 shows one of the columns with surrounding LAB rows. Altera Corporation February 2005 4-47 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-28. DSP Blocks Arranged in Columns DSP Block Column 8 LAB Rows 4-48 Stratix GX Device Handbook, Volume 1 DSP Block Altera Corporation February 2005 Stratix GX Architecture Table 4-12 shows the number of DSP blocks in each Stratix GX device. Table 4-12. DSP Blocks in Stratix GX Devices Device Notes (1), (2) DSP Blocks Total 9 x 9 Multipliers Total 18 x 18 Multipliers Total 36 x 36 Multipliers 6 48 24 6 EP1SGX10 EP1SGX25 10 80 40 10 EP1SGX40 14 112 56 14 Notes to Table 4-12: (1) (2) Each device has either the number of 9 x 9-, 18 x 18-, or 36 x 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations. DSP block multipliers can optionally feed an adder/subtractor or accumulator within the block depending on the configuration. This makes routing to LEs easier, saves LE routing resources, and increases performance, because all connections and blocks are within the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 4-29 shows the top-level diagram of the DSP block configured for 18 x 18-bit multiplier mode. Figure 4-30 shows the 9 x 9-bit multiplier configuration of the DSP block. Altera Corporation February 2005 4-49 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-29. DSP Block Diagram for 18 x 18-Bit Configuration Optional Serial Shift Register Inputs from Previous DSP Block Multiplier Stage D Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor Q ENA CLRN D D ENA CLRN Q Output Selection Multiplexer Q ENA CLRN Adder/ Subtractor/ Accumulator 1 D Q ENA CLRN D D ENA CLRN Q Q ENA CLRN Summation D Q ENA CLRN D D ENA CLRN Q Q Summation Stage for Adding Four Multipliers Together Optional Output Register Stage ENA CLRN Adder/ Subtractor/ Accumulator 2 D Optional Serial Shift Register Outputs to Next DSP Block in the Column Q ENA CLRN D D ENA CLRN Q ENA CLRN 4-50 Stratix GX Device Handbook, Volume 1 Q Optional Pipeline Register Stage Optional Input Register Stage with Parallel Input or Shift Register Configuration to MultiTrack Interconnect Altera Corporation February 2005 Stratix GX Architecture Figure 4-30. DSP Block Diagram for 9 x 9-Bit Configuration D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 1a CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN Summation D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 1b CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN Output Selection Multiplexer CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN D Q ENA CLRN Adder/ Subtractor/ 2a CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN Summation D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 2b CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN To MultiTrack Interconnect Altera Corporation February 2005 4-51 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block The DSP block consists of the following elements: Multiplier block Adder/output block Multiplier Block The DSP block multiplier block consists of the input registers, a multiplier, and pipeline register for pipelining multiply-accumulate and multiply-add/subtract functions as shown in Figure 4-31. Figure 4-31. Multiplier Sub-Block Within Stratix GX DSP Block sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0] shiftin A shiftin B D Data A Q ENA CLRN D ENA Q CLRN D Data B Q ENA Result to Adder blocks Optional Multiply-Accumulate and Multiply-Add Pipeline CLRN shiftout B shiftout A Note to Figure 4-31: (1) These signals can be unregistered or registered once to match data path pipelines if required. 4-52 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Input Registers A bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multiplier. When these registers are configured for parallel data inputs, they are driven by regular routing resources. You can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of A and B inputs for each multiplier in the DSP block. You select these control signals from a set of four different clock[3..0], aclr[3..0], and ena[3..0] signals that drive the entire DSP block. You can also configure the input registers for a shift register application. In this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftoutA and shiftoutB. The shift outputs of one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block) as shown in Figure 4-32, to form a shift register chain. This chain can terminate in any block, that is, you can create any length of shift register chain up to 224 registers. You can use the input shift registers for FIR filter applications. One set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. When implementing 9 x 9- and 18 x 18-bit multipliers, you do not need to implement external shift registers in LAB LEs. You implement all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 x 36-bit multipliers. Altera Corporation February 2005 4-53 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-32. Multiplier Sub-Blocks Using Input Shift Register Connections Data A D Note (1) Q ENA A[n] x B[n] CLRN Data B D Q D ENA Q CLRN ENA CLRN Data B Data A D Q ENA A[n 1] x B[n 1] CLRN D Q D ENA Q CLRN ENA CLRN Data B Data A D Q ENA A[n 2] x B[n 2] CLRN D Q D ENA Q CLRN ENA CLRN Note to Figure 4-32: (1) Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication. 4-54 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-13 shows the summary of input register modes for the DSP block. Table 4-13. Input Register Modes 9x9 18 x 18 36 x 36 Parallel input v v v Shift register input v v Register Input Mode Multiplier The multiplier supports 9 x 9-, 18 x 18-, or 36 x 36-bit multiplication. Each DSP block supports eight possible 9 x 9-bit or smaller multipliers. There are four multiplier blocks available for multipliers larger than 9 x 9 bits but smaller than 18 x 18 bits. There is one multiplier block available for multipliers larger than 18 x 18 bits but smaller than or equal to 36 x 36 bits. The ability to have several small multipliers is useful in applications such as video processing. Large multipliers greater than 18 x 18 bits are useful for applications such as the mantissa multiplication of a single-precision floating-point number. The multiplier operands can be signed or unsigned numbers, where the result is signed if either input is signed as shown in Table 4-14. The sign_a and sign_b signals provide dynamic control of each operand's representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. These sign signals affect all multipliers and adders within a single DSP block and you can register them to match the data path pipeline. The multipliers are full precision (that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and so on), regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers. Table 4-14. Multiplier Signed Representation Altera Corporation February 2005 Data A Data B Result Unsigned Unsigned Unsigned Unsigned Signed Signed Signed Unsigned Signed Signed Signed Signed 4-55 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Pipeline/Post Multiply Register The output of 9 x 9- or 18 x 18-bit multipliers can optionally feed a register to pipeline multiply-accumulate and multiply-add/subtract functions. For 36 x 36-bit multipliers, this register pipelines the multiplier function. Adder/Output Blocks The result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtractor/accumulator unit, summation unit, output select multiplexer, and output registers. The results are used to configure the adder/output block as a pure output, accumulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. You can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Figure 4-33 shows the adder and output stages. 4-56 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-33. Adder/Output Blocks Note (1) Accumulator Feedback accum_sload0 (2) Result A addnsub1 (2) overflow0 Adder/ Subtractor/ Accumulator1 Output Selection Multiplexer Result B signa (2) Summation Output Register Block signb (2) Result C addnsub3 (2) Adder/ Subtractor/ Accumulator2 overflow1 Result D accum_sload1 (2) Accumulator Feedback Notes to Figure 4-33: (1) (2) Adder/output block shown in Figure 4-33 is in 18 x 18-bit mode. In 9 x 9-bit mode, there are four adder/subtractor blocks and two summation blocks. These signals are either not registered, registered once, or registered twice to match the data path pipeline. Altera Corporation February 2005 4-57 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Adder/Subtractor/Accumulator The adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumulator or as an adder/subtractor. Adder/Subtractor Each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each firstlevel adder in 18 x 18-bit mode. There are two addnsub[1..0] signals available in a DSP block for any configuration. For 9 x 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. A high addnsub signal indicates addition, and a low signal indicates subtraction. The addnsub control signal can be unregistered or registered once or twice when feeding the adder blocks to match data path pipelines. The signa and signb signals serve the same function as the multiplier block signa and signb signals. The only difference is that these signals can be registered up to two times. These signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. Accumulator When configured for accumulation, the adder/output block output feeds back to the accumulator as shown in Figure 4-33. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. Additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. This signal is always registered and must be externally latched in LEs if the design requires a latched overflow signal. Summation The output of the adder/subtractor/accumulator block feeds to an optional summation block. This block sums the outputs of the DSP block multipliers. In 9 x 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 x 9-bit multipliers. In 18 x 18-bit mode, there is one summation providing the sum of one set of four 18 x 18-bit multipliers. 4-58 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Output Selection Multiplexer The outputs from the various elements of the adder/output block are routed through an output selection multiplexer. Based on the DSP block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output. Output Registers Optional output registers for the DSP block outputs are controlled by four sets of control signals: clock[3..0], aclr[3..0], and ena[3..0]. Output registers can be used in any mode. Modes of Operation The adder, subtractor, and accumulate functions of a DSP block have four modes of operation: 1 Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported. Simple Multiplier Mode In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register. Up to four 18 x 18-bit multipliers or eight 9 x 9-bit multipliers can drive their results directly out of one DSP block. See Figure 4-34. Altera Corporation February 2005 4-59 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-34. Simple Multiplier Mode signa (1) signb (1) aclr clock ena shiftin A shiftin B D Data A Q Data Out ENA CLRN D ENA Q D ENA Q CLRN CLRN D Data B Q ENA CLRN shiftout B shiftout A Note to Figure 4-34: (1) These signals are not registered or registered once to match the data path pipeline. DSP blocks can also implement one 36 x 36-bit multiplier in multiplier mode. DSP blocks use four 18 x 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. The input shift register feature is not available for the 36 x 36-bit multiplier. In 36 x 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 x 36-bit multiplier. Figure 4-35 shows the 36 x 36-bit multiply mode. 4-60 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-35. 36 x 36 Multiply Mode signa (1) signb (1) aclr clock ena A[17..0] D Q ENA CLRN D ENA Q CLRN B[17..0] D Q ENA CLRN A[35..18] D Q D ENA ENA CLRN D ENA Q 36 x 36 Multiplier Adder CLRN B[35..18] D Q Data Out CLRN Q signa (2) ENA signb (2) CLRN A[35..18] D Q ENA CLRN D ENA Q CLRN B[17..0] D Q ENA CLRN A[17..0] D Q ENA CLRN D ENA Q CLRN B[35..18] D Q ENA CLRN Notes to Figure 4-35: (1) (2) These signals are not registered or registered once to match the pipeline. These signals are not registered, registered once, or registered twice for latency to match the pipeline. Altera Corporation February 2005 4-61 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Multiply-Accumulator Mode In multiply-accumulator mode (see Figure 4-36), the DSP block drives multiplied results to the adder/subtractor/accumulator block configured as an accumulator. You can implement one or two multiply-accumulators up to 18 x 18 bits in one DSP block. The first and third multiplier subblocks are unused in this mode, since only one multiplier can feed one of two accumulators. The multiply-accumulator output can be up to 52 bits--a maximum of a 36-bit result with 16 bits of accumulation. The accum_sload and overflow signals are only available in this mode. The addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. Figure 4-36. Multiply-Accumulate Mode signa (1) signb (1) aclr clock ena Shiftin A Shiftin B D Data A Q ENA D ENA CLRN Q Accumulator D ENA Q Data Out CLRN CLRN D Data B Q overflow ENA CLRN Shiftout B addnsub (2) signa (2) signb (2) accum_sload (2) Shiftout A Notes to Figure 4-36: (1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. Two-Multipliers Adder Mode The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A single DSP block can implement two sums or differences from two 18 x 18-bit multipliers each or four sums or differences from two 9 x 9-bit multipliers each. 4-62 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture You can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) x (c + jd) = [(a x c) - (b x d)] + j x [(a x d) + (b x c)] The two-multipliers adder mode allows a single DSP block to calculate the real part [(a x c) - (b x d)] using one subtractor and the imaginary part [(a x d) + (b x c)] using one adder, for data widths up to 18 bits. Two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. Figure 4-37 shows an 18-bit two-multipliers adder. Figure 4-37. Two-Multipliers Adder Mode Implementing Complex Multiply 18 DSP Block 18 A 36 18 18 C 18 37 (A x C) - (B x D) (Real Part) Subtractor 18 B 36 18 18 D 18 A 36 18 D 37 Adder 18 B (A x D) + (B x C) (Imaginary Part) 36 18 C Four-Multipliers Adder Mode In the four-multipliers adder mode, the DSP block adds the results of two first -stage adder/subtractor blocks. One sum of four 18 x 18-bit multipliers or two different sums of two sets of four 9 x 9-bit multipliers can be implemented in a single DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. Figure 4-38 shows the four multipliers adder mode. Altera Corporation February 2005 4-63 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block Figure 4-38. Four-Multipliers Adder Mode signa (1) signb (1) aclr clock ena shiftin A shiftin B D Data A Q ENA CLRN D ENA Q Adder/Subtractor CLRN D Data B Q ENA CLRN D Data A Q D ENA ENA CLRN D ENA Q CLRN D Data B Q addnsub1 (2) signa (2) signb (2) Q Data Out Summation CLRN addnsub3 (2) ENA CLRN D Data A Q ENA CLRN D ENA Q Adder/Subtractor CLRN D Data B Q ENA CLRN D Data A Q ENA CLRN D ENA Q CLRN D Data B Q ENA CLRN shiftout B shiftout A Notes to Figure 4-38: (1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. 4-64 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture For FIR filters, the DSP block combines the four-multipliers adder mode with the shift register inputs. One set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. The input shift register eliminates the need for shift registers external to the DSP block (that is, implemented in LEs). This architecture simplifies filter design since the DSP block implements all of the filter circuitry. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, DSP blocks can be cascaded with additional adder stages implemented in LEs. Table 4-15 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions. Table 4-15. Multiplier Size & Configurations per DSP block DSP Block Mode 9x9 18 x 18 36 x 36 (1) Multiplier Eight multipliers with eight product outputs Four multipliers with four product outputs One multiplier with one product output Multiply-accumulator Two multiply and accumulate (52 bits) Two multiply and accumulate (52 bits) - Two-multipliers adder Four sums of two multiplier products each Two sums of two multiplier products each - Four-multipliers adder Two sums of four multiplier products each One sum of four multiplier products each - Note to Table 4-15: (1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations. DSP Block Interface Stratix GX device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade DSP blocks for 9 x 9- or 18 x 18-bit FIR filters larger than four taps, with additional adder stages implemented in LEs. If the DSP block is configured as 36 x 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks. Altera Corporation February 2005 4-65 Stratix GX Device Handbook, Volume 1 Digital Signal Processing Block The DSP block is divided into eight block units that interface with eight LAB rows on the left and right. Each block unit can be considered half of an 18 x 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 10 direct link interconnects from the LAB to the left or right of the DSP block in the same row. All row and column routing resources can access the DSP block's local interconnect region. The outputs also work similarly to LAB outputs as well. Nine outputs from the DSP block can drive to the left LAB through direct link interconnects and nine can drive to the right LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. Figures 4-39 and 4-40 show the DSP block interfaces to LAB rows. Figure 4-39. DSP Block Interconnect Interface DSP Block MultiTrack Interconnect OA[17..0] MultiTrack Interconnect A1[17..0] OB[17..0] B1[17..0] OC[17..0] A2[17..0] OD[17..0] B2[17..0] OE[17..0] A3[17..0] OF[17..0] B3[17..0] OG[17..0] A4[17..0] OH[17..0] B4[17..0] 4-66 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-40. DSP Block Interface to Interconnect C4 and C8 Interconnects Direct Link Interconnect from Adjacent LAB R4 and R8 Interconnects Nine Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB 18 DSP Block Row Structure LAB 10 LAB 9 9 10 3 Control 18 18 [17..0] [17..0] Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The Altera Corporation February 2005 4-67 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 4-16. Table 4-16. DSP Block Signal Sources & Destinations LAB Row at Interface PLLs & Clock Networks Control Signals Generated Data Inputs Data Outputs 1 signa A1[17..0] OA[17..0] 2 aclr0 accum_sload0 B1[17..0] OB[17..0] 3 addnsub1 clock0 ena0 A2[17..0] OC[17..0] 4 aclr1 clock1 ena1 B2[17..0] OD[17..0] 5 aclr2 clock2 ena2 A3[17..0] OE[17..0] 6 sign_b clock3 ena3 B3[17..0] OF[17..0] 7 clear3 accum_sload1 A4[17..0] OG[17..0] 8 addnsub3 B4[17..0] OH[17..0] Stratix GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Stratix GX devices contain up to four enhanced PLLs and up to four fast PLLs. In addition, there are four receiver PLLs and one transmitter PLL per transceiver block located on the right side of Stratix GX devices. Global & Hierarchical Clocking Stratix GX devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), 8 dedicated fast regional clock networks within EP1SGX10 and EP1SGX25, and 16 dedicated fast regional clock networks within EP1SGX40 devices. 4-68 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 40 unique clock domains within EP1SGX10 and EP1SGX25 devices, and 48 unique clock domains within EP1SGX40 devices. There are 12 dedicated clock pins (CLK[15..12], and CLK[7..0]) to drive either the global or regional clock networks. Three clock pins drive the top, bottom, and left side of the device. Enhanced and fast PLL outputs as well as an I/O interface can also drive these global and regional clock networks. There are up to 20 recovered clocks (rxclkout[20..0]) and up to 5 transmitter clock outputs (coreclk_out) which can drive any of the global clock networks (CLK[15..0]), as shown in Figure 4-41. Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 4-41 shows the 12 dedicated CLK pins and the transceiver clocks driving global clock networks. Altera Corporation February 2005 4-69 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-41. Global Clock Resources CLK[15..12] CLK[3..0] Global Clock [15..0] Transceiver Clocks CLK[7..4] Regional Clock Network There are four regional clock networks RCLK[3..0] within each quadrant of the Stratix GX device that are driven by the same dedicated CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver clocks. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 4-42. 4-70 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-42. Regional Clocks RCLK[15..14] RCLK[13..12] CLK[15..12] RCLK[1..0] RCLK[11..10] CLK[3..0] Transceiver Clocks RCLK[3..2] RCLK[9..8] CLK[7..4] RCLK[5..4] RCLK[7..6] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins, Recovered Clocks, or PLLs within that Quadrant Fast Regional Clock Network In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock networks, FCLK[1..0], within each quadrant, fed by input pins (see Figure 4-43). In EP1SGX40 devices, there are two fast regional clock networks within each half-quadrant (see Figure 4-44). The FCLK[1..0] clocks can also be used for high fanout control signals, such as asynchronous clears, presets, clock enables, or protocol control signals such as TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast clock networks. All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. The I/O interconnect drives this signal. Altera Corporation February 2005 4-71 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-43. EP1SGX25 & EP1SGX10 Device Fast Clock Pin Connections to Fast Regional Clocks Fast Clock [3..2] [1..0] FCLK[1..0] FCLK[1..0] FCLK[1..0] FCLK[1..0] [5..4] Fast Clock 4-72 Stratix GX Device Handbook, Volume 1 Fast Clock [7..6] Fast Clock Altera Corporation February 2005 Stratix GX Architecture Figure 4-44. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast Regional Clocks Fast Clock Fast Clock Fast Clock Fast Clock [3] [2] [1] [0] [4] [5] [6] [7] Fast Clock Fast Clock Fast Clock Fast Clock fclk[1..0] Combined Resources Within each region, there are 22 distinct dedicated clocking resources consisting of 16 global clock lines, 4 regional clock lines, and 2 fast regional clock lines. Multiplexers are used with these clocks to form 8-bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer at the LAB level selects two of the eight row clocks to feed the LE registers within the LAB. See Figure 4-45. Altera Corporation February 2005 4-73 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-45. Regional Clock Bus Clocks Available to a Quadrant or Half-Quadrant Vertical I/O Cell IO_CLK[7..0] Global Clock Network [15..0] Regional Clock Network [3..0] Clock [21:0] Lab Row Clock [7..0] Fast Regional Clock Network [1..0] Horizontal I/O Cell IO_CLK[7..0] IOE clocks have horizontal and vertical block regions that are clocked by eight I/O clock signals chosen from the 22-quadrant or half-quadrant clock resources. Figures 4-46 and 4-47 show the quadrant and halfquadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins). 4-74 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-46. EP1SGX25 & EP1SGX10 Device I/O Clock Groups IO_CLKA[7:0] IO_CLKB[7:0] 8 8 I/O Clock Regions 8 13 22 Clocks in the Quadrant 22 Clocks in the Quadrant IO_CLKH[7:0] 14 8 16 IO_CLKG[7:0] 22 Clocks in the Quadrant 22 Clocks in the Quadrant 15 8 8 IO_CLKF[7:0] Altera Corporation February 2005 IO_CLKE[7:0] 4-75 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-47. EP1SGX40 Device I/O Clock Groups IO_CLKA[7:0] IO_CLKC[7:0] IO_CLKB[7:0] 8 8 IO_CLKD[7:0] 8 8 I/O Clock Regions 8 13 IO_CLKP[7:0] 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8 14 IO_CLKO[7:0] 8 17 IO_CLKN[7:0] 8 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 16 15 IO_CLKM[7:0] 8 8 IO_CLKL[7:0] 8 IO_CLKK[7:0] 8 IO_CLKJ[7:0] IO_CLKI[7:0] You can use the Quartus II software to control whether a clock input pin is either global, regional, or fast regional. The Quartus II software automatically selects the clocking resources if not specified. Enhanced & Fast PLLs Stratix GX devices provide robust clock management and synthesis using up to four enhanced PLLs and four fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis. With features such as clock switchover, spread spectrum 4-76 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture clocking, programmable bandwidth, phase and delay control, and dynamic PLL reconfiguration, the Stratix GX device's enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Table 4-17 shows which PLLs are available for each Stratix GX device and their type. Table 4-18 shows the enhanced PLL and fast PLL features in Stratix GX devices. Table 4-17. Stratix GX Device PLL Availability Fast PLLs Enhanced PLLs Device 1 2 EP1SGX10 v v EP1SGX25 v v EP1SGX40 v v 3 (1) 4 (1) 7 8 v 9 (1) 10 (1) v 5 (2) 6 (2) v v v v v v 11 (3) 12 (3) v v Notes to Table 4-17: (1) (2) (3) PLLs 3, 4, 9, and 10 are not available in Stratix GX devices. However, these PLLs are listed in Table 4-17 because the Stratix GX PLL numbering scheme is consistent with Stratix devices. PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output. Table 4-18. Stratix GX Enhanced PLL & Fast PLL Features (Part 1 of 2) Feature Notes (1)-(8) Enhanced PLL Fast PLL m/ (n x post-scale counter) (1) m/(post-scale counter) (2) Phase shift Down to 156.25-ps increments (3), (4) Down to 125-ps increments (3), (4) Delay shift 250-ps increments for 3 ns Clock multiplication and division Clock switchover v PLL reconfiguration v Programmable bandwidth v Spread spectrum clocking v Programmable duty cycle v v Number of internal clock outputs 6 3 (5) Altera Corporation February 2005 4-77 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Table 4-18. Stratix GX Enhanced PLL & Fast PLL Features (Part 2 of 2) Feature Notes (1)-(8) Enhanced PLL Fast PLL Number of external clock outputs Four differential/eight singled-ended or one single-ended (6) (7) Number of feedback clock inputs 4 (8) Notes to Table 4-18: (1) (2) (3) (4) (5) (6) (7) (8) The maximum count value is 1024, with a 50% duty cycle setting on the counter. The maximum count value for any other duty cycle setting is 512. For fast PLLs, m and post-scale counters range from 1 to 32. The smallest phase shift is determined by the VCO period divided by 8. For degree increments, Stratix GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7 and 8 have two output ports per PLL. PLLs 1 and 2 have three output ports per PLL. Every Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with eight single-ended or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1SGX40 devices each have one single-ended output. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per PLL. Figure 4-48 shows a top-level diagram of the Stratix GX device and the PLL floorplan. 4-78 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-48. PLL Floorplan CLK[15..12] 5 FPLL7CLK 11 High-Speed Transceivers 7 inclk1 inclk2 CLK[3..0] 1 2 inclk3 inclk4 PLLs inclk5 FPLL8CLK 8 6 12 CLK[7..4] Figure 4-49 shows the global and regional clock connections from the PLL outputs and the CLK pins. Altera Corporation February 2005 4-79 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-49. Global & Regional Clock Connections From Side Pins & Fast PLL Outputs RCLK1 RCLK0 FPLL7CLK G1 G0 Note (1) G3 G2 l0 PLL 7 l 1 g0 CLK0 CLK1 l0 PLL 1 l 1 g0 CLK2 CLK3 l 02 PLL 2 l 1 g0 l0 PLL 8 l 1 g0 FPLL8CLK RCLK2 RCLK3 Global Clocks Regional Clocks Note to Figure 4-49: (1) PLLs 1,2 7, and 8 are fast PLLs. PLLs 7 and 8 do not drive global clocks. Figure 4-50 shows the global and regional clocking from enhanced PLL outputs and top CLK pins. 4-80 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-50. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Note (1) PLL5_OUT[3..0] CLK14 (1) PLL5_FB CLK15 (2) CLK12 (1) CLK13 (2) E[0..3] PLL 5 PLL 11 (4) L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL11_OUT RCLK10 RCLK11 Regional Clocks RCLK2 RCLK3 G12 G13 G14 G15 Global Clocks Regional Clocks G4 G5 G6 G7 RCLK6 RCLK7 RCLK12 RCLK13 PLL12_OUT L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL 6 PLL6_OUT[3..0] PLL 12 (4) PLL6_FB CLK4 (1) CLK6 (1) CLK7 (2) CLK5 (2) Note to Figure 4-50: (1) PLLs 5, 6, 11, and 12 are enhanced PLLs. Altera Corporation February 2005 4-81 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Enhanced PLLs Stratix GX devices contain up to four enhanced PLLs with advanced clock management features. Figure 4-51 shows a diagram of the enhanced PLL. Figure 4-51. Stratix GX Enhanced PLL Programmable Time Delay on Each PLL Port Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL /l0 t /l1 t Regional Clocks Clock Switch-Over Circuitry Spread Spectrum Phase Frequency Detector CLK0 4 t /n PFD Charge Pump 8 Loop Filter VCO CLK1 (1) FBIN t /m /g0 t /g1 t /g2 t /g3 t Global Clocks I/O Buffers (2) to I/O or general routing Lock Detect & Filter VCO Phase Selection Affecting All Outputs /e0 t /e1 t /e2 t /e3 t 4 I/O Buffers (3) Notes to Figure 4-51: (1) (2) (3) External feedback is available in PLLs 5 and 6. This external output is available from the g0 counter for PLLs 11 and 12. These counters and external outputs are available in PLLs 5 and 6. 4-82 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Clock Multiplication & Division Each Stratix GX device enhanced PLL provides clock synthesis for PLL output ports using m/(n x post-scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN x (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO's range). There is one pre-scale divider, n, and one multiply divider, m, per PLL, with a range of 1 to 512 on each. There are two post-scale dividers (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 512. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. Clock Switchover To effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. For this reason, Stratix GX device enhanced PLLs support a flexible clock switchover capability. Figure 4-52 shows a block diagram of the switchover circuit.The switchover circuit is configurable, so you can define how to implement it. Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present. Altera Corporation February 2005 4-83 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-52. Clock Switchover Circuitry CLK0_BAD CLK1_BAD Active Clock SMCLKSW Clock Sense Switch-Over State Machine CLKLOSS CLKSWITCH t CLK0 MUXOUT CLK1 n Counter PFD FBCLK Enhanced PLL Note to Figure 4-52: (1) PFD: phase frequency detector. There are two possible ways to use the clock switchover feature. You can use automatic switchover circuitry for switching between inputs of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 4-52. In this case, the secondary clock becomes the reference clock for the PLL. You can use the clkswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. This feature is useful when clock sources can originate from multiple cards on the backplane, 4-84 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture requiring a system-controlled switchover between frequencies of operation. You can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. During switchover, the PLL VCO continues to run and either slows down or speeds up, generating frequency drift on the PLL outputs. The clock switchover transitions without any glitches. After the switch, there is a finite resynchronization period to lock onto new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock relates to the PLL configuration and may be adjusted by using the programmable bandwidth feature of the PLL. The preliminary specification for the maximum time to relock is 100 s. f For more information on clock switchover, see AN313: Implementing Clock Switchover in Stratix & Stratix GX Devices. PLL Reconfiguration The PLL reconfiguration feature enables system logic to change Stratix GX device enhanced PLL counters and delay elements without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis, allowing real-time PLL frequency and output clock delay variation. You can sweep the PLL output frequencies and clock delay in prototype environments. The PLL reconfiguration feature can also dynamically or intelligently control system clock speeds or tCO delays in end systems. Clock delay elements at each PLL output port implement variable delay. Figure 4-53 shows a diagram of the overall dynamic PLL control feature for the counters and the clock delay elements. The configuration time is less than 20 s for the enhanced PLL using a input shift clock rate of 25 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted. Altera Corporation February 2005 4-85 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-53. Dynamically Programmable Counters & Delays in Stratix GX Device Enhanced PLLs All Output Counters and Clock Delay Settings can be Programmed Dynamically Counters and Clock Delay Settings are Programmable fREF /n t PFD Charge Pump Loop Filter VCO /g t /l t /e t scandata scanclk /m t scanaclr PLL reconfiguration data is shifted into serial registers from the logic array or external devices. The PLL input shift data uses a reference input shift clock. Once the last bit of the serial chain is clocked in, the register chain is synchronously loaded into the PLL configuration bits. The shift circuitry also provides an asynchronous clear for the serial registers. Programmable Bandwidth You have advanced control of the PLL bandwidth using the programmable control of the PLL loop characteristics, including loop filter and charge pump. The PLL's bandwidth is a measure of its ability to track the input clock and jitter. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. It also allows a wide band of input jitter spectrum to pass to the output. A low-bandwidth PLL takes longer to lock, but it attenuates all high-frequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable bandwidth is tuned by varying the charge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. You can manually adjust these values if desired. Bandwidth is programmable from 150 kHz to 2 MHz. 4-86 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture External Clock Outputs Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 4-54. Figure 4-54. External Clock Outputs for PLLs 5 & 6 From IOE (1) extclk0_a (2) e0 Counter From IOE (1) From IOE (1) extclk0_b extclk1_a e1 Counter 4 From IOE (1) From IOE (1) extclk1_b extclk2_a e2 Counter extclk2_b From IOE (1) From IOE (1) extclk3_a e3 Counter From IOE (1) extclk3_b Notes to Figure 4-54: (1) (2) Each external clock output pin can be used as a general purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter--either two outputs of the same frequency and phase or one shifted 180. Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each Altera Corporation February 2005 4-87 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock's overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180 out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table 4-19 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. You can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed. Table 4-19. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK LVTTL v v v v LVCMOS v v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v v v 3.3-V PCI-X v v v LVPECL v v v 3.3-V PCML v v v LVDS v v v HyperTransport technology v v Differential HSTL v v v v Differential SSTL 3.3-V GTL v v v 3.3-V GTL+ v v v 1.5-V HSTL class I v v v 1.5-V HSTL class II v v v SSTL-18 class I v v v SSTL-18 class II v v v SSTL-2 class I v v v SSTL-2 class II v v v 4-88 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-19. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK SSTL-3 class I v v v SSTL-3 class II v v v AGP (1x and 2x ) v v v CTT v v v Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 4-55). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 4-55. External Clock Outputs for Enhanced PLLs 11 & 12 g0 Counter CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1) From Internal Logic or IOE Note to Figure 4-55: (1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n. Stratix GX devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases. Clock Feedback The following four feedback modes in Stratix GX device enhanced PLLs allow multiplication and/or phase and delay shifting: Altera Corporation February 2005 Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. External feedback: The external feedback input pin, FBIN, is phase-aligned with the clock input, CLK, pin. Aligning these clocks allows you to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support 4-89 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop. Normal mode: If an internal clock is used in this mode, it is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. You define which internal clock output from the PLL should be phase-aligned to the internal clock pin. No compensation: In this mode, the PLL does not compensate for any clock networks or external clock outputs. Phase & Delay Shifting Stratix GX device enhanced PLLs provide advanced programmable phase and clock delay shifting. For phase shifting, you can specify a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Phase-shifting values in time units are allowed with a resolution range of 160 to 420 ps. This resolution is a function of frequency input and the multiplication and division factors. In other words, it is a function of the VCO period equal to one-eighth of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps. You can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. The phase tap feedback to the m counter can shift all outputs to a single phase or delay. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entered. In addition to the phase-shift feature, the fine tune clock delay shift feature provides advanced time delay shift control on each of the four PLL outputs. Each PLL output shifts in 250-ps increments for a range of -3.0 ns to +3.0 ns between any two outputs using discrete delay elements. Total delay shift between any two PLL outputs must be less than 3 ns. For example, shifts on outputs of -1 and +2 ns is allowed, but not -1 and +2.5 ns. There is some delay variation due to process, voltage, and temperature. Only the clock delay shift blocks can be controlled during system operation for dynamic clock delay control. Spread-Spectrum Clocking The Stratix GX device's enhanced PLLs use spread-spectrum technology to reduce electromagnetic interference generation from a system by distributing the energy over a broader frequency range. The enhanced 4-90 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture PLL typically provides 0.5% down spread modulation using a triangular profile. The modulation frequency is programmable. Enabling spread spectrum for a PLL affects all of its outputs. Lock Detect The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. You may need to gate the lock signal for use as a system control. The lock signal from the locked port can drive the logic array or an output pin. Whenever the PLL loses lock for any reason (be it excessive inclk jitter, clock switchover, PLL reconfiguration, power supply noise etc.), the PLL must be reset with the areset signal for correct phase shift operation. If the phase relationship between the input clock versus output clock, and between different output clocks from the PLL is not important in the design, then the PLL need not be reset. f See the Stratix GX FPGA Errata Sheet for more information on implementing the gated lock signal in the design. Programmable Duty Cycle The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. Advanced Clear & Enable Control There are several control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. Altera Corporation February 2005 4-91 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true: PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters resets, clearing the PLL output and placing the PLL out of lock. The VCO sets back to its nominal setting (~700 MHz). When driven low again, the PLL resynchronizes to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency starts at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system continues running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. You can either use your own control signal or a clkloss status signal to trigger pfdena. The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 4-56 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization. The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period 4-92 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Figure 4-56. extclkena Signals COUNTER OUTPUT CLKENA CLKOUT Fast PLLs Stratix GX devices contain up to four fast PLLs with high-speed serial interfacing ability, along with general-purpose features. Figure 4-57 shows a diagram of the fast PLL. Altera Corporation February 2005 4-93 Stratix GX Device Handbook, Volume 1 PLLs & Clock Networks Figure 4-57. Stratix GX Device Fast PLL Post-Scale Counters diffioclk1 (2) /l0 VCO Phase Selection Selectable at each PLL Output Port Global or regional clock (1) Clock Input Phase Frequency Detector Global or regional clock txload_en rxload_en /l1 Global or regional clock diffioclk2 (2) PFD Charge Pump 8 Loop Filter VCO /g0 Global or regional clock m / Notes to Figure 4-57: (1) (2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal. Clock Multiplication & Division The Stratix GX device's fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply divider, m, per fast PLL with a range of 1 to 32. There are two post scale L dividers for regional and/or LVDS interface clocks, and g0 counter for global clock output port; all range from 1 to 32. In the case of a high-speed differential interface, you can set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES. External Clock Outputs Each fast PLL supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. Any I/O pin can be driven by the fast PLL global or regional outputs as an external output 4-94 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank. Table 4-20 shows the I/O standards supported by fast PLL input pins. Table 4-20. Fast PLL Port Input Pin I/O Standards Input I/O Standard INCLK PLLENABLE LVTTL v v LVCMOS v v 2.5 V v 1.8 V v 1.5 V v 3.3-V PCI 3.3-V PCI-X LVPECL v 3.3-V PCML v LVDS v HyperTransport technology v Differential HSTL v Differential SSTL Altera Corporation February 2005 3.3-V GTL v 3.3-V GTL+ v 1.5V HSTL class I v 1.5V HSTL class II v SSTL-18 class I v SSTL-18 class II v SSTL-2 class I v SSTL-2 class II v SSTL-3 class I v SSTL-3 class II v AGP (1x and 2x ) v CTT v 4-95 Stratix GX Device Handbook, Volume 1 I/O Structure Phase Shifting Stratix GX device fast PLLs have advanced clock shift capability that enables programmable phase shifts. You can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can perform phase shifting in time units with a resolution range of 150 to 400 ps. This resolution is a function of the VCO period. Control Signals The fast PLL has the same lock output, pllenable input, and areset input control signals as the enhanced PLL. For more information on high-speed differential I/O support, see the High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. I/O Structure IOEs provide many features, including: Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Differential on-chip termination for LVDS I/O standard Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers The IOE in Stratix GX devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 4-58 shows the Stratix GX IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. 4-96 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-58. Stratix GX IOE Structure Logic Array OE Register D OE Q OE Register D Q Output Register Output A D Q CLK Output Register Output B D Q Input Register D Q Input A Input B Input Register D Q Input Latch D Q ENA The IOEs are located in I/O blocks around the periphery of the Stratix GX device. There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 4-59 shows how a row I/O block connects to the logic array. Figure 4-60 shows how a column I/O block connects to the logic array. Altera Corporation February 2005 4-97 Stratix GX Device Handbook, Volume 1 I/O Structure Figure 4-59. Row I/O Block Connection to the Interconnect R4, R8 & R24 Interconnects C4, C8 & C16 Interconnects I/O Interconnect I/O Block Local Interconnect 16 Control Signals from I/O Interconnect (1) 16 28 Data & Control Signals from Logic Array (2) 28 LAB Horizontal I/O Block io_dataouta[3..0] io_dataoutb[3..0] Direct Link Interconnect to Adjacent LAB Direct Link Interconnect to Adjacent LAB io_clk[7:0] LAB Local Interconnect Horizontal I/O Block Contains up to Four IOEs Notes to Figure 4-59: (1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_clk[3..0], and four clear signals io_bclr[3..0]. The 28 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear signals io_cclr[3..0]. 4-98 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-60. Column I/O Block Connection to the Interconnect 42 Data & Control Signals from Logic Array (2) 16 Control Signals from I/O Interconnect (1) Vertical I/O Block Contains up to Six IOEs Vertical I/O Block 16 42 io_clk[7..0] IO_datain[3:0] I/O Block Local Interconnect I/O Interconnect R4, R8 & R24 Interconnects LAB LAB Local Interconnect LAB LAB C4, C8 & C16 Interconnects Notes to Figure 4-60: (1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0]. Altera Corporation February 2005 4-99 Stratix GX Device Handbook, Volume 1 I/O Structure Stratix GX devices have an I/O interconnect similar to the R4 and C4 interconnect to drive high-fanout signals to and from the I/O blocks. There are 16 signals that drive into the I/O blocks composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The pin's datain signals can drive the IO interconnect, which in turn drives the logic array or other I/O blocks. In addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from regional, global, or fast regional clocks (see "PLLs & Clock Networks" on page 4-68). Figure 4-61 illustrates the signal paths through the I/O block. Figure 4-61. Signal Path Through the I/O Block Row or Column io_clk[7..0] io_boe[3..0] From I/O Interconnect To Other IOEs io_bce[3..0] io_bclk[3..0] io_bclr[3..0] To Logic Array io_datain0 io_datain1 oe ce_in ce_out io_coe io_cce_in Control Signal Selection aclr/preset IOE sclr io_cce_out From Logic Array clk_in io_cclr clk_out io_cclk io_dataout0 io_dataout1 Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 4-62 illustrates the control signal selection. 4-100 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-62. Control Signal Selection per IOE io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0] Dedicated I/O Clock [7..0] I/O Interconnect [15..0] Local Interconnect io_coe Local Interconnect io_cclr Local Interconnect io_cce_out Local Interconnect io_cce_in Local Interconnect io_cclk ce_out clk_out clk_in ce_in sclr/preset aclr/preset oe In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 4-63 shows the IOE in bidirectional configuration. Altera Corporation February 2005 4-101 Stratix GX Device Handbook, Volume 1 I/O Structure Figure 4-63. Stratix GX IOE in Bidirectional I/O Configuration Column or Row Interconnect Note (1) ioe_clk[7..0] I/O Interconnect [15..0] OE OE Register D Output tZX Delay Q clkout Output Enable Clock Enable Delay ce_out ENA CLRN/PRN OE Register tCO Delay VCCIO Output Clock Enable Delay Optional PCI Clamp VCCIO Programmable Pull-Up Resistor aclr/prn Chip-Wide Reset Logic Array to Output Register Delay Output Register D sclr/preset Q ENA CLRN/PRN Output Pin Delay Drive Strength Control Open-Drain Output Slew Control Input Pin to Logic Array Delay Input Register D clkin ce_in Input Clock Enable Delay Input Pin to Input Register Delay Bus-Hold Circuit Q ENA CLRN/PRN Note to Figure 4-63: (1) All input signals to the IOE can be inverted at the IOE. The Stratix GX device IOE includes programmable delays that can be activated to ensure zero hold times, input IOE register-to-logic array register transfers, or logic array-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. 4-102 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Programmable delays can increase the register-to-pin delays for output and/or output enable registers. A programmable delay exists to increase the tZX delay to the output pin, which is required for ZBT interfaces. Table 4-21 shows the programmable delays for Stratix GX devices. Table 4-21. Stratix GX Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Decrease input delay to internal cells Input pin to input register delay Decrease input delay to input register Output pin delay Increase delay to output pin Output enable register tCO delay Increase delay to output enable pin Output tZX delay Increase tZX delay to output pin Output clock enable delay Increase output clock enable delay Input clock enable delay Increase input clock enable delay Logic array to output register delay Decrease input delay to output register Output enable clock enable delay Increase output enable clock enable delay The IOE registers in Stratix GX devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers. Double-Data Rate I/O Pins Stratix GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes. Altera Corporation February 2005 4-103 Stratix GX Device Handbook, Volume 1 I/O Structure When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 4-64 shows an IOE configured for DDR input. Figure 4-65 shows the DDR input timing diagram. Figure 4-64. Stratix GX IOE in DDR Input I/O Configuration Column or Row Interconnect Note (1) VCCIO ioe_clk[7..0] (1) I/O Interconnect [15..0] (1) To DQS Local Bus (3) DQS Local Bus (1), (2) Optional PCI Clamp VCCIO Programmable Pull-Up Resistor Input Pin to Input Register Delay sclr Input Register D Q clkin Output Clock Enable Delay ENA CLRN/PRN Bus-Hold Circuit aclr/prn Chip-Wide Reset Latch Input Register D Q ENA CLRN/PRN D Q ENA CLRN/PRN Notes to Figure 4-64: (1) (2) (3) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only. 4-104 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-65. Input Timing Diagram in DDR Mode Data at input pin A0 B1 A1 B2 A2 B3 A3 B4 CLK A' A1 A2 A3 B' B1 B2 B3 Input To Logic Array When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from LEs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a x2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 4-66 shows the IOE configured for DDR output. Figure 4-67 shows the DDR output timing diagram. Altera Corporation February 2005 4-105 Stratix GX Device Handbook, Volume 1 I/O Structure Figure 4-66. Stratix GX IOE in DDR Output I/O Configuration Column or Row Interconnect Notes (1), (2) IOE_CLK[7..0] I/O Interconnect [15..0] OE Register D Q Output tZX Delay clkout ENA CLRN/PRN OE Register tCO Delay Output Enable Clock Enable Delay Output Clock Enable Delay aclr/prn VCCIO Optional PCI Clamp Chip-Wide Reset OE Register D VCCIO Q sclr ENA CLRN/PRN Logic Array to Output Register Delay Programmable Pull-Up Resistor Output Register D Q Output Pin Delay ENA CLRN/PRN Logic Array to Output Register Delay Used for DDR SDRAM Output Register D clk Drive Strength Control Open-Drain Output Slew Control Q ENA CLRN/PRN Bus-Hold Circuit Notes to Figure 4-66: (1) (2) All input signals to the IOE can be inverted at the IOE. The tristate is by default active high. It can, however, be designed to be active low. 4-106 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-67. Output Timing Diagram in DDR Mode CLK A A1 A2 A3 A4 B B1 B2 B3 B4 From Internal Registers B1 DDR output A1 B2 A2 B3 A3 The Stratix GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. Stratix GX device I/O pins transfer data on a DDR bidirectional bus to support DDR SDRAM. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements. External RAM Interfacing Stratix GX devices support DDR SDRAM at up to 200 MHz (400-Mbps data rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz. Stratix GX devices also provide preliminary support for reduced latency DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated phase-shift circuitry. 1 f Altera Corporation February 2005 In addition to the required signals for external memory interfacing, Stratix GX devices offer the optional clock enable signal. By default the Quartus II software sets the clock enable signal high, which tells the output register to update with new values. The output registers hold their own values if the design sets the clock enable signal low. See Figure 4-63. To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix GX devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix GX. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. 4-107 Stratix GX Device Handbook, Volume 1 I/O Structure Table 4-22 shows the performance specification for DDR SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM interfaces in EP1SGX10 through EP1SGX40 devices. The DDR SDRAM and QDR SRAM numbers in Table 4-22 have been verified with hardware characterization with third-party DDR SDRAM and QDR SRAM devices over temperature and voltage extremes. Table 4-22. External RAM Support in EP1SGX10 Through EP1SGX40 Devices Maximum Clock Rate (MHz) DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade DDR SDRAM (1), (2) SSTL-2 200 167 133 DDR SDRAM - side banks (2), (3), (4) SSTL-2 150 133 133 RLDRAM II (4) 1.8-V HSTL 200 (5) (5) QDR SRAM (6) 1.5-V HSTL 167 167 133 QDRII SRAM (6) 1.5-V HSTL 200 167 133 ZBT SRAM (7) LVTTL 200 200 167 Notes to Table 4-22: (1) (2) (3) (4) (5) (6) (7) These maximum clock rates apply if the Stratix GX device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix GX device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. These performance specifications are preliminary. This device does not support RLDRAM II. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. In addition to six I/O registers and one input latch in the IOE for interfacing to these high-speed memory interfaces, Stratix GX devices also have dedicated circuitry for interfacing with DDR SDRAM. In every Stratix GX device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz. These pins support DQS signals with DQ bus modes of x8, x16, or x32. 4-108 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-23 shows the number of DQ and DQS buses that are supported per device. Table 4-23. DQS & DQ Bus Mode Support Device Package Note (1) Number of x8 Groups Number of x16 Groups Number of x32 Groups EP1SGX10 672-pin FineLine BGA 12 (2) 0 0 EP1SGX25 672-pin FineLine BGA EP1SGX40 16 (3) 8 4 1,020-pin FineLine BGA 20 8 4 1,020-pin FineLine BGA 20 8 4 Notes to Table 4-23: (1) (2) (3) See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2 for VREF guidelines. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8. A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and clocks DQ input registers with the DQS signal. Two separate single phase-shifting reference circuits are located on the top and bottom of the Stratix GX device. Each circuit is driven by a system reference clock through the CLK pins that is the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase-shift circuitry on the bottom of the device. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device. The phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device shift by the same degree amount. For example, all 10 DQS pins on the top of the device can be shifted by 90 and all 10 DQS pins on the bottom of the device can be shifted by 72. The reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. Figure 4-68 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. Altera Corporation February 2005 4-109 Stratix GX Device Handbook, Volume 1 I/O Structure Figure 4-68. Simplified Diagram of the DQS Phase-Shift Circuitry Input Reference Clock Phase Comparator Up/Down Counter Delay Chains 6 Control Signals to DQS Pins See the External Memory Interfaces chapter of the Stratix GX Device Handbook, Volume 2 for more information on external memory interfaces. Programmable Drive Strength The output buffer for each Stratix GX device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standard has several levels of drive strength that the user can control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. 4-110 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-24 shows the possible settings for the I/O standards with drive strength control. Table 4-24. Programmable Drive Strength I/O Standard IOH / IOL Current Strength Setting (mA) 3.3-V LVTTL 24 (1), 16, 12, 8, 4 3.3-V LVCMOS 24 (2), 12 (1), 8, 4, 2 2.5-V LVTTL/LVCMOS 16 (1), 12, 8, 2 1.8-V LVTTL/LVCMOS 12 (1), 8, 2 1.5-V LVCMOS 8 (1), 4, 2 GTL/GTL+ 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-3 class I and II SSTL-2 class I and II SSTL-18 class I and II Support maximum and minimum strength Notes to Table 4-24: (1) (2) This is the Quartus II software default current setting. I/O banks 1 and 2 do not support this setting. The Quartus II software, beginning with version 4.2, reports current strength as "PCI Compliant" for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix GX devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative. Open-Drain Output Stratix GX devices provide an optional open-drain (equivalent to an open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (that is, interrupt and write-enable signals) that can be asserted by any of several devices. Altera Corporation February 2005 4-111 Stratix GX Device Handbook, Volume 1 I/O Structure Slew-Rate Control The output buffer for each Stratix GX device I/O pin has a programmable output slew-rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. Bus Hold Each Stratix GX device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Table 4-25 shows bus hold support for different pin types. Table 4-25. Bus Hold Support Pin Type I/O pins Bus Hold v CLK[15..0] CLK[0,1,2,3,8,9,10,11] FCLK v FPLL[7..10]CLK The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when using opendrain outputs with the GTL+ I/O standard or when the I/O pin has been configured for differential signals. 4-112 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to weakly pull the signal level to the last-driven state. The chapter DC & Switching Characteristics of the Stratix GX Device Handbook, Volume 1 gives the specific sustaining current driven through this resistor and the overdrive current used to identify the next-driven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Programmable Pull-Up Resistor Each Stratix GX device I/O pin provides an optional programmable pullup resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor (typically 25 k) weakly holds the output to the VCCIO level of the output pin's bank. Table 4-26 shows which pin types support the weak pull-up resistor feature. Table 4-26. Programmable Weak Pull-Up Resistor Support Pin Type I/O pins Programmable Weak Pull-Up Resistor v CLK[15..0] FCLK v FPLL[7..10]CLK Configuration pins JTAG pins v (1) Note to Table 4-26: (1) TDO pins do not support programmable weak pull-up resistors. Advanced I/O Standard Support Stratix GX device IOEs support the following I/O standards: Altera Corporation February 2005 LVTTL LVCMOS 1.5 V 1.8 V 2.5 V 3.3-V PCI 3.3-V PCI-X 1.0 3.3-V AGP (1x and 2x) 4-113 Stratix GX Device Handbook, Volume 1 I/O Structure LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL class I and II 1.8-V HSTL Class I and II SSTL-3 class I and II SSTL-2 class I and II SSTL-18 class I and II CTT Table 4-27 describes the I/O standards supported by Stratix GX devices. Table 4-27. Stratix GX Supported I/O Standards (Part 1 of 2) Type Input Reference Voltage (VREF) (V) Output Supply Voltage (VCCIO) (V) Board Termination Voltage (VTT) (V) LVTTL Single-ended N/A 3.3 N/A LVCMOS Single-ended N/A 3.3 N/A 2.5 V Single-ended N/A 2.5 N/A 1.8 V Single-ended N/A 1.8 N/A 1.5 V Single-ended N/A 1.5 N/A 3.3-V PCI Single-ended N/A 3.3 N/A 3.3-V PCI-X 1.0 I/O Standard Single-ended N/A 3.3 N/A LVDS Differential N/A 3.3 N/A LVPECL Differential N/A 3.3 N/A 3.3-V PCML Differential N/A 3.3 N/A HyperTransport Differential N/A 2.5 N/A Differential HSTL (1) Differential 0.75 1.5 0.75 Differential 1.25 2.5 1.25 Voltage-referenced 0.8 N/A 1.20 Differential SSTL (2) GTL GTL+ Voltage-referenced 1.0 N/A 1.5 1.5-V HSTL class I and II Voltage-referenced 0.75 1.5 0.75 1.8-V HSTL class I and II Voltage-referenced 0.9 1.8 0.9 SSTL-18 class I and II Voltage-referenced 0.90 1.8 0.90 SSTL-2 class I and II Voltage-referenced 1.25 2.5 1.25 4-114 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-27. Stratix GX Supported I/O Standards (Part 2 of 2) I/O Standard Type Input Reference Voltage (VREF) (V) Output Supply Voltage (VCCIO) (V) Board Termination Voltage (VTT) (V) SSTL-3 class I and II Voltage-referenced 1.5 3.3 1.5 AGP (1x and 2x) Voltage-referenced 1.32 3.3 N/A CTT Voltage-referenced 1.5 3.3 1.5 Notes to Table 4-27: (1) (2) This I/O standard is only available on input and output clock pins. This I/O standard is only available on output column clock pins. f For more information on I/O standards supported by Stratix GX devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. Stratix GX devices contain eight I/O banks in addition to the four enhanced PLL external clock out banks, as shown in Figure 4-69. The four I/O banks on the right and left of the device contain circuitry to support high-speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and HyperTransport inputs and outputs. These banks support all I/O standards listed in Table 4-27 except PCI I/O pins or PCI-X 1.0, GTL, SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix GX devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Table 4-28 shows I/O standard support for each I/O bank. Altera Corporation February 2005 4-115 Stratix GX Device Handbook, Volume 1 I/O Structure Figure 4-69. Stratix GX I/O Banks DQST9 PLL7 DQST8 DQST7 DQST6 Notes (1), (2), (3) DQST5 9 DQST4 PLL11 DQST3 DQST2 DQST1 DQST0 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 10 Bank 4 I/O Bank 13 (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3) Bank 2 VREF1B2 VREF2B2 VREF3B2 VREF4B2 Bank 3 (4) I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2) I/O Banks 1 and 2 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x PLL1 Bank 1 PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1 PLL5 VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 I/O Bank 17 (5) 1.5-V PCML (5) I/O Bank 16 (5) I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2) (4) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3) I/O Bank 15 (5) Bank 8 PLL8 I/O Bank 14 (5) 11 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 DQSB9 DQSB8 DQSB7 DQSB6 DQSB5 12 PLL6 Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 DQSB4 DQSB3 DQSB2 DQSB1 DQSB0 Notes to Figure 4-69: (1) (2) (3) (4) (5) Figure 4-69 is a top view of the Stratix GX silicon die. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x. For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix GX Device Handbook, Volume 2. These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled) 4-116 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-28 shows I/O standard support for each I/O bank. Table 4-28. I/O Support by Bank (Part 1 of 2) Top & Bottom Banks (3, 4, 7 & 8) Left Banks (1 & 2) Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) LVTTL v v v LVCMOS v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v 3.3-V PCI-X 1.0 v I/O Standard v v LVPECL v v 3.3-V PCML v v LVDS v v HyperTransport technology v v Differential HSTL (clock inputs) v v Differential HSTL (clock outputs) v Differential SSTL (clock outputs) v 3.3-V GTL v 3.3-V GTL+ v v v v 1.5-V HSTL class I v v v 1.5-V HSTL class II v 1.8-V HSTL class I v 1.8-V HSTL class II v SSTL-18 class I v SSTL-18 class II v SSTL-2 class I v v v v v v v v v SSTL-2 class II v v v SSTL-3 class I v v v Altera Corporation February 2005 v 4-117 Stratix GX Device Handbook, Volume 1 I/O Structure Table 4-28. I/O Support by Bank (Part 2 of 2) Top & Bottom Banks (3, 4, 7 & 8) Left Banks (1 & 2) Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) SSTL-3 class II v v v AGP (1x and 2x) v CTT v I/O Standard v v v Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard independently. Each bank also has dedicated VREF pins to support any one of the voltage-referenced standards (such as SSTL-3) independently. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. Differential On-Chip Termination Stratix GX devices provide differential on-chip termination (LVDS I/O standard) to reduce reflections and maintain signal integrity. Differential on-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. The internal termination is designed using transistors in the linear region of operation. Stratix GX devices support internal differential termination with a nominal resistance value of 137.5 for LVDS input receiver buffers. LVPECL signals require an external termination resistor. Figure 4-70 shows the device with differential termination. 4-118 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Figure 4-70. LVDS Input Differential On-Chip Termination Transmitting Device Receiving Device with Differential Termination Z0 + + RD Z0 I/O banks on the left and right side of the device support LVDS receiver (far-end) differential termination. Table 4-29 shows the Stratix GX device differential termination support. Table 4-29. Differential Termination Supported by I/O Banks Differential Termination Support I/O Standard Support Differential termination (1), (2) Top & Bottom Banks (3, 4, 7 & 8) Left Banks (1 & 2) v LVDS Notes to Table 4-29: (1) (2) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination. Differential termination is only supported for LVDS because of a 3.3-V VC C I O . Table 4-30 shows the termination support for different pin types. Table 4-30. Differential Termination Support Across Pin Types RD Pin Type Top and bottom I/O banks (3, 4, 7, and 8) v DIFFIO_RX[] CLK[0,2,9,11],CLK[4-7],CLK[12-15] CLK[1,3,8,10] v FCLK FPLL[7..10]CLK The differential on-chip resistance at the receiver input buffer is 118 20 %. Altera Corporation February 2005 4-119 Stratix GX Device Handbook, Volume 1 I/O Structure However, there is additional resistance present between the device ball and the input of the receiver buffer, as shown in Figure 4-71. This resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). Figure 4-71. Differential Resistance of LVDS Differential Pin Pair (RD) Pad Package Ball 0.3 9.3 0.3 9.3 LVDS Input Buffer RD Package Ball Differential On-Chip Termination Resistor Pad Table 4-31 defines the specification for internal termination resistance for commercial devices. Table 4-31. Differential On-Chip Termination Resistance Symbol RD (2) Description Internal differential termination for LVDS Conditions Unit Min Typ Max Commercial (1), (3) 110 135 165 Industrial (2), (3) 100 135 170 Notes to Table 4-31: (1) (2) (3) Data measured over minimum conditions (Tj = 0 C, VC C I O +5%) and maximum conditions (Tj = 85 C, VCCIO = -5%). Data measured over minimum conditions (Tj = -40 C, VCCIO +5%) and maximum conditions (Tj = 100 C, VCCIO = -5%). LVDS data rate is supported for 840 Mbps using internal differential termination. MultiVolt I/O Interface The Stratix GX architecture supports the MultiVolt I/O interface feature, which allows Stratix GX devices in all packages to interface with systems of different supply voltages. The Stratix GX VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 4-120 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 4-32 summarizes Stratix GX MultiVolt I/O support. Table 4-32. Stratix GX MultiVolt I/O Support Note (1) Input Signal (5) VCCIO (V) Output Signal (6) 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.5 v v v (2) v (2) v 1.8 v (2) v v (2) v (2) v (3) v 2.5 v v v (3) v (3) v 3.3 v (2) v v (3) v (3) v (3) v (4) 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V v v Notes to Table 4-32: (1) (2) (3) (4) (5) (6) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V. The input pin current may be slightly higher than the typical value. Although VCCIO specifies the voltage necessary for the Stratix GX device to drive out, a receiving device powered at a different level can still interface with the Stratix GX device if it has inputs that tolerate the VCCIO value. Stratix GX devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. This is the external signal that is driving the Stratix GX device. This represents the system voltage that Stratix GX supports when a VCCIO pin is connected to a specific voltage level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal coming out from Stratix GX is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Power Sequencing & Hot Socketing Because Stratix GX devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Signals can be driven into Stratix GX devices before and during power up without damaging the device. In addition, Stratix GX devices do not drive out during power up. Once operating conditions are reached and the device is configured, Stratix GX devices operate as specified by the user. For more information, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2. Altera Corporation February 2005 4-121 Stratix GX Device Handbook, Volume 1 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support IEEE Std. 1149.1 (JTAG) Boundary-Scan Support All Stratix GX devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix GX devices can also use the JTAG port for configuration together with either the Quartus II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix GX devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode. You can use this ability for JTAG testing before configuration when some of the Stratix GX pins drive or receive from other devices on the board using voltage-referenced standards. Because the Stratix GX device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows you to fully test I/O connection to other devices. The enhanced PLL reconfiguration bits are part of the JTAG chain before configuration and after power-up. After device configuration, the PLL reconfiguration bits are not part of the JTAG chain. Stratix GX devices also use the JTAG port to monitor the logic operation of the device with the SignalTap(R) embedded logic analyzer. Stratix GX devices support the JTAG instructions shown in Table 4-33. Table 4-33. Stratix GX JTAG Instructions (Part 1 of 2) JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap(R) embedded logic analyzer. EXTEST (1) Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. IDCODE Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. HIGHZ (1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. 4-122 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-33. Stratix GX JTAG Instructions (Part 2 of 2) JTAG Instruction Description CLAMP (1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. ICR instructions Used when configuring a Stratix GX device through the JTAG port with a MasterBlasterTM or ByteBlasterMVTM download cable, or when using a .jam file or .jbc file with an embedded processor. PULSE_NCONFIG Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. CONFIG_IO Allows the IOE standards to be configured through the JTAG chain. Stops configuration if executed during configuration. Can be executed before or after configuration. SignalTap instructions Monitors internal device operation with the SignalTap embedded logic analyzer. Note to Table 4-33: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. The Stratix GX device instruction register length is 10 bits, and the USERCODE register length is 32 bits. Tables 4-34 and 4-35 show the boundary-scan register length and IDCODE information for Stratix GX devices. Table 4-34. Stratix GX Boundary-Scan Register Length Device Boundary-Scan Register Length EP1SGX10 1,029 EP1SGX25 1,665 EP1SGX40 1,941 Table 4-35. 32-Bit Stratix GX Device IDCODE (Part 1 of 2) IDCODE (32 Bits) (1) Device Version (4 Bits) Part Number (16 Bits) Manufacturer Identity (11 Bits) LSB (1 Bit) (2) EP1SGX10 0000 0010 0000 0100 0001 000 0110 1110 1 EP1SGX25 0000 0010 0000 0100 0011 000 0110 1110 1 Altera Corporation February 2005 4-123 Stratix GX Device Handbook, Volume 1 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Table 4-35. 32-Bit Stratix GX Device IDCODE (Part 2 of 2) IDCODE (32 Bits) (1) Device Version (4 Bits) Part Number (16 Bits) Manufacturer Identity (11 Bits) LSB (1 Bit) (2) 0000 0010 0000 0100 0101 000 0110 1110 1 EP1SGX40 Notes to Table 4-35: (1) (2) The most significant bit (MSB) is at the left end of the string. The IDCODE's least significant bit (LSB) is always 1. Figure 4-72 shows the timing requirements for the JTAG signals. Figure 4-72. Stratix GX JTAG Waveforms TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX t JPXZ t JPCO TDO tJSH tJSSU Signal to Be Captured Signal to Be Driven tJSCO tJSZX tJSXZ Table 4-36 shows the JTAG timing parameters and values for Stratix GX devices. Table 4-36. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2) Symbol Parameter Min (ns) Max (ns) tJ C P TCK clock period 100 tJ C H TCK clock high time 50 tJ C L TCK clock low time 50 tJ P S U JTAG port setup time 20 4-124 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Stratix GX Architecture Table 4-36. Stratix GX JTAG Timing Parameters & Values (Part 2 of 2) Symbol Altera Corporation February 2005 Parameter Min (ns) Max (ns) tJ P H JTAG port hold time 45 tJ P C O JTAG port clock to output 25 tJ P Z X JTAG port high impedance to valid output 25 tJ P X Z JTAG port valid output to high impedance 25 tJ S S U Capture register setup time 20 tJ S H Capture register hold time 45 tJ S C O Update register clock to output 35 tJ S Z X Update register high impedance to valid output 35 tJ S X Z Update register valid output to high impedance 35 4-125 Stratix GX Device Handbook, Volume 1 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support 4-126 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 5. Configuration & Testing SGX51005-1.0 SignalTap Embedded Logic Analyzer Stratix(R) GX devices feature the SignalTap(R) embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA(R) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. Configuration The logic, circuitry, and interconnects in the Stratix GX architecture are configured with CMOS SRAM elements. Stratix GX devices are reconfigurable and are 100% tested prior to shipment. As a result, you do not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. In addition, you do not need to manage inventories of different ASIC designs. Stratix GX devices can be configured on the board for the specific functionality required. Stratix GX devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix GX devices via a serial data stream. Stratix GX devices can be configured in under 100 ms using 8-bit parallel data at 100 MHz. The Stratix GX device's optimized interface allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Stratix GX devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Stratix GX device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. Operating Modes The Stratix GX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power up, Altera Corporation February 2005 5-1 Configuration and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. A built-in weak pull-up resistor pulls all user I/O pins to VCCIO before and during device configuration. SRAM configuration elements allow Stratix GX devices to be reconfigured in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely. Configuration Schemes You can load the configuration data for a Stratix GX device with one of five configuration schemes (see Table 5-1), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix GX device. A configuration device can automatically configure a Stratix GX device at system power-up. You can configure multiple Stratix GX devices in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 5-1. Data Sources for Configuration Configuration Scheme Data Source Configuration device Enhanced or EPC2 configuration device Passive serial (PS) ByteBlasterMVTM or MasterBlasterTM download cable or serial data source Passive parallel asynchronous (PPA) Parallel data source Fast passive parallel Parallel data source JTAG MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file (.jam or .jbc) 5-2 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Configuration & Testing Partial Reconfiguration The enhanced PLLs within the Stratix GX device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See the Stratix GX Architecture chapter of the Stratix GX Device Handbook, Volume 1 for more information on Stratix GX PLLs. Remote Update Configuration Modes Stratix GX devices also support remote configuration using an Altera enhanced configuration device (for example, EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration which contains the design required to control remote updates and handle or recover from errors. You write the factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information. There are two remote configuration modes: remote and local configuration. You can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (for example, EPC16 devices) only support serial and parallel synchronous modes. Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the Stratix GX device. This host must support page mode settings similar to an EPC16 device. Remote Update Mode When the Stratix GX device is first powered-up in remote update programming mode, it loads the configuration located at page address 000. The factory configuration should always be located at page address 000, and should never be remotely updated. The factory configuration contains the required logic to perform the following operations: Altera Corporation February 2005 Determine the page address/load location for the next application's configuration data Recover from a previous configuration error 5-3 Stratix GX Device Handbook, Volume 1 Configuration Receive new configuration data and write it into the configuration device The factory configuration is the default and takes control if an error occurs while loading the application configuration. While in the factory configuration, the factory-configuration logic performs the following operations: Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should be if it is enabled The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations. If an error occurs in loading the application configuration, the configuration logic writes a status register to specify the cause of the reconfiguration. Once this occurs, the Stratix GX device automatically loads the factory configuration, which reads the status register and determines the reason for reconfiguration. Based on the reason, the factory configuration takes appropriate steps and writes the remote update control register to specify the next application configuration page to be loaded. When the Stratix GX device successfully loads the application configuration, it enters into user mode. The Stratix GX device then executes the main application of the user. Intellectual property (IP), such as a Nios(R) embedded processor, can help the Stratix GX device determine when remote update is coming. The Nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. The factory configuration reads the remote update status register and determine the valid application configuration to load. Figure 5-1 shows the Stratix GX remote update. Figure 5-2 shows the transition diagram for remote update mode. 5-4 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Configuration & Testing Figure 5-1. Stratix GX Device Remote Update (1) Watchdog Timer New Remote Configuration Data Configuration Device Application Configuration Page 7 Application Configuration Stratix GX Device Factory Configuration Page 6 Page 0 Configuration Device Updates Stratix GX Device with Factory Configuration (to Handle Update) or New Application Configuration Note to Figure 5-1: (1) When the Stratix GX device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device. Altera Corporation February 2005 5-5 Stratix GX Device Handbook, Volume 1 Configuration Figure 5-2. Remote Update Transition Diagram Notes (1), (2) Application 1 Configuration Power-Up Configuration Error Configuration Error Reload an Application Factory Configuration Reload an Application Configuration Error Application n Configuration Notes to Figure 5-2: (1) (2) Remote update of application configuration is controlled by a Nios embedded processor or user logic programmed in the factory or application configurations. Up to seven pages can be specified allowing up to seven different configuration applications. 5-6 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Configuration & Testing Local Update Mode Local update mode is a simplified version of the remote update. This feature is intended for simple systems that need to load a single application configuration immediately upon power-up without loading the factory configuration first. Local update designs have only one application configuration to load, so it does not require a factory configuration to determine which application configuration to use. Figure 5-3 shows the transition diagram for local update mode. Figure 5-3. Local Update Transition Diagram Power-Up or nCONFIG nCONFIG Application Configuration Configuration Error Configuration Error nCONFIG Factory Configuration Stratix GX Automated Single Event Upset (SEU) Detection Stratix GX devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to earth's North or South Pole require periodic checks to ensure continued data integrity. The error detection cyclic redundancy code (CRC) feature controlled by the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. Altera Corporation February 2005 5-7 Stratix GX Device Handbook, Volume 1 Temperature-Sensing Diode You can implement the error detection CRC feature with existing circuitry in Stratix GX devices, eliminating the need for external logic. For Stratix GX devices, the CRC is computed by Quartus II and downloaded into the device as a part of the configuration bit stream. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration. Custom-Built Circuitry Dedicated circuitry is built into Stratix GX devices to perform error detection automatically. This error detection circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a reconfiguration cycle. You can select the desired time between checks by adjusting a built-in clock divider. Software Interface In the Quartus II software version 4.1 and later, you can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 100 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices. TemperatureSensing Diode Stratix GX devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Stratix GX diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device's output represents the package temperature of the Stratix GX device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Stratix GX device to connect to the external temperature-sensing device, as shown in Figure 5-4. The temperature-sensing diode is a passive element and therefore can be used before the Stratix GX device is powered. 5-8 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 Configuration & Testing Figure 5-4. External Temperature-Sensing Diode Stratix GX Device Temperature-Sensing Device tempdiodep tempdioden Table 5-2 shows the specifications for bias voltage and current of the Stratix GX temperature-sensing diode. Table 5-2. Temperature-Sensing Diode Electrical Characteristics Parameter Minimum Typical Maximum Units IB I A S high 80 100 120 A IB I A S low 8 10 12 A VB P - VB N VB N Series resistance 0.3 0.9 0.7 V V 3 W The temperature-sensing diode works for the entire operating range shown in Figure 5-5. Altera Corporation February 2005 5-9 Stratix GX Device Handbook, Volume 1 Temperature-Sensing Diode Figure 5-5. Temperature Versus Temperature-Sensing Diode Voltage 0.95 0.90 100 A Bias Current 10 A Bias Current 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -55 -30 -5 20 45 70 95 120 Temperature ( C) 5-10 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005 6. DC & Switching Characteristics SGX51006-1.2 Operating Conditions Stratix(R) GX devices are offered in both commercial and industrial grades. However, industrial-grade devices may have limited speed-grade availability. Tables 6-1 through 6-12 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and transceiver block absolute maximum ratings. Notes for Tables 6-1 through 6-6 immediately follow Table 6-6, notes for Table 6-7 immediately follow that table, and notes for Tables 6-8 through 6-12 immediately follow Table 6-12. Table 6-1. Stratix GX Device Absolute Maximum Ratings Symbol VCCINT Parameter Notes (1), (2) Conditions With respect to ground (3) Supply voltage VCCIO Minimum Maximum Unit -0.5 2.4 V -0.5 4.6 V -0.5 4.6 V VI DC input voltage IOUT DC output current, per pin -25 25 mA TSTG Storage temperature No bias -65 150 C TAMB Ambient temperature Under bias -65 135 C TJ Junction temperature BGA packages under bias 135 C Table 6-2. Stratix GX Device Recommended Operating Conditions (Part 1 of 2) Symbol Parameter Conditions Minimum Maximum Unit 1.425 1.575 V 3.00 (3.135) 3.60 (3.465) V Supply voltage for output buffers, (4) 2.5-V operation 2.375 2.625 V Supply voltage for output buffers, (4) 1.8-V operation 1.71 1.89 V Supply voltage for output buffers, (4) 1.5-V operation 1.4 1.6 V -0.5 4.1 V (4) VCCINT Supply voltage for internal logic and input buffers VCCIO Supply voltage for output buffers, (4), (5) 3.3-V operation VI Note (7), (12), (13) Input voltage Altera Corporation June 2006 (3), (6) 6-1 Operating Conditions Table 6-2. Stratix GX Device Recommended Operating Conditions (Part 2 of 2) Symbol Parameter Conditions VO Output voltage TJ Operating junction temperature For commercial use For industrial use Table 6-3. Stratix GX Device DC Operating Conditions Symbol Parameter Note (7), (12), (13) Minimum Maximum Unit 0 VCCIO V 0 85 C -40 100 C Note (12) Conditions Minimum Typical Maximum Unit II Input pin leakage current VI = VC C I O m a x to 0 V (8) -10 10 A IOZ Tri-stated I/O pin leakage current VO = VC C I O m a x to 0 V (8) -10 10 A RCONF Value of I/O pin pull- VCCIO = 3.0 V (9) up resistor before VCCIO = 2.375 V (9) and during VCCIO = 1.71 V (9) configuration 20 50 k 30 80 k 60 150 k Table 6-4. Stratix GX Transceiver Block Absolute Maximum Ratings Symbol Parameter Conditions Minimum Maximum Units VC C A Transceiver block supply voltage Commercial and industrial -0.5 4.6 V VC C P Transceiver block supply voltage Commercial and industrial -0.5 2.4 V VC C R Transceiver block supply Voltage Commercial and industrial -0.5 2.4 V VC C T Transceiver block supply voltage Commercial and industrial -0.5 2.4 V VC C G Transceiver block supply voltage Commercial and industrial -0.5 2.4 V Receiver input voltage VI C M VI D single / 2 Commercial and industrial 1.675 (10), (13) V refclkb input VI C M VI D single / 2 Commercial and industrial 1.675 (10), (13) V voltage 6-2 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-5. Stratix GX Transceiver Block Operating Conditions Symbol Parameter Conditions Minimum Typical Maximum Units VC C A Transceiver block supply voltage Commercial and industrial 3.135 3.3 3.465 V VC C P Transceiver block supply voltage Commercial and industrial 1.425 1.5 1.575 V VC C R Transceiver block supply voltage Commercial and industrial 1.425 1.5 1.575 V VC C T Transceiver block supply voltage Commercial and industrial 1.425 1.5 1.575 V VC C G Transceiver block supply voltage Commercial and industrial 1.425 1.5 1.575 V VI D (differential p-p) Receiver input differential voltage swing Commercial and industrial 170 2,000 mV refclkb input differential voltage swing Commercial and industrial 400 2,000 mV VI C M Receiver input common mode voltage Commercial and industrial 1,025 1,175 mV VO D (differential p-p) Transmitter output differential Commercial voltage and industrial 1,600 mV VO C M Transmitter output common mode voltage Commercial and industrial RR E F (11) Reference resistor Commercial and industrial 1,100 350 750 2K -1% 2K mV 2K +1% Table 6-6. Stratix GX Transceiver Block On-Chip Termination (Part 1 of 2) Symbol Rx Tx Parameter Receiver termination Transmitter termination Altera Corporation June 2006 Conditions Min Typ Max Units Commercial and industrial, 100- setting 103 108 113 Commercial and industrial, 120- setting 120 128 134 Commercial and industrial, 150- setting 149 158 167 Commercial and industrial, 100- setting 103 108 113 Commercial and industrial, 120- setting 120 128 134 Commercial and industrial, 150- setting 149 158 167 6-3 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-6. Stratix GX Transceiver Block On-Chip Termination (Part 2 of 2) Symbol Refclkb Parameter Dedicated transceiver clock termination Conditions Min Typ Max Units Commercial and industrial, 100- setting 103 108 113 Commercial and industrial, 120- setting 120 128 134 Commercial and industrial, 150- setting 149 158 167 Notes to Tables 6-1 through 6-6: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 6-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (The information in this note does not include the transceiver pins. See note 13 for information about the transient voltage on the transceiver pins.) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses. All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. Typical values are for TA = 25 C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). Pin pull-up resistance values decrease if an external source drives the pin higher than VCCIO. The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated. Each usable quad requires its own RREF resistor path to ground. For example, the "D" in the EP1SGX25DC1020 device code means it has two usable quad so two different RREF pins must be connected to a RREF resistor each to ground. The DC signal on the RREF pin must be as clean as possible. Ensure that no noise is coupled to this pin. The Stratix GX device's recommended operating conditions do not include the transceiver. Refer to Tables 6-4 to 6-7. Minimum DC input to the transceiver pins is -0.5 V. During transitions, the transceiver pins may undershoot to -0.5 V or overshoot to 3.5 V for input currents less than 100 mA and periods shorter than 20 ns. Table 6-7. Stratix GX Transceiver Block AC Specification (Part 1 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Power per quadrant (PCS + PMA) 3.125 Gbps, 400mV Vo d 0 pre-emphasis 6-4 Stratix GX Device Handbook, Volume 1 Typ 450 Max -6 Commercial & Industrial Speed Grade (1) Min Typ 450 Max -7 Commercial & Industrial Speed Grade (1) Min Typ Unit Max mW Altera Corporation June 2006 DC & Switching Characteristics Table 6-7. Stratix GX Transceiver Block AC Specification (Part 2 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Typ Max -6 Commercial & Industrial Speed Grade (1) Min Typ Max -7 Commercial & Industrial Speed Grade (1) Min Typ Unit Max Reference Clock Jitter tolerance (peak-topeak) Reference input clock frequency Jitter components <20 MHz 20 20 20 ps Wideband 50 50 50 ps Dedicated 25 650 25 650 25 312.5 MHz PLD clock resources 25 325 25 325 25 156.25 MHz Serial data rate (general) Commercial / industrial 614 3,187.5 614 3,187.5 614 2,500 Mbps Serial data rate (8B/10B encoded) Commercial / industrial 500 3,187.5 500 3,187.5 500 2,500 Mbps 20 398.4 20 375 20 312.5 MHz 100 ppm refclkb pins Receiver Parallel transceiver/ logic array interface speed Rate matching frequency tolerance XAUI mode only 100 8B/10B Custom Receiver Jitter Tolerance using Encoded CJPAT 100 Note (2) Deterministic 500 Mbps jitter 0.45 0.45 0.45 UI Total jitter 0.71 0.71 0.71 UI 500 Mbps Fibre Channel Receiver Jitter Tolerance using 8B/10B Encoded CJTPAT Note (2) Deterministic 1.0625 Gbps jitter 0.37 0.37 0.37 UI Total jitter 0.68 0.68 0.68 UI 1.0625 Gbps Altera Corporation June 2006 6-5 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-7. Stratix GX Transceiver Block AC Specification (Part 3 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Sinusoidal jitter Typ Max -6 Commercial & Industrial Speed Grade (1) Min Typ Max -7 Commercial & Industrial Speed Grade (1) Min Typ Unit Max f = 42.5 kHz at 1.0625 Gbps 1.5 1.5 1.5 UI f = 637 kHz at 1.0625 Gbps 0.1 0.1 0.1 UI Deterministic 2.125 Gbps jitter 0.33 0.33 0.33 UI Total jitter 2.125 Gbps 0.62 0.62 0.62 UI Sinusoidal jitter f = 85 kHz at 2.125 Gbps 1.5 1.5 1.5 UI f = 1,274 kHz at 2.125 Gbps 0.1 0.1 0.1 UI Serial Rapid I/O Receiver Jitter Tolerance using 8B/10B Encoded CJPAT Deterministic 1.25 Gbps Note (2) 0.45 0.45 0.45 UI 1.25 Gbps 0.71 0.71 0.71 UI Deterministic 2.5 Gbps jitter 0.41 0.41 0.41 UI Total jitter 0.65 0.65 0.65 UI Deterministic 3.125 Gbps jitter 0.36 0.36 N/A UI Total jitter 0.60 0.60 N/A UI 1.5 1.5 1.5 UI 0.15 0.15 0.15 UI jitter Total jitter 2.5 Gbps 3.125 Gbps SONET Receiver Jitter Tolerance using PRBS23 Sinusoidal jitter f = 6 kHz at 2.48832 Gbps f = 1 MHz at 2.48832 Gbps Note (2) XAUI Receiver Jitter Tolerance using 8B/10B Encoded CJPAT Note (2) Deterministic 3.125 Gbps jitter 0.37 0.37 N/A UI Total jitter 0.65 0.65 N/A UI 3.125 Gbps 6-6 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-7. Stratix GX Transceiver Block AC Specification (Part 4 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Sinusoidal jitter Max Min Typ Max -7 Commercial & Industrial Speed Grade (1) Min Typ 8.5 8.5 N/A f = 1.875 MHz at 3.125 Gbps 0.1 0.1 N/A f = 20 MHz at 3.125 Gbps 0.1 0.1 N/A 10-12 10-12 10-12 Single width 7 32 7 32 7 Double width 5 19 5 19 5 40 XAUI mode / Channel to inter-quadrant channel bit only skew tolerance (5), (6) 40 Unit Max f = 22.1 kHz at 3.125 Gbps BER (12) Receive latency (4) Typ -6 Commercial & Industrial Speed Grade (1) 32 (3) 19 (3) N/A UI (7) Run-length (8) 80 80 80 UI Receive return loss (differential) 100 MHz to 2.5 Ghz -10 -10 -10 dB Receive return loss (common mode) 100 MHz to 2.5 Ghz -6 -6 -6 dB Transmitter Serial data rate Commercial / industrial Parallel transceiver/ core interface speed 500 3,187.5 500 3,187.5 500 2,500 Mbps 20 398.4 20 375 20 312.5 MHz 8B/10B Custom Transmitter Jitter using Encoded CRPAT Deterministic 500 Mbps jitter Pre-emphasis = 1 VOD = 1,400 mV Total jitter Altera Corporation June 2006 Note (9) 0.11 0.11 0.11 UI 0.18 0.18 0.18 UI 6-7 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-7. Stratix GX Transceiver Block AC Specification (Part 5 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Typ Max -6 Commercial & Industrial Speed Grade (1) Min Fibre Channel Transmitter Jitter using 8B/10B Encoded CRPAT Typ Max -7 Commercial & Industrial Speed Grade (1) Min Typ Unit Max Note (9) Deterministic 1.0625 Gbps jitter Pre-emphasis = 0 VOD = 1,200 mV Total jitter 0.09 0.09 0.09 UI 0.17 0.17 0.17 UI Deterministic 2.125 Gbps jitter Pre-emphasis= 1 VOD = 1,200 mV Total jitter 0.16 0.16 0.16 UI 0.33 0.33 0.33 UI Serial Rapid I/O Short Run Transmitter Jitter using 8B/10B Encoded CRPAT Note (9) 1.25 Gbps 0.09 0.09 0.09 UI Pre-emphasis = 1 VOD = 1,600 mV 0.17 0.17 0.17 UI Deterministic 2.5 Gbps jitter Pre-emphasis = 1 VOD = 800 mV Total jitter 0.15 0.15 0.15 UI 0.32 0.32 0.32 UI Deterministic 3.125 Gbps jitter Pre-emphasis = 1 VOD = 800 mV Total jitter 0.15 0.15 N/A UI 0.32 0.32 N/A UI Deterministic jitter Total jitter Serial Rapid I/O Long Run Transmitter Jitter using 8B/10B Encoded CRPAT Note (9) Deterministic 1.25 Gbps Pre-emphasis = 1 jitter VOD = 1,600 mV Total jitter 0.09 0.09 0.09 UI 0.17 0.17 0.17 UI Deterministic 2.5 Gbps Pre-emphasis = 2 jitter VOD = 1,400 mV Total jitter 0.18 0.18 0.18 UI 0.35 0.35 0.35 UI Deterministic 3.125 Gbps Pre-emphasis = 2 jitter VOD = 1,400 mV Total jitter 0.20 0.20 N/A UI 0.37 0.37 N/A UI 0.20 0.20 0.20 UI SONET Transmitter Jitter PRBS23 Total jitter Note (9) 2.48832 Gbps Pre-emphasis = 1 VOD = 800 mV 6-8 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-7. Stratix GX Transceiver Block AC Specification (Part 6 of 7) Symbol / Description Conditions -5 Commercial Speed Grade (1) Min Typ Max XAUI Transmitter Jitter using 8B/10B Encoded CJPAT Deterministic 3.125 Gbps Pre-emphasis = 0 jitter VOD = 1,200 mV Total jitter -6 Commercial & Industrial Speed Grade (1) Min Typ Max -7 Commercial & Industrial Speed Grade (1) Min Typ Unit Max Note (9) 0.15 0.15 N/A UI 0.32 0.32 N/A UI 3 3 N/A MHz High bandwidth setting at 3.125 Gbps 4.7 4.7 N/A MHz Low bandwidth setting at 2.5 Gbps 3.2 3.2 3.2 MHz High bandwidth setting at 2.5 Gbps 4.3 4.3 4.3 MHz Jitter transfer Low bandwidth setting at bandwidth 3.125 Gbps (10) Output tR I S E 20% to 80% 60 130 60 130 60 130 ps Output tFA L L 80% to 20% 60 130 60 130 60 130 ps Transmit latency (11) Single width 3 8 3 8 3 8 (3) Double width 3 7 3 7 3 7 (3) Intra differential pair skew Channel to channel skew Within a single quadrant Altera Corporation June 2006 10 10 10 ps 50 50 50 ps 6-9 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-7. Stratix GX Transceiver Block AC Specification (Part 7 of 7) Symbol / Description -5 Commercial Speed Grade (1) Conditions Min Output return 100 MHz to loss 2.5 GHz Typ -10 Max -6 Commercial & Industrial Speed Grade (1) Min Typ -7 Commercial & Industrial Speed Grade (1) Max -10 Min Typ Unit Max -10 dB Notes to Table 6-7: (1) All numbers for the -6 and -7 speed grades are for both commercial and industrial unless specified otherwise in the Conditions column. Speed grade -5 is available only for commercial specifications. (2) Not all VID and equalizer values will get the same results. The condition for the specification was that the VID before jitter was added is 1,000 mV and the equalizer was set to the maximum condition of 111 (equalizer control setting = 4 in the MegaWizard Plug-In Manager). (3) Number of parallel clocks. (4) Receive latency delay from serial receiver indata to parallel receiver data. (5) Per IEEE Standard 802.3ae @ 3.125 for -5 and -6. (6) The specification is for channel aligner tolerance. (7) UI = Unit Interval. (8) Run-length conditions are true for all data rates, but the average transition density must be enough to keep the receiver phase aligned and the overall data must be DC balanced. (9) Not all combinations of VOD and pre-emphasis will get the same results. (10) The numbers are for 3.125-Gbps data rate for -5 and -6 devices and 2.5 Gbps for -7 devices. (11) Transmitter latency delay from parallel transceiver data to serial transceiver out data. (12) The receiver operates with a BER of better than 10-12 in the presence of an input signal as defined in the XAUI driver template for 3.125 Gbps and in the PCI Exp transmitter eye mask for 2.5 Gbps. Table 6-8. LVTTL Specifications Symbol Parameter Conditions Minimum Maximum Units 3.0 3.6 V VCCIO Output supply voltage VI H High-level input voltage 1.7 4.1 V VIL Low-level input voltage -0.5 0.7 V VOH High-level output voltage IOH = -4 to -24 mA (1) VOL Low-level output voltage IOL = 4 to 24 mA (1) 2.4 V 0.45 V Minimum Maximum Units 3.0 3.6 V Table 6-9. LVCMOS Specifications Symbol VCCIO Parameter Output supply voltage Conditions VIH High-level input voltage 1.7 4.1 V VIL Low-level input voltage -0.5 0.7 V 6-10 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-9. LVCMOS Specifications Symbol Parameter Conditions Minimum VOH High-level output voltage VCCIO = 3.0, IOH = -0.1 mA VCCIO - 0.2 VOL Low-level output voltage VCCIO = 3.0, IOL = 0.1 mA Table 6-10. 2.5-V I/O Specifications Symbol Maximum Units V 0.2 V Minimum Maximum Units Note (1) Parameter Conditions VCCIO Output supply voltage 2.375 2.625 V VIH High-level input voltage 1.7 4.1 V VIL Low-level input voltage -0.5 0.7 V VOH High-level output voltage VOL Low-level output voltage IOH = -0.1 mA 2.1 V IOH = -1 mA 2.0 V IOH = -2 to -16 mA (1) 1.7 V IOL = 0.1 mA 0.2 V IOH = 1 mA 0.4 V IOH = 2 to 16 mA (1) 0.7 V Maximum Units Table 6-11. 1.8-V I/O Specifications Symbol Parameter Conditions Minimum VCCIO Output supply voltage 1.65 1.95 V VI H High-level input voltage 0.65 x VCCIO 2.25 V VIL Low-level input voltage -0.3 V VOH High-level output voltage IOH = -2 to -8 mA (1) VOL Low-level output voltage IOL = 2 to 8 mA (1) 0.35 x VCCIO VCCIO - 0.45 V 0.45 V Table 6-12. 1.5-V I/O Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Maximum Output supply voltage 1.4 VI H High-level input voltage 0.65 x VCCIO VCCIO + 0.3 V VIL Low-level input voltage -0.3 V VOH High-level output voltage Altera Corporation June 2006 IOH = -2 mA (1) 0.75 x VCCIO 1.6 Units VCCIO 0.35 x VCCIO V V 6-11 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-12. 1.5-V I/O Specifications (Part 2 of 2) Symbol VOL Parameter Conditions Minimum IOL = 2 mA (1) Low-level output voltage Maximum Units 0.25 x VCCIO V Note to Tables 6-8 through 6-12: (1) Drive strength is programmable according to values in found in the Stratix GX Architecture chapter of the Stratix GX Device Handbook, Volume 1. Figures 6-1 through 6-3 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 6-1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH VID Negative Channel (n) = VOL VCM Ground Differential Waveform (VID (Differential) = 2 x VID (single-ended)) VID p-n=0V VID 6-12 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Figure 6-2. Receiver Input Waveform Example with Values Single-Ended Waveform: What is Applied to the Pin (2) Positive Channel (p) VID = 1 V Negative Channel (n) VIH = 1.175 V + 0.5 V = 1.675 V VICM = 1.175 V (3) VIL = 1.175 V - 0.5 V = 0.675 V Ground Differential Waveform: As Seen by the Buffer or by Subtraction on an Oscilloscope VID = 1 V p-n=0V VID = 1 V Differential VID = 2 * VID (Single-Ended) = 2 V Notes to Figure 6-2: (1) (2) (3) The values in this figure are for example only. These values must meet the voltages specified in the section "Operating Conditions" on page 6-1. If internal termination is used, the common mode is generated after the pins. Figure 6-3. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH VID Negative Channel (n) = VOL VCM Ground Differential Waveform (VID (Differential) = 2 x VID (single-ended)) VID p-n=0V VID Altera Corporation June 2006 6-13 Stratix GX Device Handbook, Volume 1 Operating Conditions Tables 6-13 through 6-33 provide information about specifications and bus hold parameters for 1.5-V Stratix GX devices. Notes for Tables 6-14 through 6-33 immediately follow Table 6-33. Table 6-13. 3.3-V LVDS I/O Specifications Symbol Parameter VCCIO I/O supply voltage VI D (1) Input differential voltage swing (single-ended) VI C M (1) Input common-mode voltage Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 0.1 V < VC M < 1.1 V W = 1 through 10 300 1,000 mV 1.1 V < VC M < 1.6 V W=1 200 1,000 mV 1.1 V < VC M < 1.6 V W = 2 through 10 100 1,000 mV 1.6 V < VC M < 1.8 V W = 1 through 10 300 1,000 mV LVDS 0.3 V < VI D < 1.0 V W = 1 through 10 100 1,100 mV LVDS 0.3 V < VI D < 1.0 V W = 1 through 10 1,600 1,800 mV LVDS 0.2 V < VI D < 1.0 V W=1 1,100 1,600 mV LVDS 0.1 V < VI D < 1.0 V W = 2 through 10 1,100 1,600 mV 550 mV 50 mV 1,375 mV 50 mV 110 VOD Differential output voltage (single ended) RL = 100 VOD Change in VOD between high and low RL = 100 VOCM Output common-mode voltage RL = 100 VOCM Change in VOCM between high and low RL = 100 RL Receiver differential input resistor, external 250 1,125 90 375 1,200 100 Note to Table 6-13: (1) For up to 1 Gbps in DPA mode and 840 Mbps in non-DPA mode 6-14 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-14. 3.3-V PCML Specifications Symbol Parameter Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCIO I/O supply voltage VID Input differential voltage swing (single-ended) 300 600 mV VICM Input common mode voltage 1.5 3.465 V VOD Output differential voltage (single-ended) 300 500 mV VOD Change in VO D between high and low 50 mV VO C M Output common mode voltage 3.3 V VO C M Change in VO C M between high and low 50 mV VT Output termination voltage R1 Output external pull-up resistors 45 50 55 R2 Output external pull-up resistors 45 50 55 Minimum Typical Maximum Units 3.135 3.3 2.5 370 2.85 VC C I O V Table 6-15. LVPECL Specifications Symbol Parameter Conditions VCCIO I/O supply voltage VID Input differential voltage swing (single-ended) VICM Input common mode voltage VOD Differential output voltage (single ended) RL = 100 525 VO C M Output common mode voltage RL = 100 RL Receiver differential input resistor, external Altera Corporation June 2006 3.465 V 300 1,000 mV 1 2 V 700 970 mV 1.5 1.7 1.9 V 90 100 110 6-15 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-16. HyperTransport Specifications Symbol Parameter Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 380 485 820 mV 50 mV 780 mV 50 mV VCCIO I/O supply voltage VOD Differential output voltage (single ended) RL = 100 VO D Change in between high and low RL = 100 VOCM Output common mode voltage RL = 100 VO C M Change in between high and low RL = 100 VID Differential input voltage swing (single-ended) 300 900 mV VICM Input common mode voltage 300 900 mV RL Receiver differential input resistor, external 90 100 110 Minimum Typical Maximum Units 440 650 Table 6-17. 3.3-V PCI Specifications Symbol Parameter Conditions VCCIO Output supply voltage 3.0 3.6 V VIH High-level input voltage 0.5 x VCCIO 3.3 VCCIO + 0.5 V VIL Low-level input voltage -0.5 0.3 x VCCIO V VOH High-level output voltage IOUT = -500 A VOL Low-level output voltage IOUT = 1,500 A 0.9 x VCCIO V 0.1 x VCCIO V Maximum Units Table 6-18. PCI-X Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 3.0 3.6 V VIH High-level input voltage 0.5 x VCCIO VCCIO + 0.5 V VIL Low-level input voltage -0.5 0.35 x VCCIO V 6-16 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-18. PCI-X Specifications (Part 2 of 2) Symbol Parameter Conditions VIPU Input pull-up voltage VO H High-level output voltage IO U T = -500 A VO L Low-level output voltage IO U T = 1,500 A Minimum Typical Maximum Units 0.7 x VCCIO V 0.9 x VC C I O V 0.1 x VC C I O V Table 6-19. GTL+ I/O Specifications Typical Maximum Units VTT Symbol Termination voltage Parameter Conditions 1.35 Minimum 1.5 1.65 V VREF Reference voltage 0.88 1.0 1.12 V VIH High-level input voltage VREF + 0.1 VIL Low-level input voltage VOL Low-level output voltage V IOL = 36 mA (1) VR E F - 0.1 V 0.65 V Table 6-20. GTL I/O Specifications Symbol Parameter VTT Termination voltage VREF Reference voltage VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage Conditions Minimum Typical Maximum Units 1.14 1.2 1.26 V 0.74 0.8 0.86 V VREF + 0.05 V IOL = 40 mA (1) VR E F - 0.05 V 0.4 V Table 6-21. SSTL-18 Class I Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum VCCIO Output supply voltage VREF Reference voltage 0.8 VTT Termination voltage VR E F - 0.04 VIH(DC) High-level DC input voltage VR E F + 0.125 Altera Corporation June 2006 1.65 Typical Maximum Units 1.8 1.95 V 0.9 1.0 V VR E F VR E F + 0.04 V V 6-17 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-21. SSTL-18 Class I Specifications (Part 2 of 2) Symbol Parameter Conditions VIL(DC) Low-level DC input voltage VIH(AC) High-level AC input voltage VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = -6.7 mA (1) VOL Low-level output voltage IOL = 6.7 mA (1) Minimum Typical Maximum Units VR E F - 0.125 V VR E F + 0.275 V VR E F - 0.275 VTT + 0.475 V V VT T - 0.475 V Maximum Units Table 6-22. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 1.65 1.8 1.95 V VREF Reference voltage 0.8 0.9 1.0 V VTT Termination voltage VR E F - 0.04 VR E F + 0.04 V VIH(DC) High-level DC input voltage VR E F + 0.125 VIL(DC) Low-level DC input voltage VIH(AC) High-level AC input voltage VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = -13.4 mA (1) VOL Low-level output voltage IOL = 13.4 mA (1) VR E F V VR E F - 0.125 VR E F + 0.275 V V VR E F - 0.275 VTT + 0.630 V V VT T - 0.630 V Maximum Units Table 6-23. SSTL-2 Class I Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 2.375 2.625 V VTT Termination voltage VR E F - 0.04 VR E F VR E F + 0.04 V VREF Reference voltage 1.15 1.25 1.35 V VIH High-level input voltage VR E F + 0.18 3.0 V VIL Low-level input voltage -0.3 VR E F - 0.18 V 6-18 Stratix GX Device Handbook, Volume 1 2.5 Altera Corporation June 2006 DC & Switching Characteristics Table 6-23. SSTL-2 Class I Specifications (Part 2 of 2) Symbol Parameter Conditions VOH High-level output voltage IOH = -8.1 mA (1) VOL Low-level output voltage IOL = 8.1 mA (1) Minimum Typical Maximum VTT + 0.57 Units V VT T - 0.57 V Table 6-24. SSTL-2 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage 2.3 2.5 2.7 V VTT Termination voltage VR E F - 0.04 VR E F VR E F + 0.04 V VREF Reference voltage 1.15 1.25 1.35 V VIH High-level input voltage VR E F + 0.18 VCCIO + 0.3 V -0.3 VR E F - 0.18 V VIL Low-level input voltage VOH High-level output voltage IOH = -16.4 mA (1) VOL Low-level output voltage IOL = 16.4 mA (1) VTT + 0.76 V VT T - 0.76 V Maximum Units Table 6-25. SSTL-3 Class I Specifications Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 3.0 3.6 V VTT Termination voltage VR E F - 0.05 VR E F 3.3 VR E F + 0.05 V VREF Reference voltage 1.3 1.7 V 1.5 VIH High-level input voltage VR E F + 0.2 VCCIO + 0.3 V VIL Low-level input voltage -0.3 VR E F - 0.2 V VOH High-level output voltage IOH = -8 mA (1) VOL Low-level output voltage IOL = 8 mA (1) VTT + 0.6 V VT T - 0.6 V Table 6-26. SSTL-3 Class II Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical Output supply voltage 3.0 VTT Termination voltage VR E F - 0.05 VR E F VR E F + 0.05 V VREF Reference voltage 1.3 1.7 V VIH High-level input voltage VR E F + 0.2 VCCIO + 0.3 V 1.5 3.6 Units VCCIO Altera Corporation June 2006 3.3 Maximum V 6-19 Stratix GX Device Handbook, Volume 1 Operating Conditions Table 6-26. SSTL-3 Class II Specifications (Part 2 of 2) Symbol Parameter Conditions Minimum VIL Low-level input voltage VOH High-level output voltage IOH = -16 mA (1) VT T + 0.8 VOL Low-level output voltage IOL = 16 mA (1) Typical -0.3 Maximum VR E F - 0.2 Units V V VT T - 0.8 V Table 6-27. 3.3-V AGP 2x Specifications Symbol Parameter Conditions Minimum VCCIO Output supply voltage 3.15 VREF Reference voltage VIH High-level input voltage (2) VIL Low-level input voltage (2) VOH High-level output voltage IOUT = -0.5 mA VOL Low-level output voltage IOUT = 1.5 mA Typical 3.3 Maximum Units 3.45 V 0.39 x VC C I O 0.41 x VC C I O V 0.5 x VC C I O VCCIO + 0.5 V 0.3 x VC C I O V 3.6 V 0.1 x VC C I O V Maximum Units 0.9 x VC C I O Table 6-28. 3.3-V AGP 1x Specifications Symbol Parameter Conditions Minimum VCCIO Output supply voltage 3.15 VIH High-level input voltage (2) 0.5 x VC C I O VIL Low-level input voltage (2) VOH High-level output voltage IOUT = -0.5 mA VOL Low-level output voltage IOUT = 1.5 mA Typical 3.3 0.9 x VC C I O 3.45 V VCCIO + 0.5 V 0.3 x VC C I O V 3.6 V 0.1 x VC C I O V Maximum Units Table 6-29. 1.5-V HSTL Class I Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 1.4 1.5 1.6 V VREF Input reference voltage 0.68 0.75 0.9 V VTT Termination voltage 0.7 0.75 0.8 V VIH (DC) DC high-level input voltage VR E F + 0.1 VIL (DC) DC low-level input voltage -0.3 VIH (AC) AC high-level input voltage VR E F + 0.2 VIL (AC) AC low-level input voltage 6-20 Stratix GX Device Handbook, Volume 1 V VR E F - 0.1 V V VR E F - 0.2 V Altera Corporation June 2006 DC & Switching Characteristics Table 6-29. 1.5-V HSTL Class I Specifications (Part 2 of 2) Symbol Parameter Conditions VOH High-level output voltage IO H = 8 mA (1) VOL Low-level output voltage IO H = -8 mA (1) Minimum Typical Maximum VC C I O - 0.4 Units V 0.4 V Table 6-30. 1.5-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage 1.4 1.5 1.6 V VREF Input reference voltage 0.68 0.75 0.9 V VTT Termination voltage 0.7 0.75 0.8 V VIH (DC) DC high-level input voltage VR E F + 0.1 VIL (DC) DC low-level input voltage -0.3 VR E F + 0.2 VIH (AC) AC high-level input voltage VIL (AC) AC low-level input voltage VOH High-level output voltage IOH = 16 mA (1) VOL Low-level output voltage IO H = -16 mA (1) V VR E F - 0.1 V V VR E F - 0.2 VC C I O - 0.4 V V 0.4 V Table 6-31. 1.5-V Differential HSTL Specifications Symbol Parameter Conditions Minimum VCCIO I/O supply voltage 1.4 VDIF (DC) DC input differential voltage 0.2 VCM (DC) DC common mode input voltage 0.68 VDIF (AC) AC differential input voltage 0.4 Typical 1.5 Maximum 1.6 Units V V 0.9 V V Table 6-32. CTT I/O Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage 3.0 3.3 3.6 V VT T /VREF Termination and input reference voltage 1.35 1.5 1.65 V VIH High-level input voltage VR E F + 0.2 VIL Low-level input voltage Altera Corporation June 2006 V VR E F - 0.2 V 6-21 Stratix GX Device Handbook, Volume 1 Power Consumption Table 6-32. CTT I/O Specifications (Part 2 of 2) Symbol Parameter Conditions VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA IO Output leakage current (when output is high Z) GND VO U T VC C I O Minimum Typical Maximum VR E F + 0.4 Units V -10 VR E F - 0.4 V 10 A Table 6-33. Bus Hold Parameters VC C I O Level Parameter Conditions 1.5 V Min 1.8 V Max Min Max 2.5 V Min Units 3.3 V Max Min Max VIN > VIL (maximum) 25 30 50 70 A High sustaining VIN < VIH current (minimum) -25 -30 -50 -70 A Low sustaining current Low overdrive current 0 V < VIN < VCCIO 160 200 300 500 A High overdrive current 0 V < VIN < VCCIO -160 -200 -300 -500 A 2.0 V Bus-hold trip point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 Notes to Tables 6-14 through 6-33: (1) (2) Drive strength is programmable according to values in the Stratix GX Architecture chapter of the Stratix GX Device Handbook, Volume 1. VR E F specifies the center point of the switching range. Power Consumption Detailed power consumption information for Stratix GX devices will be released when available. Timing Model The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix GX device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. 6-22 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Preliminary & Final Timing Timing models can have either preliminary or final status. The Quartus(R) II software displays an informational message during the design compilation if the timing models are preliminary. Table 6-34 shows the status of the Stratix GX device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions. Table 6-34. Stratix GX Device Timing Model Status Device Preliminary Final EP1SGX10 -- v EP1SGX25 -- v EP1SGX40 -- v Performance Table 6-35 shows Stratix GX device performance for some common designs. All performance values were obtained with Quartus II software compilation of LPM, or MegaCore(R) functions for the FIR and FFT designs. Table 6-35. Stratix GX Device Performance (Part 1 of 3) Notes (1), (2) Resources Used Applications LE Performance TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade -6 Speed Grade -7 Speed Grade Units 16-to-1 multiplexer (1) 22 0 0 407.83 324.56 288.68 MHz 32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 MHz 16-bit counter 16 0 0 422.11 422.11 390.01 MHz 64-bit counter 64 0 0 321.85 290.52 261.23 MHz Altera Corporation June 2006 6-23 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-35. Stratix GX Device Performance (Part 2 of 3) Notes (1), (2) Resources Used Applications Simple dual-port RAM 32 x 18 TriMatrix memory bit M512 block FIFO 32 x 18 bit TriMatrix memory M4K block TriMatrix memory M-RAM block Simple dual-port RAM 128 x 36 bit Performance TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade -6 Speed Grade -7 Speed Grade Units 0 1 0 317.76 277.62 241.48 MHz 30 1 0 319.18 278.86 242.54 MHz 0 1 0 290.86 255.55 222.27 MHz True dual-port RAM 128 x 18 bit 0 1 0 290.86 255.55 222.27 MHz FIFO 128 x 36 bit 34 1 0 290.86 255.55 222.27 MHz Single port RAM 4K x 144 bit 1 1 0 255.95 223.06 194.06 MHz Simple dual-port RAM 4K x 144 bit 0 1 0 255.95 233.06 194.06 MHz True dual-port RAM 4K x 144 bit 0 1 0 255.95 233.06 194.06 MHz Single port RAM 8K x 72 bit 0 1 0 278.94 243.19 211.59 MHz Simple dual-port RAM 8K x 72 bit 0 1 0 255.95 223.06 194.06 MHz True dual-port RAM 8K x 72 bit 0 1 0 255.95 223.06 194.06 MHz Single port RAM 16K x 36 bit 0 1 0 280.66 254.32 221.28 MHz Simple dual-port RAM 16K x 36 bit 0 1 0 269.83 237.69 206.82 MHz 6-24 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-35. Stratix GX Device Performance (Part 3 of 3) Notes (1), (2) Resources Used Applications TriMatrix memory M-RAM block DSP block Larger Designs Performance TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade -6 Speed Grade -7 Speed Grade Units True dual-port RAM 16K x 36 bit 0 1 0 269.83 237.69 206.82 MHz Single port RAM 32K x 18 bit 0 1 0 275.86 244.55 212.76 MHz Simple dual-port RAM 32K x 18 bit 0 1 0 275.86 244.55 212.76 MHz True dual-port RAM 32K x 18 bit 0 1 0 275.86 244.55 212.76 MHz Single port RAM 64K x 9 bit 0 1 0 287.85 253.29 220.36 MHz Simple dual-port RAM 64K x 9 bit 0 1 0 287.85 253.29 220.36 MHz True dual-port RAM 64K x 9 bit 0 1 0 287.85 253.29 220.36 MHz 9 x 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 MHz 18 x 18-bit multiplier (4) 0 0 1 278.78 237.41 206.52 MHz 36 x 36-bit multiplier (4) 0 0 1 148.25 134.71 117.16 MHz 36 x 36-bit multiplier (5) 0 0 1 278.78 237.41 206.52 MHz 18-bit, 4-tap FIR filter 0 0 1 278.78 237.41 206.52 MHz 8-bit, 16-tap parallel FIR filter 58 0 4 141.26 133.49 114.88 MHz 8-bit, 1,024-point FFT function 870 5 1 261.09 235.51 205.21 MHz Notes to Table 6-35: (1) (2) (3) (4) (5) These design performance numbers were obtained using the Quartus II software. Numbers not listed will be included in a future version of the data sheet. This application uses registered inputs and outputs. This application uses registered multiplier input and output stages within the DSP block. This application uses registered multiplier input, pipeline, and output stages within the DSP block. Altera Corporation June 2006 6-25 Stratix GX Device Handbook, Volume 1 Timing Model Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 6-36 through 6-42 describe the Stratix GX device internal timing microparameters for LEs, IOEs, TriMatrixTM memory structures, DSP blocks, and MultiTrack interconnects. Table 6-36. LE Internal Timing Microparameter Descriptions Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LE combinational LUT delay for data-in to data-out tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Minimum clock high or low time Table 6-37. IOE Internal Timing Microparameter Descriptions Symbol Parameter tSU IOE input and output register setup time before clock tH IOE input and output register hold time after clock tCO IOE input and output register clock-to-output delay tPIN2COMBOUT_R Row input pin to IOE combinational output tPIN2COMBOUT_C Column input pin to IOE combinational output tCOMBIN2PIN_R Row IOE data input to combinational output pin tCOMBIN2PIN_C Column IOE data input to combinational output pin tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Minimum clock high or low time 6-26 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-38. DSP Block Internal Timing Microparameter Descriptions Symbol Parameter tSU Input, pipeline, and output register setup time before clock tH Input, pipeline, and output register hold time after clock tCO Input, pipeline, and output register clock-to-output delay tINREG2PIPE9 Input register to DSP block pipeline register in 9 x 9-bit mode tINREG2PIPE18 Input register to DSP block pipeline register in 18 x 18-bit mode tPIPE2OUTREG2ADD DSP block pipeline register to output register delay in twomultipliers adder mode tPIPE2OUTREG4ADD DSP Block Pipeline Register to output register delay in fourmultipliers adder mode tPD9 Combinational input to output delay for 9 x 9-bit mode tPD18 Combinational input to output delay for 18 x 18-bit mode tPD36 Combinational input to output delay for 36 x 36-bit mode tCLR Minimum clear pulse width tCLKHL Minimum clock high or low time Table 6-39. M512 Block Internal Timing Microparameter Descriptions Symbol Altera Corporation June 2006 Parameter tM512RC Synchronous read cycle time tM512WC Synchronous write cycle time tM512WERESU Write or read enable setup time before clock tM512WEREH Write or read enable hold time after clock tM512DATASU Data setup time before clock tM512DATAH Data hold time after clock tM512WADDRSU Write address setup time before clock tM512WADDRH Write address hold time after clock tM512RADDRSU Read address setup time before clock tM512RADDRH Read address hold time after clock tM512DATACO1 Clock-to-output delay when using output registers tM512DATACO2 Clock-to-output delay without output registers tM512CLKHL Minimum clock high or low time tM512CLR Minimum clear pulse width 6-27 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-40. M4K Block Internal Timing Microparameter Descriptions Symbol Parameter tM4KRC Synchronous read cycle time tM4KWC Synchronous write cycle time tM4KWERESU Write or read enable setup time before clock tM4KWEREH Write or read enable hold time after clock tM4KBESU Byte enable setup time before clock tM4KBEH Byte enable hold time after clock tM4KDATAASU A port data setup time before clock tM4KDATAAH A port data hold time after clock tM4KADDRASU A port address setup time before clock tM4KADDRAH A port address hold time after clock tM4KDATABSU B port data setup time before clock tM4KDATABH B port data hold time after clock tM4KADDRBSU B port address setup time before clock tM4KADDRBH B port address hold time after clock tM4KDATACO1 Clock-to-output delay when using output registers tM4KDATACO2 Clock-to-output delay without output registers tM4KCLKHL Minimum clock high or low time tM4KCLR Minimum clear pulse width Table 6-41. M-RAM Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol Parameter tM R A M R C Synchronous read cycle time tMRAMWC Synchronous write cycle time tMRAMWERESU Write or read enable setup time before clock tMRAMWEREH Write or read enable hold time after clock tMRAMBESU Byte enable setup time before clock tMRAMBEH Byte enable hold time after clock tMRAMDATAASU A port data setup time before clock tMRAMDATAAH A port data hold time after clock tMRAMADDRASU A port address setup time before clock tMRAMADDRAH A port address hold time after clock 6-28 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-41. M-RAM Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol Parameter tMRAMDATABSU B port setup time before clock tMRAMDATABH B port hold time after clock tMRAMADDRBSU B port address setup time before clock tMRAMADDRBH B port address hold time after clock tMRAMDATACO1 Clock-to-output delay when using output registers tMRAMDATACO2 Clock-to-output delay without output registers tMRAMCLKHL Minimum clock high or low time tMRAMCLR Minimum clear pulse width Table 6-42. Routing Delay Internal Timing Microparameter Descriptions Symbol Parameter tR4 Delay for an R4 line with average loading; covers a distance of four LAB columns tR8 Delay for an R8 line with average loading; covers a distance of eight LAB columns tR24 Delay for an R24 line with average loading; covers a distance of 24 LAB columns tC4 Delay for an C4 line with average loading; covers a distance of four LAB rows tC8 Delay for an C8 line with average loading; covers a distance of eight LAB rows tC16 Delay for an C16 line with average loading; covers a distance of 16 LAB rows tLOCAL Local interconnect delay Table 6-43. Stratix GX Reset & PLL Lock Time Parameter Descriptions (Part 1 of 2) Symbol Altera Corporation June 2006 Parameter tA N A L O G R E S E T P W Pulse width to power down analog circuits. tD I G I T A L R E S E T P W Pulse width to reset digital circuits tT X _ P L L _ L O C K The time it takes the tx_pll to lock to the reference clock. 6-29 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-43. Stratix GX Reset & PLL Lock Time Parameter Descriptions (Part 2 of 2) Symbol Parameter tR X _ F R E Q L O C K The time until the clock recovery unit (CRU) switches to data mode from lock to reference mode. tR X _ F R E Q L O C K 2 P H A S E L O C K The time until CRU phase locks to data after switching from lock to data mode. Figure 6-4 shows the TriMatrix memory waveforms for the M512, M4K, and M-RAM timing parameters shown in Tables 6-39 through 6-41. Figure 6-4. Dual-Port RAM Timing Microparameter Waveform wrclock tWEREH tWERESU wren tWADDRH tWADDRSU wraddress an-1 an a0 a1 a2 a3 a4 a5 a6 din4 din5 din6 tDATAH data-in din-1 din tDATASU rdclock tWEREH tWERESU rden tRC rdaddress bn b1 b0 b2 b3 tDATACO1 reg_data-out doutn-2 doutn-1 doutn dout0 tDATACO2 unreg_data-out doutn-1 doutn 6-30 Stratix GX Device Handbook, Volume 1 dout0 Altera Corporation June 2006 DC & Switching Characteristics Figure 6-5. Stratix GX Transceiver Reset & PLL Lock Time Waveform Note (1) tWEREH tWERESU rden tRC rdaddress bn b0 tDATACO1 reg_data-out doutn-1 doutn-2 doutn tDATACO2 unreg_data-out doutn doutn-1 Note to Figure 6-5: (1) Waveforms are for minimum pulse width timing and output timing only. Please refer to the Stratix GX Transceiver User Guide for the complete reset sequence. Tables 6-44 through 6-50 show the internal timing microparameters for all Stratix GX devices. Table 6-44. LE Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min Altera Corporation June 2006 tSU 10 tH 100 Max Min Max 10 Min Max 11 100 ps 114 ps tCO 156 176 202 ps tLUT 366 459 527 ps tCLR 100 100 114 ps tPRE 100 100 114 ps tCLKHL 100 100 114 ps 6-31 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-45. IOE Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min tSU 64 tH 76 tCO tPIN2COMBOUT_R tPIN2COMBOUT_C Max Min Max 68 Min Max 68 80 ps 80 ps 162 171 171 ps 1,038 1,093 1,256 ps 927 976 1,122 ps tCOMBIN2PIN_R 2,944 3,099 3,563 ps tCOMBIN2PIN_C 3,189 3,357 3,860 ps tCLR 262 276 317 ps tPRE 262 276 317 ps tCLKHL 90 95 109 ps Table 6-46. DSP Block Internal Timing Microparameters Symbol -5 Speed Grade Min Max -6 Speed Grade Min Max -7 Speed Grade Min Unit Max tSU 0 0 0 ps tH 67 75 86 ps tCO 142 158 181 ps tINREG2PIPE18 2,613 2,982 3,429 ps tINREG2PIPE9 3,390 3,993 4,591 ps tPIPE2OUTREG2ADD 2,002 2,203 2,533 ps tPIPE2OUTREG4ADD 2,899 3,189 3,667 ps tPD9 3,709 4,081 4,692 ps tPD18 4,795 5,275 6,065 ps tPD36 7,495 8,245 9,481 ps tCLR tCLKHL 6-32 Stratix GX Device Handbook, Volume 1 450 500 575 ps 1,350 1,500 1,724 ps Altera Corporation June 2006 DC & Switching Characteristics Table 6-47. M512 Block Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min tM512RC Max Min 3,340 tM512WC Max Min 3,816 3,318 Max 4,387 3,590 4,128 ps ps tM512WERESU 110 123 141 ps tM512WERH 34 38 43 ps tM512DATASU 110 123 141 ps tM512DATAH 34 38 43 ps tM512WADDRASU 110 123 141 ps tM512WADDRH 34 38 43 ps tM512DATACO1 424 472 541 ps tM512DATACO2 3,366 3,846 4,421 ps tM512CLKHL 150 167 192 ps tM512CLR 170 189 217 ps Table 6-48. M4K Block Internal Timing Microparameters (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min Altera Corporation June 2006 Max Min Max Min Max tM4KRC 3,807 4,320 4,967 ps tM4KWC 2,556 2,840 3,265 ps tM4KWERESU 131 149 171 ps tM4KWERH 34 38 43 ps tM4KDATASU 131 149 171 ps tM4KDATAH 34 38 43 ps tM4KWADDRASU 131 149 171 ps tM4KWADDRH 34 38 43 ps tM4KRADDRASU 131 149 171 ps tM4KRADDRH 34 38 43 ps tM4KDATABSU 131 149 171 ps tM4KDATABH 34 38 43 ps tM4KADDRBSU 131 149 171 ps tM4KADDRBH 34 38 43 ps 6-33 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-48. M4K Block Internal Timing Microparameters (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min Max tM4KDATACO1 Min Max 571 tM4KDATACO2 Min Max 635 3,984 729 4,507 5,182 ps ps tM4KCLKHL 150 167 192 ps tM4KCLR 170 189 255 ps Table 6-49. M-RAM Block Internal Timing Microparameters -5 -6 -7 Symbol Unit Min Max Min Max Min Max tMRAMRC 4,364 4,838 5,562 ps tMRAMWC 3,654 4,127 4,746 ps tMRAMWERESU 25 25 28 ps tMRAMWERH 18 20 23 ps tMRAMDATASU 25 25 28 ps tMRAMDATAH 18 20 23 ps tMRAMWADDRASU 25 25 28 ps tMRAMWADDRH 18 20 23 ps tMRAMRADDRASU 25 25 28 ps tMRAMRADDRH 18 20 23 ps tMRAMDATABSU 25 25 28 ps tMRAMDATABH 18 20 23 ps tMRAMADDRBSU 25 25 28 ps tMRAMADDRBH 18 20 23 ps tMRAMDATACO1 1,038 1,053 1,210 ps tMRAMDATACO2 4,362 4,939 5,678 ps tMRAMCLKHL 270 300 345 ps tMRAMCLR 135 150 172 ps 6-34 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-50. Stratix GX Transceiver Reset & PLL Lock Time Parameters Symbol Min Typ Max Units tA N A L O G R E S E T P W (5) 1 mS tD I G I TA L R E S E T P W (5) 4 Parallel clock cycle tT X _ P L L _ L O C K (3) 10 S tR X _ F R E Q L O C K (4) 5 mS tR X _ F R E Q L O C K 2 P H A S E L O C K (2) 5 S Notes to Table 6-50: (1) (2) (3) (4) (5) The minimum pulse width specified is associated with the power-down of circuits. The clock recovery unit (CRU) phase locked-to-data time is based on a data rate of 500 Mbps and 8B/10B encoded data. After #pll_areset, pll_enable, or PLL power-up, the time required for the transceiver PLL to lock to the reference clock. After #rx_analogreset, the time for the CRU to switch to lock-to-data mode. There is no maximum pulse width specification. The GXB can be held in reset indefinitely. Routing delays vary depending on the load on a specific routing line. The Quartus II software reports the routing delay information when running the timing analysis for a design. Contact Altera Applications Engineering for more details. External Timing Parameters External timing parameters are specified by device density and speed grade. Figure 6-6 shows the timing model for bidirectional IOE pin timing. All registers are within the IOE. Altera Corporation June 2006 6-35 Stratix GX Device Handbook, Volume 1 Timing Model Figure 6-6. External Timing in Stratix GX Devices OE Register Dedicated Clock D PRN Q tINSU tINH tOUTCO CLRN Output Register D PRN Q Bidirectional Pin CLRN Input Register PRN D Q CLRN All external I/O timing parameters shown are for 3.3-V LVTTL or LVCMOS I/O standards with the maximum current strength. For external I/O timing using standards other than LVTTL or LVCMOS use the I/O standard input and output delay adders in Tables 6-72 through 6-76. Table 6-51 shows the external I/O timing parameters when using fast regional clock networks. Table 6-51. Stratix GX Fast Regional Clock External I/O Timing Parameters Symbol Parameter tINSU Setup time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin tINH Hold time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin tOUTCO Clock-to-output delay output or bidirectional pin using column IOE output register with fast regional clock fed by FCLK pin Notes (1), (2) Conditions CL O A D = 10 pF Notes to Table 6-51: (1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device and speed grade and whether it is tCO or tSU. You should use the Quartus II software to verify the external timing for any pin. 6-36 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-52 shows the external I/O timing parameters when using regional clock networks. Table 6-52. Stratix GX Regional Clock External I/O Timing Parameters Symbol Notes (1), (2) Parameter Conditions tINSU Setup time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin tINH Hold time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin tOUTCO Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock fed by CLK pin tINSUPLL Setup time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting tINHPLL Hold time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting tOUTCOPLL Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock Enhanced PLL with default phase setting CL O A D = 10 pF CL O A D = 10 pF Notes to Table 6-52: (1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external timing for any pin. Table 6-53 shows the external I/O timing parameters when using global clock networks. Table 6-53. Stratix GX Global Clock External I/O Timing Parameters (Part 1 of 2) Symbol Parameter Notes (1), (2) Conditions tINSU Setup time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin tINH Hold time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin tOUTCO CL O A D = 10 pF Clock-to-output delay output or bidirectional pin using column IOE output register with global clock fed by CLK pin tINSUPLL Setup time for input or bidirectional pin using column IOE input register with global clock fed by Enhanced PLL with default phase setting Altera Corporation June 2006 6-37 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-53. Stratix GX Global Clock External I/O Timing Parameters (Part 2 of 2) Symbol Parameter Notes (1), (2) Conditions tINHPLL Hold time for input or bidirectional pin using column IOE input register with global clock fed by enhanced PLL with default phase setting tOUTCOPLL Clock-to-output delay output or bidirectional pin using column IOE output register with global clock enhanced PLL with default phase setting CL O A D = 10 pF Notes to Table 6-53: (1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external timing for any pin. Tables 6-54 through 6-59 show the external timing parameters on column and row pins for EP1SGX10 devices. Table 6-54. EP1SGX10 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 2.245 tINH 0.000 tOUTCO 2.000 Max Max 2.332 2.666 0.000 4.597 2.000 Max ns 0.000 4.920 2.000 ns 5.635 ns Table 6-55. EP1SGX10 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max 2.218 Max tINSU 2.114 2.348 tINH 0.000 tOUTCO 2.000 tINSUPLL 1.035 0.941 1.070 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 0.000 4.728 2.629 6-38 Stratix GX Device Handbook, Volume 1 2.000 0.500 ns 0.000 5.078 2.769 2.000 0.500 ns 6.004 3.158 ns ns Altera Corporation June 2006 DC & Switching Characteristics Table 6-56. EP1SGX10 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 1.785 tINH 0.000 tOUTCO 2.000 tINSUPLL 0.988 tINHPLL 0.000 tOUTCOPLL 0.500 Max Max 1.814 2.087 0.000 5.057 2.000 2.000 ns 6.214 1.066 0.000 0.500 ns 0.000 5.438 0.936 2.634 Max ns 0.000 2.774 0.500 ns ns 3.162 ns Table 6-57. EP1SGX10 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 2.194 tINH 0.000 tOUTCO 2.000 Max Max 2.384 2.727 0.000 4.956 2.000 Max ns 0.000 4.971 2.000 ns 5.463 ns Table 6-58. EP1SGX10 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 2.244 2.413 2.574 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 tINSUPLL 1.126 1.186 1.352 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 4.906 2.804 2.000 0.500 4.942 2.627 2.000 0.500 5.616 2.765 ns ns Table 6-59. EP1SGX10 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 1.919 2.062 2.368 ns tINH 0.000 0.000 0.000 ns Altera Corporation June 2006 6-39 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-59. EP1SGX10 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Max Min Max Min Max tOUTCO 2.000 5.231 2.000 5.293 2.000 5.822 tINSUPLL 1.126 1.186 1.352 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 Symbol Unit 2.804 0.500 2.627 0.500 2.765 ns ns Tables 6-60 through 6-65 show the external timing parameters on column and row pins for EP1SGX25 devices. Table 6-60. EP1SGX25 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 2.418 2.618 3.014 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 4.524 2.000 4.834 2.000 5.538 ns Table 6-61. EP1SGX25 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 1.713 1.838 2.069 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 tINSUPLL 1.061 tINHPLL 0.000 tOUTCOPLL 0.500 5.229 2.000 5.614 1.155 6-40 Stratix GX Device Handbook, Volume 1 0.500 6.432 1.284 0.000 2.661 2.000 ns 0.000 2.799 0.500 ns ns 3.195 ns Altera Corporation June 2006 DC & Switching Characteristics Table 6-62. EP1SGX25 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 1.790 tINH 0.000 tOUTCO 2.000 tINSUPLL 1.046 tINHPLL 0.000 tOUTCOPLL 0.500 Max Max 1.883 2.120 0.000 5.194 2.000 2.000 ns 6.381 1.220 0.000 0.500 ns 0.000 5.569 1.141 2.676 Max ns 0.000 2.813 0.500 ns ns 3.208 ns Table 6-63. EP1SGX25 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Unit Min tINSU 2.394 tINH 0.000 tOUTCO 2.000 Max Min Max 2.594 2.000 Max 2.936 0.000 4.456 Min ns 0.000 4.761 2.000 ns 5.454 ns Table 6-64. EP1SGX25 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 1.970 2.109 2.377 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 tINSUPLL 1.326 1.386 1.552 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 4.880 2.304 2.000 0.500 5.246 2.427 2.000 0.500 6.013 2.765 ns ns Table 6-65. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 1.963 2.108 2.379 ns tINH 0.000 0.000 0.000 ns Altera Corporation June 2006 6-41 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-65. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Max Min Max Min Max tOUTCO 2.000 4.887 2.000 5.247 2.000 6.011 tINSUPLL 1.326 1.386 1.552 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 Symbol Unit 2.304 0.500 2.427 0.500 2.765 ns ns Tables 6-66 through 6-71 show the external timing parameters on column and row pins for EP1SGX40 devices. Table 6-66. EP1SGX40 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 2.704 2.912 3.235 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 5.060 2.000 5.432 2.000 6.226 ns Table 6-67. EP1SGX40 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 2.467 2.671 3.011 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 tINSUPLL 1.254 tINHPLL 0.000 tOUTCOPLL 0.500 5.255 2.000 5.673 1.259 6-42 Stratix GX Device Handbook, Volume 1 0.500 6.501 1.445 0.000 2.610 2.000 ns 0.000 2.751 0.500 ns ns 3.134 ns Altera Corporation June 2006 DC & Switching Characteristics Table 6-68. EP1SGX40 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 2.033 tINH 0.000 tOUTCO 2.000 tINSUPLL 1.228 tINHPLL 0.000 tOUTCOPLL 0.500 Max Max 2.184 2.451 0.000 5.689 2.000 2.000 ns 7.010 1.415 0.000 0.500 ns 0.000 6.116 1.278 2.594 Max ns 0.000 2.732 0.500 ns ns 3.113 ns Table 6-69. EP1SGX40 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit tINSU 2.450 tINH 0.000 tOUTCO 2.000 Max Max 2.662 3.046 0.000 4.880 2.000 Max ns 0.000 5.241 2.000 ns 6.004 ns Table 6-70. EP1SGX40 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 2.398 2.567 2.938 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 tINSUPLL 1.126 1.186 1.352 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 4.932 2.304 2.000 0.500 5.336 2.427 2.000 0.500 6.112 2.765 ns ns Table 6-71. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Symbol Unit Max Max Max tINSU 1.965 2.128 2.429 ns tINH 0.000 0.000 0.000 ns Altera Corporation June 2006 6-43 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-71. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Max Min Max Min Max tOUTCO 2.000 5.365 2.000 5.775 2.000 6.621 tINSUPLL 1.126 1.186 1.352 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 Symbol Unit 2.304 0.500 2.427 0.500 2.765 ns ns External I/O Delay Parameters External I/O delay timing parameters, both for I/O standard input and output adders and programmable input and output delays, are specified by speed grade, independent of device density. Tables 6-72 through 6-77 show the adder delays associated with column and row I/O pins. If an I/O standard is selected other than LVTTL 24 mA with a fast slew rate, add the selected delay to the external tCO and tSU I/O parameters. Table 6-72. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard Unit Max Max Max LVCMOS 0 0 0 ps 3.3-V LVTTL 0 0 0 ps 2.5-V LVTTL 30 31 35 ps 1.8-V LVTTL 150 157 180 ps 1.5-V LVTTL 210 220 252 ps GTL 220 231 265 ps GTL+ 220 231 265 ps 0 0 0 ps 3.3-V PCI 3.3-V PCI-X 1.0 0 0 0 ps Compact PCI 0 0 0 ps AGP 1x 0 0 0 ps AGP 2x 0 0 0 ps CTT 120 126 144 ps SSTL-3 class I -30 -32 -37 ps SSTL-3 class II -30 -32 -37 ps 6-44 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-72. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard Unit Max Max Max SSTL-2 class I -70 -74 -86 ps SSTL-2 class II -70 -74 -86 ps SSTL-18 class I 180 189 217 ps SSTL-18 class II 180 189 217 ps 1.5-V HSTL class I 120 126 144 ps 1.5-V HSTL class II 120 126 144 ps 1.8-V HSTL class I 70 73 83 ps 1.8-V HSTL class II 70 73 83 ps Table 6-73. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard Unit Max Max Max LVCMOS 0 0 0 ps 3.3-V LVTTL 0 0 0 ps 2.5-V LVTTL 30 31 35 ps 1.8-V LVTTL 150 157 180 ps 1.5-V LVTTL 210 220 252 ps GTL 0 0 0 ps GTL+ 220 231 265 ps 0 0 0 ps 3.3-V PCI 3.3-V PCI-X 1.0 0 0 0 ps Compact PCI 0 0 0 ps AGP 1x 0 0 0 ps AGP 2x 0 0 0 ps CTT 80 84 96 ps SSTL-3 class I -30 -32 -37 ps SSTL-3 class II -30 -32 -37 ps SSTL-2 class I -70 -74 -86 ps SSTL-2 class II -70 -74 -86 ps SSTL-18 class I 180 189 217 ps SSTL-18 class II 1.5-V HSTL class I Altera Corporation June 2006 0 0 0 ps 130 136 156 ps 6-45 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-73. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard Unit Max Max Max 1.5-V HSTL class II 0 0 0 ps 1.8-V HSTL class I 70 73 83 ps 1.8-V HSTL class II 70 73 83 ps LVDS (1) 40 42 48 ps LVPECL (1) -50 -53 -61 ps 3.3-V PCML (1) 330 346 397 ps HyperTransport (1) 80 84 96 ps Table 6-74. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Standard LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL Unit Max Max Max 2 mA 570 599 689 ps 4 mA 570 599 689 ps 8 mA 350 368 423 ps 12 mA 130 137 157 ps 24 mA 0 0 0 ps 4 mA 570 599 689 ps 8 mA 350 368 423 ps 12 mA 130 137 157 ps 16 mA 70 74 85 ps 24 mA 0 0 0 ps 2 mA 830 872 1,002 ps 8 mA 250 263 302 ps 12 mA 140 147 169 ps 16 mA 100 105 120 ps 2 mA 420 441 507 ps 8 mA 350 368 423 ps 12 mA 350 368 423 ps 2 mA 1,740 1,827 2,101 ps 4 mA 1,160 1,218 1,400 ps 8 mA GTL 6-46 Stratix GX Device Handbook, Volume 1 690 725 833 ps -150 -157 -181 ps Altera Corporation June 2006 DC & Switching Characteristics Table 6-74. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Standard Unit Max Max Max GTL+ -110 -115 -133 ps 3.3-V PCI -230 -241 -277 ps 3.3-V PCI-X 1.0 -230 -241 -277 ps Compact PCI -230 -241 -277 ps AGP 1x -30 -31 -36 ps AGP 2x -30 -31 -36 ps CTT 50 53 61 ps SSTL-3 class I 90 95 109 ps SSTL-3 class II -50 -52 -60 ps SSTL-2 class I 100 105 120 ps SSTL-2 class II 20 21 24 ps SSTL-18 class I 230 242 278 ps SSTL-18 class II 0 0 0 ps 1.5-V HSTL class I 380 399 459 ps 1.5-V HSTL class II 190 200 230 ps 1.8-V HSTL class I 380 399 459 ps 1.8-V HSTL class II 390 410 471 ps Table 6-75. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Standard LVCMOS 3.3-V LVTTL Altera Corporation June 2006 Unit Max Max Max 2 mA 570 599 689 ps 4 mA 570 599 689 ps 8 mA 350 368 423 ps 12 mA 130 137 157 ps 24 mA 0 0 0 ps 4 mA 570 599 689 ps 8 mA 350 368 423 ps 12 mA 130 137 157 ps 16 mA 70 74 85 ps 24 mA 0 0 0 ps 6-47 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-75. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Standard 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL Unit Max Max Max 2 mA 830 872 1,002 ps 8 mA 250 263 302 ps 12 mA 140 147 169 ps 16 mA 100 105 120 ps 2 mA 1,510 1,586 1,824 ps 8 mA 420 441 507 ps 12 mA 350 368 423 ps 2 mA 1,740 1,827 2,101 ps 4 mA 1,160 1,218 1,400 ps 8 mA 690 725 833 ps CTT 50 53 61 ps SSTL-3 class I 90 95 109 ps SSTL-3 class II -50 -52 -60 ps SSTL-2 class I 100 105 120 ps SSTL-2 class II 20 21 24 ps LVDS (1) -20 -21 -24 ps LVPECL (1) 40 42 48 ps PCML (1) -60 -63 -73 ps HyperTransport Technology (1) 70 74 85 ps Table 6-76. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard LVCMOS Unit Max Max Max 2 mA 1,911 2,011 2,312 ps 4 mA 1,911 2,011 2,312 ps 8 mA 1,691 1,780 2,046 ps 12 mA 1,471 1,549 1,780 ps 24 mA 1,341 1,412 1,623 ps 6-48 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-76. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL Unit Max Max Max 4 mA 1,993 2,097 2,411 ps 8 mA 1,773 1,866 2,145 ps 12 mA 1,553 1,635 1,879 ps 16 mA 1,493 1,572 1,807 ps 24 mA 1,423 1,498 1,722 ps 2 mA 2,631 2,768 3,182 ps 8 mA 2,051 2,159 2,482 ps 12 mA 1,941 2,043 2,349 ps 16 mA 1,901 2,001 2,300 ps 2 mA 4,632 4,873 5,604 ps 8 mA 3,542 3,728 4,287 ps 12 mA 3,472 3,655 4,203 ps 2 mA 6,620 6,964 8,008 ps 4 mA 6,040 6,355 7,307 ps 8 mA 5,570 5,862 6,740 ps 1,191 1,255 1,442 ps GTL+ 1,231 1,297 1,90 ps 3.3-V PCI 1,111 1,171 1,346 ps 3.3-V PCI-X 1.0 1,111 1,171 1,346 ps Compact PCI 1,111 1,171 1,346 ps AGP 1x 1,311 1,381 1,587 ps AGP 2x 1,311 1,381 1,587 ps CTT 1,391 1,465 1,684 ps SSTL-3 class I 1,431 1,507 1,732 ps SSTL-3 class II 1,291 1,360 1,563 ps SSTL-2 class I 1,912 2,013 2,314 ps SSTL-2 class II 1,832 1,929 2,218 ps SSTL-18 class I 3,097 3,260 3,748 ps SSTL-18 class II 2,867 3,018 3,470 ps 1.5-V HSTL class I 4,916 5,174 5,950 ps 1.5-V HSTL class II 4,726 4,975 5,721 ps 1.8-V HSTL class I 3,247 3,417 3,929 ps 1.8-V HSTL class II 3,257 3,428 3,941 ps Altera Corporation June 2006 6-49 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-77. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min I/O Standard LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL Unit Max Max Max 2 mA 1,930 2,031 2,335 ps 4 mA 1,930 2,031 2,335 ps 8 mA 1,710 1,800 2,069 ps 12 mA 1,490 1,569 1,803 ps 4 mA 1,953 2,055 2,363 ps 8 mA 1,733 1,824 2,097 ps 12 mA 1,513 1,593 1,831 ps 16 mA 1,453 1,530 1,759 ps 2 mA 2,632 2,769 3,183 ps 8 mA 2,052 2,160 2,483 ps 12 mA 1,942 2,044 2,350 ps 16 mA 1,902 2,002 2,301 ps 2 mA 4,537 4,773 5,489 ps 8 mA 3,447 3,628 4,172 ps 12 mA 3,377 3,555 4,088 ps 2 mA 6,575 6,917 7,954 ps 4 mA 5,995 6,308 7,253 ps 8 mA 5,525 5,815 6,686 ps CTT 1,410 1,485 1,707 ps SSTL-3 class I 1,450 1,527 1,755 ps SSTL-3 class II 1,310 1,380 1,586 ps SSTL-2 class I 1,797 1,892 2,175 ps SSTL-2 class II 1,717 1,808 2,079 ps LVDS (1) 1,340 1,411 1,622 ps LVPECL (1) 1,400 1,474 1,694 ps 3.3-V PCML (1) 1,300 1,369 1,573 ps HyperTransport technology (1) 1,430 1,506 1,731 ps Note to Tables 6-72 through 6-77: (1) These parameters are only available on the left side row I/O pins. 6-50 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Tables 6-78 and 6-79 show the adder delays for the column and row IOE programmable delays, respectively. These delays are controlled with the Quartus II software logic options listed in the Parameter column. Table 6-78. Stratix GX IOE Programmable Delays on Column Pins -5 Speed Grade Parameter -7 Speed Grade Unit Min Decrease input delay to internal cells -6 Speed Grade Setting Max Min Max Min Max Off 3,970 4,367 5,022 ps On 3,390 3,729 4,288 ps Small 2,810 3,091 3,554 ps 212 224 257 ps Medium Large 212 224 257 ps Decrease input delay to input register Off 3900 4,290 4,933 ps On 0 0 0 ps Decrease input delay to output register Off 1,240 1,364 1,568 ps On 0 0 0 ps Increase delay to output pin Off 0 0 0 ps On 377 397 456 ps Increase delay to output enable pin Off 0 0 0 ps On 338 372 427 ps Increase output clock enable delay Off 0 0 0 ps On 540 594 683 ps Small 1,016 1,118 1,285 ps Large 1,016 1,118 1,285 ps 0 0 0 ps Increase input clock enable Off delay On Increase output enable clock enable delay Altera Corporation June 2006 540 594 683 ps Small 1,016 1,118 1,285 ps Large 1,016 1,118 1,285 ps 0 0 0 ps Off On 540 594 683 ps Small 1,016 1,118 1,285 ps Large 1,016 1,118 1,285 ps 6-51 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-79. Stratix GX IOE Programmable Delays on Row Pins -5 Speed Grade Parameter -7 Speed Grade Unit Min Decrease input delay to internal cells -6 Speed Grade Setting Max Min Max Min Max Off 3,970 4,367 5,022 ps On 3,390 3,729 4,288 ps Small 2,810 3,091 3,554 ps 164 173 198 ps Medium Large 164 173 198 ps 3,900 4,290 4,933 ps Decrease input delay to input register Off On 0 0 0 ps Decrease input delay to output register Off 1,240 1,364 1,568 ps On 0 0 0 ps Increase delay to output pin Off 0 0 0 ps On 377 397 456 ps Increase delay to output enable pin Off 0 0 0 ps On 348 383 441 ps Increase output clock enable delay Off 0 0 0 ps On 180 198 227 ps Small 260 286 328 ps Large 260 286 328 ps 0 0 0 ps Increase input clock enable Off delay On Increase output enable clock enable delay 180 198 227 ps Small 260 286 328 ps Large 260 286 328 ps 0 0 0 ps Off On 540 594 683 ps Small 1,016 1,118 1,285 ps Large 1,016 1,118 1,285 ps 6-52 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics The scaling factors for output pin timing in Table 6-80 are shown in units of time per pF unit of capacitance (ps/pF). Add this delay to the combinational timing path for output or bidirectional pins in addition to the "I/O Adder" delays shown in Tables 6-72 through 6-77 and the "IOE Programmable Delays" in Tables 6-78 and 6-79. Table 6-80. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers LVTTL/LVCMOS Standards Conditions Parameter Drive Strength Output Pin Adder Delay (ps/pF) Value 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL LVCMOS 24 mA 15 - - - 8 16 mA 25 18 - - - 12 mA 30 25 25 - 15 8 mA 50 35 40 35 20 4 mA 60 - - 80 30 2 mA - 75 120 160 60 SSTL/HSTL Standards Output Pin Adder Delay (ps/pF) Conditions Class I Class II SSTL-3 SSTL-2 SSTL-1.8 1.5-V HSTL 1.8-V HSTL 25 25 25 25 25 25 20 25 20 20 GTL+/GTL/CTT/PCI Standards Conditions Output Pin Adder Delay (ps/pF) Parameter Value GTL+ GTL CTT PCI AGP VC C I O voltage level 3.3 V 18 18 25 20 20 2.5 V 15 18 - - - Altera Corporation June 2006 6-53 Stratix GX Device Handbook, Volume 1 Timing Model Maximum Input & Output Clock Rates Tables 6-81 through 6-83 show the maximum input clock rate for column and row pins in Stratix GX devices. Table 6-81. Stratix GX Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit LVTTL 422 422 390 MHz 2.5 V 422 422 390 MHz 1.8 V 422 422 390 MHz 1.5 V 422 422 390 MHz LVCMOS 422 422 390 MHz GTL 300 250 200 MHz GTL+ 300 250 200 MHz SSTL-3 class I 400 350 300 MHz SSTL-3 class II 400 350 300 MHz SSTL-2 class I 400 350 300 MHz SSTL-2 class II 400 350 300 MHz SSTL-18 class I 400 350 300 MHz SSTL-18 class II 400 350 300 MHz 1.5-V HSTL class I 400 350 300 MHz 1.5-V HSTL class II 400 350 300 MHz 1.8-V HSTL class I 400 350 300 MHz 1.8-V HSTL class II 400 350 300 MHz 3.3-V PCI 422 422 390 MHz 3.3-V PCI-X 1.0 422 422 390 MHz Compact PCI 422 422 390 MHz AGP 1x 422 422 390 MHz AGP 2x 422 422 390 MHz CTT 300 250 200 MHz Differential HSTL 400 350 300 MHz LVDS 645 645 622 MHz LVPECL 645 645 622 MHz PCML 300 275 275 MHz HyperTransport technology 500 500 450 MHz 6-54 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-82. Stratix GX Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[8..7]CLK Pins I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit LVTTL 422 422 390 MHz 2.5 V 422 422 390 MHz 1.8 V 422 422 390 MHz 1.5 V 422 422 390 MHz LVCMOS 422 422 390 MHz GTL 300 250 200 MHz GTL+ 300 250 200 MHz SSTL-3 class I 400 350 300 MHz SSTL-3 class II 400 350 300 MHz SSTL-2 class I 400 350 300 MHz SSTL-2 class II 400 350 300 MHz SSTL-18 class I 400 350 300 MHz SSTL-18 class II 400 350 300 MHz 1.5-V HSTL class I 400 350 300 MHz 1.5-V HSTL class II 400 350 300 MHz 1.8-V HSTL class I 400 350 300 MHz 1.8-V HSTL class II 400 350 300 MHz 3.3-V PCI 422 422 390 MHz 3.3-V PCI-X 1.0 422 422 390 MHz Compact PCI 422 422 390 MHz AGP 1x 422 422 390 MHz AGP 2x 422 422 390 MHz CTT 300 250 200 MHz Differential HSTL 400 350 300 MHz LVDS 717 717 640 MHz LVPECL 717 717 640 MHz PCML 400 375 350 MHz HyperTransport technology 717 717 640 MHz Table 6-83. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 1 of 2) I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit LVTTL 422 422 390 MHz 2.5 V 422 422 390 MHz Altera Corporation June 2006 6-55 Stratix GX Device Handbook, Volume 1 Timing Model Table 6-83. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 2 of 2) I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade 1.8 V 422 422 Unit 390 MHz 1.5 V 422 422 390 MHz LVCMOS 422 422 390 MHz GTL 300 250 200 MHz GTL+ 300 250 200 MHz SSTL-3 class I 400 350 300 MHz SSTL-3 class II 400 350 300 MHz SSTL-2 class I 400 350 300 MHz SSTL-2 class II 400 350 300 MHz SSTL-18 class I 400 350 300 MHz SSTL-18 class II 400 350 300 MHz 1.5-V HSTL class I 400 350 300 MHz 1.5-V HSTL class II 400 350 300 MHz 1.8-V HSTL class I 400 350 300 MHz 1.8-V HSTL class II 400 350 300 MHz 3.3-V PCI 422 422 390 MHz 3.3-V PCI-X 1.0 422 422 390 MHz Compact PCI 422 422 390 MHz AGP 1x 422 422 390 MHz AGP 2x 422 422 390 MHz CTT 300 250 200 MHz Differential HSTL 400 350 300 MHz LVDS 645 645 640 MHz LVPECL 645 645 640 MHz PCML 300 275 275 MHz HyperTransport technology 645 645 640 MHz Tables 6-84 and 6-85 show the maximum output clock rate for column and row pins in Stratix GX devices. Table 6-84. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 1 of 2) I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit LVTTL 350 300 250 MHz 2.5 V 350 300 300 MHz 6-56 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-84. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 2 of 2) I/O Standard 1.8 V -5 Speed Grade -6 Speed Grade -7 Speed Grade 250 250 Unit 250 MHz 1.5 V 225 200 200 MHz LVCMOS 350 300 250 MHz GTL 200 167 125 MHz GTL+ 200 167 125 MHz SSTL-3 class I 167 150 133 MHz SSTL-3 class II 167 150 133 MHz SSTL-2 class I 200 200 167 MHz SSTL-2 class II 200 200 167 MHz SSTL-18 class I 150 133 133 MHz SSTL-18 class II 150 133 133 MHz 1.5-V HSTL class I 250 225 200 MHz 1.5-V HSTL class II 225 200 200 MHz 1.8-V HSTL class I 250 225 200 MHz 1.8-V HSTL class II 225 200 200 MHz 3.3-V PCI 350 300 250 MHz 3.3-V PCI-X 1.0 350 300 250 MHz Compact PCI 350 300 250 MHz AGP 1x 350 300 250 MHz AGP 2x 350 300 250 MHz CTT 200 200 200 MHz Differential HSTL 225 200 200 MHz Differential SSTL-2 200 200 167 MHz LVDS 500 500 500 MHz LVPECL 500 500 500 MHz PCML 350 350 350 MHz HyperTransport technology 350 350 350 MHz Table 6-85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 1 of 2) I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit LVTTL 400 350 300 MHz 2.5 V 400 350 300 MHz 1.8 V 400 350 300 MHz Altera Corporation June 2006 6-57 Stratix GX Device Handbook, Volume 1 High-Speed I/O Specification Table 6-85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 2 of 2) I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit 1.5 V 350 300 300 MHz LVCMOS 400 350 300 MHz GTL 200 167 125 MHz GTL+ 200 167 125 MHz SSTL-3 class I 167 150 133 MHz SSTL-3 class II 167 150 133 MHz SSTL-2 class I 150 133 133 MHz SSTL-2 class II 150 133 133 MHz SSTL-18 class I 150 133 133 MHz SSTL-18 class II 150 133 133 MHz HSTL class I 250 225 200 MHz HSTL class II 225 225 200 MHz 3.3-V PCI 250 225 200 MHz 3.3-V PCI-X 1.0 225 225 200 MHz Compact PCI 400 350 300 MHz AGP 1x 400 350 300 MHz AGP 2x 400 350 300 MHz CTT 300 250 200 MHz Differential HSTL 225 225 200 MHz LVDS 717 717 500 MHz LVPECL 717 717 500 MHz PCML 420 420 420 MHz HyperTransport technology 420 420 420 MHz High-Speed I/O Specification Table 6-86 provides high-speed timing specifications definitions. Table 6-86. High-Speed Timing Specifications & Definitions (Part 1 of 2) High-Speed Timing Specification Definitions tC High-speed receiver/transmitter input and output clock period. fHSCLK High-speed receiver/transmitter input and output clock frequency. tRISE Low-to-high transmission time. 6-58 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-86. High-Speed Timing Specifications & Definitions (Part 2 of 2) High-Speed Timing Specification Definitions tFALL High-to-low transmission time. Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC/w). fHSDR Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. Sampling window (SW) The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) - tSW (min). Input jitter (peak-to-peak) Peak-to-peak input jitter on high-speed PLLs. Output jitter (peak-to-peak) Peak-to-peak output jitter on high-speed PLLs. tDUTY Duty cycle on high-speed transmitter output clock. tLOCK Lock time for high-speed transmitter and receiver PLLs. Table 6-87 shows the high-speed I/O timing specifications for Stratix GX devices. Table 6-87. High-Speed I/O Specifications (Part 1 of 4) Symbol fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology) fHSCLK = fHSDR / W Notes (1), (2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Max Min Max Min 10 717 10 717 10 624 MHz 74 717 74 717 74 717 MHz Conditions W = 1 to 30 for 717 Mbps W = 2 to 30 for > 717 Mbps fHSCLK_DPA Altera Corporation June 2006 Unit Typ Typ Typ Max 6-59 Stratix GX Device Handbook, Volume 1 High-Speed I/O Specification Table 6-87. High-Speed I/O Specifications (Part 2 of 4) Symbol fHSDR Device operation (LVDS, LVPECL, HyperTransport technology) Notes (1), (2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Conditions Unit Typ Max Typ Max Typ Max J = 10 300 840 300 840 300 840 Mbps J=8 300 840 300 840 300 840 Mbps J=7 300 840 300 840 300 840 Mbps J=4 300 840 300 840 300 840 Mbps J=2 100 624 100 624 100 462 Mbps J = 1 (LVDS and LVPECL only) 100 462 100 462 100 462 Mbps 300 1000 300 840 300 840 Mbps 840 Mbps fHSDRDPA (LVDS, J=10 LVPECL) J=8 300 1000 300 840 300 fHSCLK (Clock frequency) (PCML) fHSCLK = fHSDR / W W = 1 to 30 10 400 10 400 10 fHSDR Device operation (PCML) J = 10 300 400 300 400 300 311 Mbps J=8 300 400 300 400 300 311 Mbps J=7 300 400 300 400 300 311 Mbps J=4 300 400 300 400 300 311 Mbps J=2 100 400 100 400 100 300 Mbps J=1 100 250 100 250 100 DPA Run Length DPA Jitter Tolerance(p-p) all data rates DPA Minimum Eye opening (p-p) 0.56 DPA Receiver Latency 5 6-60 Stratix GX Device Handbook, Volume 1 311 MHz 200 Mbps 6400 6400 6400 UI 0.44 0.44 0.44 UI 0.56 9 5 0.56 9 5 UI 9 (3) Altera Corporation June 2006 DC & Switching Characteristics Table 6-87. High-Speed I/O Specifications (Part 3 of 4) Symbol DPA Lock Time Notes (1), (2) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min Conditions Standard Train ing Patt ern Unit Typ Max Typ Max Typ Max Trans ition Density 0000 10% 0000 0011 1111 1111 256 256 256 (4) Rapid IO 0000 25% 1111 256 256 256 (4) 1001 50% 0000 256 256 256 (4) 1010 100 1010 % 256 256 256 (4) 0101 0101 256 256 256 (4) SPI-4, CSIX Misc TCCS All 200 200 300 ps SW PCML (J = 4, 7, 8, 10) 750 750 800 ps PCML (J = 2) 900 900 1,200 ps PCML (J = 1) 1,500 1,500 1,700 ps LVDS and LVPECL (J = 1) 500 500 550 ps LVDS, LVPECL, HyperTransport technology (J = 2 through 10) 440 440 500 ps Input jitter tolerance (peak-to-peak) All 250 250 250 ps Output jitter (peak-to-peak) All 160 160 200 ps Output tRISE LVDS 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 120 170 200 ps LVPECL 90 130 150 90 130 150 100 135 150 ps PCML 80 110 135 80 110 135 80 110 135 ps Altera Corporation June 2006 6-61 Stratix GX Device Handbook, Volume 1 High-Speed I/O Specification Table 6-87. High-Speed I/O Specifications (Part 4 of 4) Symbol Output tFALL tDUTY -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Typ Max Min Typ Max Conditions Unit Typ Max LVDS 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 110 170 200 ps LVPECL 90 130 160 90 130 160 100 135 160 ps PCML 105 140 175 105 140 175 110 145 175 ps LVDS (J = 2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % 45 50 55 45 50 55 45 50 55 % 100 s LVDS (J =1) and LVPECL, PCML, HyperTransport technology tLOCK Notes (1), (2) All 100 100 Notes to Table 6-87: (1) (2) (3) (4) When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed. Number of parallel CLK cycles. Number of repetitions. PLL Timing Tables 6-88 through 6-90 describe the Stratix GX device enhanced PLL specifications. Table 6-88. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2) Max Unit fIN Symbol Input clock frequency Parameter 3 (1) 684 MHz fINDUTY Input clock duty cycle 40 60 % fEINDUTY External feedback clock input duty cycle 40 60 % tINJITTER Input clock period jitter 200 (2) ps tEINJITTER External feedback clock period jitter 200 (2) ps tFCOMP External feedback clock compensation time (3) 6 ns fOUT Output frequency for internal global or regional clock 0.3 500 MHz fOUT_EXT Output frequency for external clock (2) 0.3 526 MHz 6-62 Stratix GX Device Handbook, Volume 1 Min Typ Altera Corporation June 2006 DC & Switching Characteristics Table 6-88. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2) Symbol Parameter Min Typ Max Unit 55 % 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk ps or mUI tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 tJITTER Period jitter for external clock output (5) tCONFIG5,6 Time required to reconfigure the scan chains for PLLs 5 and 6 289/fSCANCLK tCONFIG11,12 Time required to reconfigure the scan chains for PLLs 11 and 12 193/fSCANCLK tSCANCLK scanclk frequency (4) 22 MHz tDLOCK Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) 100 s tLOCK Time required to lock from end of device configuration 10 400 s 300 800 (7) MHz fVCO PLL internal VCO operating range tLSKEW Clock skew between two external clock outputs driven by the same counter 50 ps tSKEW Clock skew between two external clock outputs driven by the different counters with the same settings 75 ps fSS Spread spectrum modulation frequency 30 % spread Percentage spread for spread spectrum frequency (9) 0.4 tARESET Minimum pulse width on areset signal 10 0.5 Table 6-89. Enhanced PLL Specifications for -6 Speed Grades Symbol Parameter 150 kHz 0.6 % ns (Part 1 of 2) Min Typ Max Unit fIN Input clock frequency 3 (1) 650 MHz fINDUTY Input clock duty cycle 40 60 % fEINDUTY External feedback clock input duty cycle 40 60 % tINJITTER Input clock period jitter 200 (2) ps tEINJITTER External feedback clock period jitter 200 (2) ps tFCOMP External feedback clock compensation time (3) 6 ns Altera Corporation June 2006 6-63 Stratix GX Device Handbook, Volume 1 High-Speed I/O Specification Table 6-89. Enhanced PLL Specifications for -6 Speed Grades Symbol Parameter (Part 2 of 2) Min Typ Max Unit fOUT Output frequency for internal global or regional clock 0.3 450 MHz fOUT_EXT Output frequency for external clock (2) 0.3 500 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 55 % tJITTER Period jitter for external clock output (5) 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk ps or mUI tCONFIG5,6 Time required to reconfigure the scan chains for PLLs 5 and 6 289/fSCANCLK tCONFIG11,12 Time required to reconfigure the scan chains for PLLs 11 and 12 193/fSCANCLK tSCANCLK scanclk frequency (4) tDLOCK Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) (10) tLOCK 22 MHz (8) 100 s Time required to lock from end of device configuration (10) 10 400 s fVCO PLL internal VCO operating range 300 800 (7) MHz tLSKEW Clock skew between two external clock outputs driven by the same counter 50 ps tSKEW Clock skew between two external clock outputs driven by the different counters with the same settings 75 ps fSS Spread spectrum modulation frequency 30 % spread Percentage spread for spread spectrum frequency (9) 0.4 tARESET Minimum pulse width on areset signal 10 0.5 150 kHz 0.6 % ns Table 6-90. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 3) Symbol Parameter Min Typ Max Unit fIN Input clock frequency 3 (1) 565 MHz fINDUTY Input clock duty cycle 40 60 % fEINDUTY External feedback clock input duty cycle 40 60 % tINJITTER Input clock period jitter 200 (2) ps tEINJITTER External feedback clock period jitter 200 (2) ps 6-64 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3) Symbol Parameter Min Typ Max Unit 6 ns tFCOMP External feedback clock compensation time (3) fOUT Output frequency for internal global or regional clock 0.3 420 MHz fOUT_EXT Output frequency for external clock (2) 0.3 434 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 55 % tJITTER Period jitter for external clock output (5) 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk ps or mUI tCONFIG5,6 Time required to reconfigure the scan chains for PLLs 5 and 6 289/fSCANCLK tCONFIG11,12 Time required to reconfigure the scan chains for PLLs 11 and 12 193/fSCANCLK tSCANCLK scanclk frequency (4) tDLOCK Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) (10) tLOCK fVCO 22 MHz (8) 100 s Time required to lock from end of device configuration (10) 10 400 s PLL internal VCO operating range 300 600 (7) MHz Altera Corporation June 2006 6-65 Stratix GX Device Handbook, Volume 1 High-Speed I/O Specification Table 6-90. Enhanced PLL Specifications for -7 Speed Grade (Part 3 of 3) Symbol Parameter Min Typ Max Unit tLSKEW Clock skew between two external clock outputs driven by the same counter 50 ps tSKEW Clock skew between two external clock outputs driven by the different counters with the same settings 75 ps fSS Spread spectrum modulation frequency 30 150 kHz % spread Percentage spread for spread spectrum frequency (9) 0.5 0.6 % tARESET Minimum pulse width on areset signal 10 ns Notes to Tables 6-88 through 6-90: (1) (2) (3) (4) The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs. See "Maximum Input & Output Clock Rates" on page 6-54. tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less). This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be driven by the logic array. (5) Actual jitter performance may vary based on the system configuration. (6) Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are changed, then tDLOCK is equal to 0. (7) The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected. (8) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or feedback counter change increment. (9) Exact, user-controllable value depends on the PLL settings. (10) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200 MHz. See the Stratix FPGA Errata Sheet for more information on the PLL. 6-66 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 DC & Switching Characteristics Table 6-91 describes the Stratix GX device fast PLL specifications. Table 6-91. Fast PLL Specifications for -5 & -6 Speed Grade Devices Symbol Parameter Min Max Unit CLKIN frequency (for m = 1) (1) 300 717 MHz CLKIN frequency (for m = 2 to 19) 300/ m 1,000/m MHz CLKIN frequency (for m = 20 to 32) 10 1,000/m MHz fOUT Output frequency for internal global or regional clock (2) 9.4 420 MHz fOUT_EXT Output frequency for external clock 9.375 717 MHz fVCO VCO operating frequency 300 1,000 MHz tINDUTY CLKIN duty cycle 40 60 % 200 ps 55 % 80 ps 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk ps or mUI fIN tINJITTER Period jitter for CLKIN pin tDUTY Duty cycle for DFFIO 1x CLKOUT pin (3) tJITTER Period jitter for DIFFIO clock out (3) 45 Period jitter for internal global or regional clock tLOCK Time required for PLL to acquire lock 10 100 s m Multiplication factors for m counter (3) 1 32 Integer l0, l1, g0 Multiplication factors for l0, l1, and g0 counter (4), (5) 1 32 Integer tARESET Minimum pulse width on areset signal 10 ns Table 6-92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 1 of 2) Symbol fIN Min Max Unit CLKIN frequency (for m = 1) (1), Parameter 300 640 MHz CLKIN frequency (for m = 2 to 19) 300/ m 700/m MHz CLKIN frequency (for m = 20 to 32) 10 700/m MHz 9.375 420 MHz Output frequency for external clock 9.4 500 MHz fVCO VCO operating frequency 300 700 MHz tINDUTY CLKIN duty cycle 40 60 % tINJITTER Period jitter for CLKIN pin 200 ps fOUT Output frequency for internal global or regional clock (2) fOUT_EXT Altera Corporation June 2006 6-67 Stratix GX Device Handbook, Volume 1 DLL Jitter Table 6-92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 2 of 2) Symbol Parameter Min Max Unit tDUTY Duty cycle for DFFIO 1x CLKOUT pin (3) 45 55 % tJITTER Period jitter for DIFFIO clock out (3) 80 ps 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk ps or mUI Period jitter for internal global or regional clock tLOCK Time required for PLL to acquire lock 10 100 s m Multiplication factors for m counter (4) 1 32 Integer l0, l1, g0 Multiplication factors for l0, l1, and g0 counter (4), (5) 1 32 Integer tARESET Minimum pulse width on areset signal 10 ns Notes to Tables 6-91 & 6-92: (1) (2) (3) (4) (5) See "Maximum Input & Output Clock Rates" on page 6-54. When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor of 4). This parameter is for high-speed differential I/O mode only. These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum of 16. High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10. DLL Jitter Table 6-93 reports the jitter for the DLL in the DQS phase-shift reference circuit. Table 6-93. DLL Jitter for DQS Phase Shift Reference Circuit Frequency (MHz) DLL Jitter (ps) 197 to 200 100 160 to 196 300 100 to 159 500 6-68 Stratix GX Device Handbook, Volume 1 Altera Corporation June 2006 7. Reference & Ordering Information SGX51007-1.0 Software Stratix(R) GX devices are supported by the Altera(R) Quartus(R) II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes hardware description language and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap(R) logic analysis, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows 2000/NT/98, Sun Solaris, Linux Red Hat v6.2 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface. Device Pin-Outs Device pin-outs for Stratix GX devices will be released on the Altera web site (www.altera.com). Ordering Information Figure 7-1 describes the ordering codes for Stratix GX devices. Figure 7-1. Stratix GX Device Packaging Ordering Information EP1SGX 40 G F 1020 C 7 N Family Signature Optional Suffix Indicates specific device options or shipment method. N: Lead free ES: Engineering sample EP1SGX: Stratix GX Device Type 10 25 40 Speed Grade 5, 6, or 7, with 5 being the fastest Number of Transceiver Channels C: D: F: G: Operating Temperature 4 8 16 20 Package Type F: FineLine BGA Altera Corporation February 2005 C: Commercial temperature (tj = 0 C to 85 C ) I: Industrial temperature (tj = -40 C to 100 C ) Pin Count Number of pins for a particular FineLine BGA package 7-1 Ordering Information 7-2 Stratix GX Device Handbook, Volume 1 Altera Corporation February 2005