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FEATURES
DESCRIPTION
APPLICATIONS
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
3.8V
1.8V
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
COUT
CIN
CSS
VBIAS
CBIAS
VOUT
TPS74801
SBVS074 – JANUARY 2007
1.5A LDO Linear Regulator with Programmable Soft-Start
•Ultra-Low V
IN
and V
OUT
Range: 0.8V to 5.5V
The TPS74801 low-dropout (LDO) linear regulator•V
BIAS
Range 2.7V to 5.5V
provides an easy-to-use robust power management•Low Dropout: 60mV typ at 1.5A, V
BIAS
= 5V
solution for a wide variety of applications.•Power Good (PG) Output Allows Supply
User-programmable soft-start minimizes stress onMonitoring or Provides a Sequencing Signal
the input power source by reducing capacitive inrushcurrent on start-up. The soft-start is monotonic andfor Other Supplies
well-suited for powering many different types of•2% Accuracy Over Line/Load/Temperature
processors and ASICs. The enable input and•Programmable Soft-Start Provides Linear
power-good output allow easy sequencing withVoltage Startup
external regulators. This complete flexibility permitsthe user to configure a solution that meets the•V
BIAS
Permits Low V
IN
Operation with Good
sequencing requirements of FPGAs, DSPs, andTransient Response
other applications with special start-up requirements.•Stable with Any Output Capacitor ≥2.2 µF
A precision reference and error amplifier deliver 2%•Available in a Small 3mm x 3mm x 1mm
accuracy over load, line, temperature, and process.SON-10 Package
The device is stable with any output capacitor type,and is fully specified from –40 °C to +125 °C. TheTPS74801 is offered in a small 3mm ×3mm SON-10•FPGA Applications
package, yielding a highly compact, total solution•DSP Core and I/O Voltages
size.•Post-Regulation Applications•Applications With Special Start-Up Time orSequencing Requirements•Hot-Swap and Inrush Controls
Figure 2. Turn-On Response
Figure 1. Typical Application Circuit (Adjustable)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS74801
SBVS074 – JANUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS748 xxyyyz XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).
(3)
YYY is package designator.Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Fixed output voltages from 0.8V to 3.3V are available; minimum order quantities may apply. Contact factory for details and availability.(3) For fixed 0.8V operation, tie FB to OUT.
At T
J
= –40 °C to +125 °C, unless otherwise noted. All voltages are with respect to GND.
TPS74801 UNIT
V
IN
, V
BIAS
Input voltage range –0.3 to +6 VV
EN
Enable voltage range –0.3 to +6 VV
PG
Power-good voltage range –0.3 to +6 VV
SS
Soft-start voltage range –0.3 to +6 VV
FB
Feedback voltage range –0.3 to +6 VV
OUT
Output voltage range –0.3 to V
IN
+ 0.3 VI
OUT
Maximum output current Internally limitedOutput short-circuit duration IndefiniteP
DISS
Continuous total power dissipation See Dissipation Ratings TableT
J
Operating junction temperature range –40 to +125 °CT
STG
Storage junction temperature range –55 to +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.
T
A
< +25 °C DERATING FACTORPACKAGE θ
JA
θ
JC
POWER RATING ABOVE T
A
= +25 °C
DRC (SON) High-K
(1) (2)
52 48 1.92 W 19 mW/ °C
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch multilayer board with 1-ounce internal power andground planes and 2-ounce copper traces on the top and bottom of the board(2) See the Layout Recommendations and Power Dissipation section for additional thermal information.
2
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ELECTRICAL CHARACTERISTICS
TPS74801
SBVS074 – JANUARY 2007
At V
EN
= 1.1V, V
IN
= V
OUT
+ 0.3V, C
BIAS
= 0.1 µF, C
IN
= C
OUT
= 10 µF, CNR = , I
OUT
= 50mA, V
BIAS
= 5.0V, and T
J
= –40 °C to+125 °C, unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS74801
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range V
OUT
+ V
DO
5.5 VV
BIAS
Bias pin voltage range 2.7 5.5 VV
REF
Internal reference (Adj.) T
J
= +25 °C 0.796 0.8 0.804 VOutput voltage range V
IN
= 5V, I
OUT
= 1.5A V
REF
3.6 VV
OUT
2.97V ≤V
BIAS
≤5.5V,Accuracy
(1)
–2 ±0.5 2 %50mA ≤I
OUT
≤1.5AV
OUT
/V
IN
Line regulation V
OUT (NOM)
+ 0.3 ≤V
IN
≤5.5V 0.03 %/VV
OUT
/I
OUT
Load regulation 50mA ≤I
OUT
≤1.5A 0.09 %/AI
OUT
= 1.5A, V
BIAS
– V
OUT (NOM)
≥3.25V 60 165 mVV
DO
V
IN
dropout voltage
(2)
I
OUT
= 1.5A, V
IN
= V
BIAS
1.31 1.6 VI
CL
Current limit V
OUT
= 80% ×V
OUT (NOM)
2.0 5.5 AI
BIAS
Bias pin current 1 2 mAShutdown supply currentI
SHDN
V
EN
≤0.4V 1 50 µA(I
GND
)I
FB
Feedback pin current –1 150 1 µA1kHz, I
OUT
= 1.5A,
60V
IN
= 1.8V, V
OUT
= 1.5VPower-supply rejection
dB(V
IN
to V
OUT
)
300kHz, I
OUT
= 1.5A,
30V
IN
= 1.8V, V
OUT
= 1.5VPSRR
1kHz, I
OUT
= 1.5A,
50V
IN
= 1.8V, V
OUT
= 1.5VPower-supply rejection
dB(V
BIAS
to V
OUT
)
300kHz, I
OUT
= 1.5A,
30V
IN
= 1.8V, V
OUT
= 1.5V100Hz to 100kHz,Noise Output noise voltage 25 ×V
OUT
µV
RMSI
OUT
= 1.5A, C
SS
= 0.001 µFt
STR
Minimum startup time R
LOAD
for I
OUT
= 1.0A, C
SS
= open 200 µsI
SS
Soft-start charging current V
SS
= 0.4V 440 nAV
EN, HI
Enable input high level 1.1 5.5 VV
EN, LO
Enable input low level 0 0.4 VV
EN, HYS
Enable pin hysteresis 50 mVV
EN, DG
Enable pin deglitch time 20 µsI
EN
Enable pin current V
EN
= 5V 0.1 1 µAV
IT
PG trip threshold V
OUT
decreasing 85 90 94 %V
OUT
V
HYS
PG trip hysteresis 3 %V
OUT
V
PG, LO
PG output low voltage I
PG
= 1mA (sinking), V
OUT
< V
IT
0.3 VI
PG, LKG
PG leakage current V
PG
= 5.25V, V
OUT
> V
IT
0.1 1 µAOperating junctionT
J
–40 +125 °Ctemperature
Shutdown, temperature increasing +165Thermal shutdownT
SD
°Ctemperature
Reset, temperature decreasing +140
(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.(2) Dropout is defined as the voltage from V
IN
to V
OUT
when V
OUT
is 3% below nominal.
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BLOCK DIAGRAM
Thermal
Limit
Soft-Start
Discharge
OUT VOUT
FB
PG
IN
BIAS
SS
EN Hysteresis
andDeglitch
Current
Limit
UVLO
0.44 Am
0.8V
Reference
0.9V ´VREF
GND
CSS
R1
R2
TPS74801
SBVS074 – JANUARY 2007
Table 1. Standard 1% Resistor Values for Programming the Output Voltage
(1)
R
1
(k Ω) R
2
(k Ω) V
OUT
(V)
Short Open 0.80.619 4.99 0.91.13 4.53 1.01.37 4.42 1.051.87 4.99 1.12.49 4.99 1.24.12 4.75 1.53.57 2.87 1.83.57 1.69 2.53.57 1.15 3.3
(1) V
OUT
= 0.8 ×(1 + R
1
/R
2
)
Table 2. Standard Capacitor Values for Programming the Soft-Start Time
(1)
C
SS
SOFT-START TIME
Open 0.1ms270pF 0.5ms560pF 1ms2.7nF 5ms5.6nF 10ms0.01 µF 18ms
(1) t
SS
(s) = 0.8 ×C
SS
(F)/4.4 ×10
–7
4
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DEVICE INFORMATION
OUT
OUT
FB
SS
GND
10
9
8
7
6
IN
IN
PG
BIAS
EN
1
2
3
4
5
Thermal
Pad
PIN DESCRIPTIONS
TPS74801
SBVS074 – JANUARY 2007
DRC PACKAGE
3mm x 3mm QFN(TOP VIEW)
NAME DRC (SON) DESCRIPTION
IN 1, 2 Input to the device.Enable pin. Driving this pin high enables the regulator. Driving this pin low puts theEN 5
regulator into shutdown mode. This pin must not be left unconnected.SS 7 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pinis left unconnected, the regulator output soft-start ramp time is typically 200 µs.BIAS 4 Bias input voltage for error amplifier, reference, and internal control circuits.Power-Good pin. An open-drain, active-high output that indicates the status of V
OUT
. WhenV
OUT
exceeds the PG trip threshold, the PG pin goes into a high-impedance state. WhenV
OUT
is below this threshold the pin is driven to a low-impedance state. A pull-up resistorPG 3
from 10k Ωto 1M Ωshould be connected from this pin to a supply of up to 5.5V. The supplycan be higher than the input voltage. Alternatively, the PG pin can be left unconnected ifoutput monitoring is not necessary.Feedback pin. The feedback connection to the center tap of an external resistor dividerFB 8
network that sets the output voltage. This pin must not be left floating.OUT 9, 10 Regulated output voltage. No capacitor is required on this pin for stability.GND 6 GroundThermal Pad — Should be soldered to the ground plane for increased thermal performance.
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TYPICAL CHARACTERISTICS
0.20
0.15
0.10
0.05
0
-0.05
-0.01
-0.15
-0.20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ChangeinV (%)
OUT
V V-
IN OUT (V)
5.0
+125 C°
+25 C°
- °40 C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ChangeinV (%)
OUT
V V-
BIAS OUT (V)
4.0
+125 C°+25 C°
- °40 C
1.2
1.0
0.8
0.6
0.4
0.2
0
010 20 30 40
ChangeinV (%)
OUT
I (mA)
OUT
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.05 0.5 1.0
ChangeinV (%)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°- °40 C
100
90
80
70
60
50
40
30
20
10
0
00.5 1.0
V (V V )(mV)-
DO IN OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
200
180
160
140
120
100
80
60
40
20
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDO IN
(V -VOUT)(mV)
VBIAS -VOUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =1.5A
OUT
TPS74801
SBVS074 – JANUARY 2007
At T
J
= +25 °C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
V
IN
LINE REGULATION V
BIAS
LINE REGULATION
Figure 3. Figure 4.
LOAD REGULATION LOAD REGULATION
Figure 5. Figure 6.
V
IN
DROPOUT VOLTAGE vs V
IN
DROPOUT VOLTAGE vsI
OUT
AND TEMPERATURE (T
J
) (V
BIAS
– V
OUT
) AND TEMPERATURE (T
J
)
Figure 7. Figure 8.
6
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200
180
160
140
120
100
80
60
40
20
0
01.51.00.5 2.0 2.5 3.0 3.5 4.0
V (mV)
DO IN OUT
(V V )
-
V V-
BIAS OUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =0.5A
OUT
2200
2000
1800
1600
1400
1200
1000
800
600
00.5 1.0
V (V -
DO BIAS V )(mV)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
C =1nF
SS
I =100mA
OUT
I =1.5A
OUT
1
0.1
0.01
100 1k 10k
OutputSpectralNoiseDensity(mV/Ö)
Hz
Frequency(Hz)
100k
C =1nF
SS
C =0nF
SS
C =10nF
SS
I =100mA
OUT
V =1.2V
OUT
TPS74801
SBVS074 – JANUARY 2007
TYPICAL CHARACTERISTICS (continued)At T
J
= +25 °C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
V
IN
DROPOUT VOLTAGE vs V
BIAS
DROPOUT VOLTAGE vs(V
BIAS
– V
OUT
) AND TEMPERATURE (T
J
) I
OUT
AND TEMPERATURE (T
J
)
Figure 9. Figure 10.
V
BIAS
PSRR vs FREQUENCY V
IN
PSRR vs FREQUENCY
Figure 11. Figure 12.
V
IN
PSRR vs (V
IN
– V
OUT
) NOISE SPECTRAL DENSITY
Figure 13. Figure 14.
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100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
100mV/div
100mV/div
1A/div
100mV/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
1A/ sm
50mA
C =470 F(OSCON)OUT m
C =1nF
SS
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
3.8V
1.8V
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
TPS74801
SBVS074 – JANUARY 2007
TYPICAL CHARACTERISTICS (continued)At T
J
= +25 °C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
V
BIAS
LINE TRANSIENT (1A) V
IN
LINE TRANSIENT
Figure 15. Figure 16.
OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE
Figure 17. Figure 18.
BIAS PIN CURRENT vsPOWER-UP/POWER-DOWN I
OUT
AND TEMPERATURE (T
J
)
Figure 19. Figure 20.
8
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500
475
450
425
400
375
350
325
300
-50 -25 0 25 50 75 100
I (nA)
SS
JunctionTemperature( C)°
125
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
02 4 6 8 10 12
PGCurrent(mA)
TPS74801
SBVS074 – JANUARY 2007
TYPICAL CHARACTERISTICS (continued)At T
J
= +25 °C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
BIAS PIN CURRENT vs SOFT-START CHARGING CURRENT (I
SS
) vsV
BIAS
AND TEMPERATURE (T
J
) TEMPERATURE (T
J
)
Figure 21. Figure 22.
LOW-LEVEL PG VOLTAGE vs CURRENT CURRENT LIMIT vs (V
BIAS
– V
OUT
)
Figure 23. Figure 24.
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APPLICATION INFORMATION
INPUT, OUTPUT, AND BIAS CAPACITOR
TRANSIENT RESPONSE
VOUT
COUT
10 Fm
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
CIN
1 Fm
CSS
VBIAS
CBIAS
1 Fm
V =0.8
OUT ´1+ ´1.193
R1
R2
)(
TPS74801
SBVS074 – JANUARY 2007
The TPS74801 belongs to a family of low dropout
REQUIREMENTSregulators that feature soft-start capability. Theseregulators use a low current bias input to power all The device is designed to be stable for all availableinternal control circuitry, allowing the NMOS pass types and values of output capacitors ≥2.2 µF. Thetransistor to regulate very low input and output device is also stable with multiple capacitors involtages. parallel, which can be of any type or value.
The use of an NMOS-pass FET offers several critical The capacitance required on the IN and BIAS pins isadvantages for many applications. Unlike a PMOS strongly dependent on the input supply sourcetopology device, the output capacitor has little effect impedance. To counteract any inductance in theon loop stability. This architecture allows the input, the minimum recommended capacitor for V
INTPS74801 to be stable with any capacitor type of and V
BIAS
is 1 µF. If V
IN
and V
BIAS
are connected tovalue 2.2 µF or greater. Transient response is also the same supply, the recommended minimumsuperior to PMOS topologies, particularly for low V
IN
capacitor for V
BIAS
is 4.7 µF. Good quality, low ESRapplications. capacitors should be used on the input; ceramic X5Rand X7R capacitors are preferred. These capacitorsThe TPS74801 features a programmable
should be placed as close the pins as possible forvoltage-controlled soft-start circuit that provides a
optimum performance.smooth, monotonic start-up and limits startup inrushcurrents that may be caused by large capacitiveloads. A power-good (PG) output is available to allowsupply monitoring and sequencing of other supplies.
The TPS74801 was designed to have excellentAn enable (EN) pin with hysteresis and deglitch
transient response within most applications with aallows slow-ramping signals to be used for
small amount of output capacitance. In some cases,sequencing the device. The low V
IN
and V
OUT
the transient response may be limited by thecapability allows for inexpensive, easy-to-design, and
transient response of the input supply. This limitationefficient linear regulation between the multiple supply
is especially true in applications where the differencevoltages often present in processor intensive
between the input and output is less than 300mV. Insystems.
this case, adding additional input capacitanceimproves the transient response much more than justFigure 25 illustrates the typical application circuit for
adding additional output capacitance would do. Withthe TPS74801 adjustable input device.
a solid input supply, adding additional outputcapacitance reduces undershoot and overshootduring a transient event; refer to Figure 17 in theTypical Characteristics section. Because theTPS74801 is stable with output capacitors as low as2.2 µF, many applications may then need very littlecapacitance at the LDO output. For theseapplications, local bypass capacitance for thepowered device may be sufficient to meet thetransient requirements of the application. This designreduces the total solution cost by avoiding the needto use expensive, high-value capacitors at the LDOoutput.Figure 25. Typical Application Circuit for theTPS74801 (Adjustable)
R
1
and R
2
can be calculated for any output voltageusing the formula shown in Figure 25 . Refer toTable 1 for sample resistor values of common outputvoltages. In order to achieve the maximum accuracyspecifications, R
2
should be ≤4.99k Ω.
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DROPOUT VOLTAGE
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN
VIN
V =3.3V 5%
BIAS ±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
COUT
PROGRAMMABLE SOFT-START
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN V =5V 5%
BIAS ±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
COUT
t =
SS
(V C )´
REF SS
ISS
(1)
t =
SSCL
(V C )´
OUT(NOM) OUT
ICL(MIN)
(2)
TPS74801
SBVS074 – JANUARY 2007
The TPS74801 offers very low dropout performance,making it well-suited for high-current, low V
IN
/lowV
OUT
applications. The low dropout of the TPS74801allows the device to be used in place of a DC/DCconverter and still achieve good efficiency. Thisprovides designers with the power architecture fortheir application to achieve the smallest, simplest,and lowest cost solution.
There are two different specifications for dropoutvoltage with the TPS74801. The first specification(shown in Figure 26 ) is referred to as V
IN
Dropoutand is used when an external bias voltage is appliedto achieve low dropout. This specification assumesthat V
BIAS
is at least 1.56V above V
OUT
, which is the
Figure 27. Typical Application of the TPS74801case for V
BIAS
when powered by a 3.3V rail with 5%
Without an Auxiliary Bias Railtolerance and with V
OUT
= 1.5V. If V
BIAS
is less thanV
OUT
+1.56V, V
IN
dropout is less than specified.
The TPS74801 features a programmable, monotonic,voltage-controlled soft-start that is set with anexternal capacitor (C
SS
). This feature is important formany applications because it eliminates power-upinitialization problems when powering FPGAs, DSPs,or other processors. The controlled voltage ramp ofthe output also reduces peak inrush current duringstart-up, minimizing start-up transient events to theinput power bus.
To achieve a linear and monotonic soft-start, theTPS74801 error amplifier tracks the voltage ramp ofthe external soft-start capacitor until the voltageexceeds the internal reference. The soft-start rampFigure 26. Typical Application of the TPS74801
time is dependant on the soft-start charging currentUsing an Auxiliary Bias Rail
(I
SS
), soft-start capacitance (C
SS
), and the internalreference voltage (V
REF
), and can be calculatedThe second specification (shown in Figure 27 ) is
using Equation 1 :referred to as V
BIAS
Dropout and applies toapplications where IN and BIAS are tied together.This option allows the device to be used inapplications where an auxiliary bias voltage is not
If large output capacitors are used, the deviceavailable or low dropout is not required. Dropout is
current limit (I
CL
) and the output capacitor may setlimited by BIAS in these applications because V
BIAS
the start-up time. In this case, the start-up time isprovides the gate drive to the pass FET; therefore,
given by Equation 2 :V
BIAS
must be 1.56V above V
OUT
.
where:
V
OUT(NOM)
is the nominal output voltage,C
OUT
is the output capacitance, andI
CL(MIN)
is the minimum current limit for thedevice.
In applications where monotonic startup is required,the soft-start time given by Equation 1 should be setgreater than Equation 2 .
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V ( V )=25m
N RMS xV (V)
OUT
mVRMS
V
( )
(3)
SEQUENCING REQUIREMENTS
ENABLE/SHUTDOWN
POWER-GOOD
TPS74801
GND SS
OUT
FB
EN
IN
BIAS
VIN VOUT
R2
R1
CSS
CIN
C
VBIAS
CBIAS
R
COUT
OUTPUT NOISE
TPS74801
SBVS074 – JANUARY 2007
The maximum recommended soft-start capacitor is reduced by half and is typically 30 µV
RMS
for a 1.2V0.015 µF. Larger soft-start capacitors can be used output (10Hz to 100kHz). Further increasing C
SS
hasand will not damage the device; however, the little effect on noise. Because most of the outputsoft-start capacitor discharge circuit may not be able noise is generated by the internal reference, theto fully discharge the soft-start capacitor when noise is a function of the set output voltage. Theenabled. Soft-start capacitors larger than 0.015 µF RMS noise with a 0.001 µF soft-start capacitor iscould be a problem in applications where it is given in Equation 3 :necessary to rapidly pulse the enable pin and stillrequire the device to soft-start from ground. C
SS
mustbe low-leakage; X7R, X5R, or C0G dielectricmaterials are preferred. Refer to Table 2 for
The low output noise of the TPS74801 makes it asuggested soft-start capacitor values.
good choice for powering transceivers, PLLs, orother noise-sensitive circuitry.
V
IN
, V
BIAS
, and V
EN
can be sequenced in any orderwithout causing damage to the device. However, for
The enable (EN) pin is active high and is compatiblethe soft-start function to work as intended, certain
with standard digital signaling levels. V
EN
below 0.4Vsequencing rules must be applied. Connecting EN to
turns the regulator off, while V
EN
above 1.1V turnsIN is acceptable for most applications, as long as V
IN
the regulator on. Unlike many regulators, the enableis greater than 1.1V and the ramp rate of V
IN
and
circuitry has hysteresis and deglitching for use withV
BIAS
is faster than the set soft-start ramp rate. If the
relatively slowly ramping analog signals. Thisramp rate of the input sources is slower than the set
configuration allows the TPS74801 to be enabled bysoft-start time, the output tracks the slower supply
connecting the output of another supply to the ENminus the dropout voltage until it reaches the set
pin. The enable circuitry typically has 50mV ofoutput voltage. If EN is connected to BIAS, the
hysteresis and a deglitch circuit to help avoid on-offdevice will soft-start as programmed, provided that
cycling as a result of small glitches in the V
EN
signal.V
IN
is present before V
BIAS
. If V
BIAS
and V
EN
are
The enable threshold is typically 0.8V and varies withpresent before V
IN
is applied and the set soft-start
temperature and process variations. Temperaturetime has expired, then V
OUT
tracks V
IN
. If the
variation is approximately –1mV/ °C; processsoft-start time has not expired, the output tracks V
IN
variation accounts for most of the rest of the variationuntil V
OUT
reaches the value set by the charging
to the 0.4V and 1.1V limits. If precise turn-on timingsoft-start capacitor. Figure 28 shows the use of an
is required, a fast rise-time signal must be used toRC-delay circuit to hold off V
EN
until V
BIAS
has
enable the TPS74801.ramped. This technique can also be used to drive ENfrom V
IN
. An external control signal can also be used
If not used, EN can be connected to either IN orto enable the device after V
IN
and V
BIAS
are present.
BIAS. If EN is connected to IN, it should beconnected as close as possible to the largestcapacitance on the input to prevent voltage droopson that line from triggering the enable circuit.
The power-good (PG) pin is an open-drain outputand can be connected to any 5.5V or lower railthrough an external pull-up resistor. This pin requiresat least 1.1V on V
BIAS
in order to have a valid output.The PG output is high-impedance when V
OUT
isFigure 28. Soft-Start Delay Using an RC Circuit to
greater than V
IT
+ V
HYS
. If V
OUT
drops below V
IT
or ifEnable the Device
V
BIAS
drops below 1.9V, the open-drain output turnson and pulls the PG output low. The PG pin alsoasserts when the device is disabled. The pull-upresistor for PG should be in the range of 10k ΩtoThe TPS74801 provides low output noise when a
1M Ω.soft-start capacitor is used. When the device reachesthe end of the soft-start cycle, the soft-start capacitorserves as a filter for the internal reference. By usinga 0.001 µF soft-start capacitor, the output noise is
12
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INTERNAL CURRENT LIMIT LAYOUT RECOMMENDATIONS AND POWER
THERMAL PROTECTION
P =(V V ) I- ´
D IN OUT OUT
(4)
R =
qJA
(+125 C T )° - A
PD
(5)
TPS74801
SBVS074 – JANUARY 2007
DISSIPATIONThe TPS74801 features a factory-trimmed, accuratecurrent limit that is flat over temperature and supply An optimal layout can greatly improve transientvoltage. The current limit allows the device to supply performance, PSRR, and noise. To minimize thesurges of up to 2A and maintain regulation. The voltage drop on the input of the device during loadcurrent limit responds in about 10 µs to reduce the transients, the capacitance on IN and BIAS shouldcurrent during a short-circuit fault. be connected as close as possible to the device.This capacitance also minimizes the effects ofThe internal current limit protection circuitry of the
parasitic inductance and resistance of the inputTPS74801 is designed to protect against overload
source and can, therefore, improve stability. Toconditions. It is not intended to allow operation above
achieve optimal transient performance and accuracy,the rated current of the device. Continuously running
the top side of R
1
in Figure 25 should be connectedthe TPS74801 above the rated current degrades
as close as possible to the load. If BIAS is connecteddevice reliability.
to IN, it is recommended to connect BIAS as close tothe sense point of the input supply as possible. Thisconnection minimizes the voltage drop on BIASduring transient conditions and can improve theThermal protection disables the output when the
turn-on response.junction temperature rises to approximately +160 °C,allowing the device to cool. When the junction
Knowing the device power dissipation and propertemperature cools to approximately +140 °C, the
sizing of the thermal plane that is connected to theoutput circuitry is enabled. Depending on power
thermal pad is critical to avoiding thermal shutdowndissipation, thermal resistance, and ambient
and ensuring reliable operation. Power dissipation oftemperature the thermal protection circuit may cycle
the device depends on input voltage and loadon and off. This cycling limits the dissipation of the
conditions and can be calculated using Equation 4 :regulator, protecting it from damage as a result ofoverheating.
Power dissipation can be minimized and greaterActivation of the thermal protection circuit indicates
efficiency can be achieved by using the lowestexcessive power dissipation or inadequate
possible input voltage necessary to achieve theheatsinking. For reliable operation, junction
required output voltage regulation.temperature should be limited to +125 °C maximum.To estimate the margin of safety in a complete
On the SON (DRC) package, the primary conductiondesign (including heatsink), increase the ambient
path for heat is through the exposed pad to thetemperature until thermal protection is triggered; use
printed circuit board (PCB). The pad can beworst-case loads and signal conditions. For good
connected to ground or be left floating; however, itreliability, thermal protection should trigger at least
should be attached to an appropriate amount of+40 °C above the maximum expected ambient
copper PCB area to ensure the device will notcondition of the application. This condition produces
overheat. The maximum junction to ambient thermala worst-case junction temperature of +125 °C at the
resistance depends on the maximum ambienthighest expected ambient temperature and
temperature, maximum device junction temperature,worst-case load.
and power dissipation of the device, and can becalculated using Equation 5 :The internal protection circuitry of the TPS74801 isdesigned to protect against overload conditions. It isnot intended to replace proper heatsinking.Continuously running the TPS74801 into thermalshutdown degrades device reliability.
Knowing the maximum R
θJA
and system air flow, theminimum amount of PCB copper area needed forappropriate heatsinking can be calculated usingFigure 29 through Figure 31 .
13Submit Documentation Feedback
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90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074 – JANUARY 2007
Figure 29. PCB Layout and Corresponding R
θJA
Data, No Vias Under Thermal Pad
14
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90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074 – JANUARY 2007
Figure 30. PCB Layout and Corresponding R
θJA
Data, Vias Under Thermal Pad
15Submit Documentation Feedback
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90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
PCBCrossSection PCBTopView
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074 – JANUARY 2007
Figure 31. PCB Layout and Corresponding R
θJA
Data, Top Layer Only
16
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS74801DRCR ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCT ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2007
Addendum-Page 1
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