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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP2954
,
LP2954A
SNVS096E –JUNE 1999–REVISED JULY 2016
LP2954, LP2954A 5-V and Adjustable Micropower LDOs
1
1 Features
1• 5-V Output within 1.2% Over Temperature
(A Grade)
• Adjustable 1.23-V to 29-V Output Voltage
Available (LP2954IM and LP2954AIM)
• Ensured 250-mA Output Current
• Extremely Low Quiescent Current
• Low Dropout Voltage
• Reverse Battery Protection
• Extremely Tight Line and Load Regulation
• Very Low Temperature Coefficient
• Current and Thermal Limiting
• Pin Compatible with LM2940 and LM340
(5-V Version Only)
• Adjustable Version Adds ERROR Flag to Warn of
Output Drop and a Logic-Controlled Shutdown
2 Applications
• High-Efficiency Linear Regulator
• Low Dropout Battery-Powered Regulator
3 Description
The LP2954 is a 5-V micropower LDO with very low
quiescent current (90 μA typical at 1-mA load) and
very low dropout voltage (typically 60 mV at light
loads and 470 mV at 250-mA load current).
The quiescent current increases only slightly at
dropout (120 μA typical), which prolongs battery life.
The LP2954 with a fixed 5-V output is available in
three-pin TO-220 and DDPAK/TO-263 packages. The
adjustable LP2954 is provided in an 8-pin, small-
outline SOIC package. The adjustable version also
provides a resistor network which can be pin
strapped to set the output to any voltage from to
1.23 V to 29 V.
Reverse battery protection is provided for the IN pin.
The tight line and load regulation (0.04% typical), as
well as very low output temperature coefficient make
the LP2954 well suited for use as a low-power
voltage reference.
Output accuracy is ensured at both room temperature
and over the entire operating temperature range.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LP2954 SOIC (8) 4.90 mm × 3.91 mm
DDPAK/TO-263 (3) 10.18 mm × 8.41 mm
TO-220 (3) 14.986 mm × 10.16 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview................................................................. 10
7.2 Functional Block Diagrams ..................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support................. 19
11.1 Related Documentation ....................................... 19
11.2 Related Links ........................................................ 19
11.3 Receiving Notification of Documentation Updates 19
11.4 Community Resources.......................................... 19
11.5 Trademarks........................................................... 19
11.6 Electrostatic Discharge Caution............................ 19
11.7 Glossary................................................................ 19
12 Mechanical, Packaging, and Orderable
Information........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E Page
• Changed "voltage regulator" to "LDO".................................................................................................................................... 1
• Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Feature Description,Device Functional Modes,Application and Implementation,Power Supply
Recommendations,Layout,Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections; added top nav icon for TI Designs....................................................................................................... 1
• Changed RθJA value for DDPAK/TO-263 from "73°C/W" to "44.3°C/W"; TO-220 from "60°C/W" to "80.3°C/W"; SOIC
from "160°C/W" to "105.0°C/W". These values were in former FN 3 to Abs Max table......................................................... 4
• Added Power Dissipation ..................................................................................................................................................... 15
• Added Estimating Junction Temperature ............................................................................................................................. 15
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Semiconductor data sheet to TI format.................................................................................... 18
3
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5 Pin Configuration and Functions
NDE Package
3-Pin TO-220
Front View
KTT Package
3-Pin DDPAK/TO-263
Front View
D Package
8-Pin SOIC
Top
Pin Functions
PIN I/O DESCRIPTION
NAME NDE KTT D
ERROR — — 5 O Error output
FEEDBACK — — 7 I Voltage feedback input
IN 1 1 8 I Unregulated input voltage
GND 2 2 4 — Ground
OUT 3 3 1 O Regulated output voltage. This pin requires an output capacitor to
maintain stability. See Detailed Design Procedure for output capacitor
details
SENSE — — 2 I Output voltage sense
SHUTDOWN — — 3 I Disable device
5V TAP — — 6 O Internal resistor divider
4
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(1) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a
heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal
shutdown.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input supply voltage –20 30 V
Power dissipation(1) Internally Limited
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Operating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
(3) The TO-220 (NDE) package is vertically mounted in center of JEDEC High-K test board (JESD 51-7) with no additional heat sink. This is
a through-hole package; this is NOT a surface mount package.
6.4 Thermal Information
THERMAL METRIC(1) LP2954, LP2954A
UNITKTT (DDPAK/TO-263) NDE (TO-220) D (SOIC)
3 PINS 3 PINS 8 PINS
RθJA(2) Junction-to-ambient thermal resistance, High-K 44.3 80.3(3) 105.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.8 38.6 47.3 °C/W
RθJB Junction-to-board thermal resistance 23.8 73.1 45.8 °C/W
ψJT Junction-to-top characterization parameter 10.6 13.5 6.2 °C/W
ψJB Junction-to-board characterization parameter 22.7 73.1 45.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.0 0.9 — °C/W
5
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(1) When used in dual-supply systems where the regulator load is returned to a negative supply, the output voltage must be diode-clamped
to ground.
(2) Output voltage temperature coefficient is defined as the worst-case voltage change divided by the total temperature range.
(3) Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are tested separately for load
regulation in the load ranges 0.1 mA to 1 mA and 1 mAto 250 mA. Changes in output voltage due to heating effects are covered by the
thermal regulation specification.
(4) Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a
1-V differential.
(5) GND pin current is the regulator quiescent current. The total current drawn from the source is the sum of the load current plus the GND
pin current.
6.5 Electrical Characteristics
Limits are specified by production testing or correlation techniques using standard Statistical Quality Control (SQC) methods.
Unless otherwise noted: TJ= 25°C, VIN = 6 V, IL= 1 mA, CL= 2.2 μF
PARAMETER TEST CONDITIONS LP2954AI LP2954I UNIT
MIN TYP MAX MIN TYP MAX
VOOutput voltage(1)
4.975 5 5.025 4.95 5 5.05
V
−40°C to 125°C 4.94 5.06 4.9 5.1
1 mA ≤IL≤250 mA 5 5
1 mA ≤IL≤250 mA
−40°C to 125°C 4.93 5.07 4.88 5.12
ΔVO/ΔTOutput voltage temperature
coefficient See(2), –40°C ≤TJ≤125°C 20 100 20 150 ppm/°C
ΔVO/VOLine regulation VIN = 6 V to 30 V 0.03% 0.1% 0.03% 0.2%
VIN = 6 V to 30 V
–40°C ≤TJ≤125°C 0.2% 0.3%
ΔVO/VOLoad regulation
IL= 1 to 250 mA
IL= 0.1 to 1 mA(3) 0.04% 0.16% 0.04% 0.2%
IL= 1 to 250 mA
IL= 0.1 to 1 mA
–40°C ≤TJ≤125°C 0.2% 0.3%
VIN – VODropout voltage(4)
IL= 1 mA 60 100 60 100
mV
IL= 1 mA
–40°C ≤TJ≤125°C 150 150
IL= 50 mA 240 300 240 300
IL= 50 mA,
–40°C ≤TJ≤125°C 420 420
IL= 100 mA 310 400 310 400
IL= 100 mA
–40°C ≤TJ≤125°C 520 520
IL= 250 mA 470 600 470 600
IL= 250 mA
–40°C ≤TJ≤125°C 800 800
IGND Ground pin current(5)
IL= 1 mA 90 150 90 150 µA
IL= 1 mA
–40°C ≤TJ≤125°C 180 180
IL= 50 mA 1.1 2 1.1 2
mA
IL= 50 mA
–40°C ≤TJ≤125°C 2.5 2.5
IL= 100 mA 4.5 6 4.5 6
IL= 100 mA
–40°C ≤TJ≤125°C 8 8
IL= 250 mA 21 28 21 28
IL= 250 mA
–40°C ≤TJ≤125°C 33 33
IGND Ground pin current at
dropout(5)
VIN = 4.5 V 120 170 120 170 µA
VIN = 4.5 V
–40°C ≤TJ≤125°C 210 210
6
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Electrical Characteristics (continued)
Limits are specified by production testing or correlation techniques using standard Statistical Quality Control (SQC) methods.
Unless otherwise noted: TJ= 25°C, VIN = 6 V, IL= 1 mA, CL= 2.2 μF
PARAMETER TEST CONDITIONS LP2954AI LP2954I UNIT
MIN TYP MAX MIN TYP MAX
(6) Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load
or line regulation effects. Specifications are for 200-mA load pulse at VIN = 20 V (3-W pulse) for T = 10 ms.
(7) Connect a 0.1-μF capacitor from the OUT pin to the FEEDBACK pin.
(8) VREF ≤VOUT ≤(VIN −1 V), 2.3 V ≤VIN ≤30 V, 100 μA≤IL≤250 mA.
(9) Two separate tests are performed, one covering VIN = 2.5 V to VO(NOM) + 1 V and the other test for VIN = 2.5 V to VO(NOM) + 1 V to 30 V.
(10) VSHUTDOWN ≤1.1 V, VOUT = VO(NOM).
(11) Comparator thresholds are expressed in terms of a voltage differential at the FEEDBACK pin below the nominal reference voltage
measured at VIN = VO(NOM) + 1 V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain,
which is VOUT/VREF = (R1 + R2 ) / R2.
ILIMIT Current limit VO= 0 V 380 500 380 500 mA
VO= 0 V
–40°C ≤TJ≤125°C 530 530
ΔVO/ΔPDThermal regulation See(6) 0.05 0.2 0.05 0.2 %/W
enOutput noise
10 Hz to 100 kHz
IL= 100 mA, CL= 2.2 µF 400 400
μVRMS
IL= 100 mA, CL= 33 µF 260 260
IL= 100 mA, CL= 33 µF(7) 80 80
ADDITIONAL SPECIFICATIONS FOR THE ADJUSTABLE DEVICE (LP2954AIM and LP2954IM)
VREF Reference voltage See(8) 1.215 1.23 1.245 1.205 1.23 1.255 V
See(8)
–40°C ≤TJ≤125°C 1.205 1.255 1.19 1.27
ΔVREF/
VREF Reference voltage line
regulation
VIN= 2.5 V to VO(NOM) + 1 V 0.03% 0.1% 0.03% 0.2%
VIN= 2.5 V to VO(NOM) +1 V to
30 V(9)(8)–40°C ≤TJ≤125°C 0.2% 0.4%
ΔVREF/ΔTReference voltage
temperature coefficient See(2)
–40°C ≤TJ≤125°C 20 ppm/°C
IB(FB) Feedback pin bias current 20 40 20 40 nA
–40°C ≤TJ≤125°C 60 60
IGND Ground pin current at
shutdown(5) VSHUTDOWN ≤1.1 V 105 140 105 140 μA
IO(SINK) Output OFF pulldown
current
See(10) 30 30 mA
See(10)
–40°C ≤TJ≤125°C 20 20
DROPOUT DETECTION COMPARATOR
IOH Output HIGH leakage
current
VOH = 30 V 0.01 1 0.01 1 µA
VOH = 30 V, –40°C ≤TJ≤
125°C 2 2
VOL Output LOW voltage
VIN = VO(NOM) −0.5 V
IO(COMP) = 400 μA
–40°C ≤TJ≤125°C 150 250 150 250 mV
400 400
VTHR(MAX) Upper threshold voltage See(11) –80 –60 –35 –80 –60 –35 mV
See(11)
–40°C ≤TJ≤125°C –95 –25 –95 –25
VTHR(MIN) Lower threshold voltage See(11) –110 –85 –55 –110 –85 –55 mV
See(11)
–40°C ≤TJ≤125°C –160 –40 –160 –40
HYST Hysteresis See(11) 15 15 mV
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Electrical Characteristics (continued)
Limits are specified by production testing or correlation techniques using standard Statistical Quality Control (SQC) methods.
Unless otherwise noted: TJ= 25°C, VIN = 6 V, IL= 1 mA, CL= 2.2 μF
PARAMETER TEST CONDITIONS LP2954AI LP2954I UNIT
MIN TYP MAX MIN TYP MAX
SHUTDOWN INPUT
VOS Input offset voltage (Referred to VREF)−7.5 ±3 7.5 −7.5 ±3 7.5 mV
(Referred to VREF), –40°C ≤TJ
≤125°C –10 10 –10 10
HYST Hysteresis 6 6 mV
IBInput bias current VIN(SHUTDOWN) = 0 V to 5 V –30 10 30 –30 10 30 nA
VIN(SHUTDOWN) = 0 V to 5 V,
–40°C ≤TJ≤125°C –50 50 –50 50
6.6 Typical Characteristics
Figure 1. Quiescent Current Figure 2. Quiescent Current
Figure 3. Ground Pin Current vs Load Figure 4. Ground Pin Current
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Typical Characteristics (continued)
Figure 5. Ground Pin Current Figure 6. Output Noise Voltage
Figure 7. Ripple Rejection Figure 8. Ripple Rejection
Figure 9. Ripple Rejection Figure 10. Output Impedance
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Typical Characteristics (continued)
Figure 11. Dropout Characteristics Figure 12. Thermal Response
Figure 13. Short-Circuit Output Current and Maximum
Output Current Figure 14. Maximum Power Dissipation (DDPAK/TO-263)
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7 Detailed Description
7.1 Overview
The LP2954 is a 5-V micropower LDO with very low quiescent current (90 μA typical at 1-mA load) and very low
dropout voltage (typically 60 mV at light loads and 470 mV at 250-mA load current).
7.2 Functional Block Diagrams
Figure 15. LP2954 TO-220 and TO-263 Functional Block Diagram
Figure 16. LP2954 SOIC Functional Block Diagram
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7.3 Feature Description
7.3.1 Dropout Voltage
The dropout voltage of the regulator is defined as the minimum input-to-output voltage differential required for the
output voltage to stay within 100 mV of the output voltage measured with a 1-V differential. The dropout voltages
for various values of load current are listed under Electrical Characteristics.
If the regulator is powered from a rectified AC source with a capacitive filter, the minimum AC line voltage and
maximum load current must be used to calculate the minimum voltage at the input of the regulator. The minimum
input voltage, including AC ripple on the filter capacitor, must not drop below the voltage required to keep the
LP2954 in regulation. It is also advisable to verify operating at minimum operating ambient temperature, because
the increasing ESR of the filter capacitor makes this a worst-case test for dropout voltage due to increased ripple
amplitude.
7.3.2 Dropout Detection Comparator
This comparator produces a logic LOW whenever the output falls out of regulation by more than about 5%. The
5% value is from the comparators built-in offset of 60 mV divided by the 1.23-V reference. The 5% low trip level
remains constant regardless of the programmed output voltage. An out-of-regulation condition can result from
low input voltage, current limiting, or thermal limiting.
Figure 17 gives a timing diagram showing the relationship between the output voltage, the ERROR output, and
input voltage as the input voltage is ramped up and down to a regulator programmed for 5-V output. The ERROR
signal becomes low at about 1.3-V input. It goes high at about 5-V input, where the output equals 4.75 V.
Because the dropout voltage is load dependent, the input voltage trip points vary with load current. The output
voltage trip point does not vary.
The comparator has an open-collector output which requires an external pullup resistor. This resistor may be
connected to the regulator output or some other supply voltage. Using the regulator output prevents an invalid
HIGH on the comparator output which occurs if it is pulled up to an external voltage while the regulator input
voltage is reduced below 1.3 V. In selecting a value for the pullup resistor note that, while the output can sink
400 μA, this current adds to battery drain. Suggested values range from 100 kΩto 1 MΩ. This resistor is not
required if the output is unused.
When VIN ≤1.3 V, the ERROR pin becomes a high impedance, allowing the error flag voltage to rise to its pullup
voltage. Using VOUT as the pullup voltage (rather than an external 5-V source) keeps the error flag voltage below
1.2 V (typical) in this condition. The user may wish to divide down the error flag voltage using equal-value
resistors (10 kΩsuggested) to ensure a low-level logic signal during any fault condition, while still allowing a valid
high logic level during normal operation.
* In shutdown mode, ERROR goes high if it has been pulled up to an external supply. To avoid this invalid response,
pull up to regulator output.
** Exact value depends on dropout voltage. (See Dropout Voltage)
Figure 17. ERROR Output Timing
7.3.3 Output Isolation
The regulator output can be left connected to an active voltage source (such as a battery) with the regulator input
power turned off, as long as the regulator ground pin is connected to ground. If the ground pin is left floating,
damage to the regulator can occur if the output is pulled up by an external voltage source.
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Feature Description (continued)
7.3.4 Reducing Output Noise
In reference applications it may be advantageous to reduce the AC noise present on the output. One method is
to reduce regulator bandwidth by increasing output capacitance. This is relatively inefficient, because large
increases in capacitance are required to get significant improvement.
Noise can be reduced more effectively by a bypass capacitor placed across R1 (refer to Figure 19). The formula
for selecting the capacitor to be used is:
CB= 1 / 2πR1 × 20 Hz (1)
This gives a value of about 0.1 μF. When this is used, the output capacitor must be 6.8 μF (or greater) to
maintain stability. The 0.1-μF capacitor reduces the high frequency gain of the circuit to unity, lowering the output
noise from 260 μV to 80 μV using a 10-Hz to 100-kHz bandwidth. Also, noise is no longer proportional to the
output voltage, so improvements are more pronounced at high output voltages.
7.4 Device Functional Modes
7.4.1 Shutdown Input
A logic-level signal shuts off the regulator output when a LOW (< 1.2 V) is applied to the SHUTDOWN input.
To prevent possible mis-operation, the SHUTDOWN input must be actively terminated. If the input is driven from
open-collector logic, a pullup resistor (TI recommends 20 kΩto 100 kΩ) must be connected from the
SHUTDOWN input to the regulator input.
If the SHUTDOWN input is driven from a source that actively pulls high and low (like an operational amplifier),
the pullup resistor is not required, but may be used.
If the shutdown function is not to be used, the cost of the pullup resistor can be saved by simply tying the
SHUTDOWN input directly to the regulator input.
IMPORTANT: Because the Absolute Maximum Ratings state that the SHUTDOWN input cannot go more than
0.3 V below ground, the reverse-battery protection feature that protects the regulator input is sacrificed if the
SHUTDOWN input is tied directly to the regulator input.
If reverse-battery protection is required in an application, the pullup resistor between the SHUTDOWN input and
the regulator input must be used. The recommended 20 kΩto 100 kΩprovides adequate protection of the
SHUTDOWN pin during negative voltage transitions at the IN pin.
IN OUT
GND
VIN 5 V OUT
1 µF 2.2 µF LOAD
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP2954-N is a linear voltage regulator operating from 2.3 V to 30 V on the input and regulated output
voltage of 5 V with typical 0.5% accuracy (LP2954AI) and 250 mA maximum output current. For linear voltage
regulator the efficiency is defined by the ratio of output voltage to input voltage (efficiency = VOUT/VIN). To
achieve high efficiency, the dropout voltage (VIN – VOUT) must be as small as possible, thus requiring a very low
dropout LDO. Successfully implementing an LDO in an application depends on the application requirements. If
the requirements are simply input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified to ensure a solid design. If timing, start-up, noise, PSRR, or any other
transient specification is required, the design becomes more challenging.
8.2 Typical Application
Figure 18. LP2954 Typical Application
8.2.1 Design Requirements
For typical LDO applications, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.5 V to 30 V
Output voltage 1.23 V to 29 V
Output current 250 mA (maximum)
RMS noise, 10 Hz to100 kHz 260 μVRMS
8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
A 2.2 μF (or greater) capacitor is required between the OUT pin and GND to assure stability (refer to Figure 20).
Without this capacitor, the device may oscillate. Most types of tantalum or aluminum electrolytic capacitors work
here. Film-type capacitors work, but are more expensive. Many aluminum electrolytics contain electrolytes which
freeze at −30°C, which requires the use of solid tantalums below −25°C. The important parameters of the
capacitor are an equivalent series resistance (ESR) of about 5 Ωor less and a resonant frequency above 500
kHz (the ESR may increase by a factor of 20 or 30 as the temperature is reduced from 25°C to −30°C). The
value of this capacitor may be increased without limit. At lower values of output current, less output capacitance
is required for stability. The capacitor can be reduced to 0.68 μF for currents below 10 mA or 0.22 μF for currents
below 1 mA.
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Place a 1-μF capacitor from the IN pin to GND if there is more than 10 inches of wire between the input and the
AC filter capacitor or if a battery input is used.
Programming the output for voltages below 5 V runs the error amplifier at lower gains requiring more output
capacitance for stability. At 3.3-V output, a minimum of 4.7 μF is required. For the worst case condition of 1.23-V
output and 250 mA of load current, a 6.8-μF (or larger) capacitor must be used.
Stray capacitance to the FEEDBACK pin can cause instability. This problem is most likely to appear when using
high value external resistors to set the output voltage. Adding a 100-pF capacitor between the OUT and
FEEDBACK pins and increasing the output capacitance to 6.8 μF (or greater) solves the problem.
8.2.2.2 Minimum Load
When setting the output voltage using an external resistive divider, TI recommends a minimum current of 1 μA
through the resistors to provide a minimum load.
It should be noted that a minimum load current is specified in several of the electrical characteristic test
conditions, so this value must be used to obtain correlation on these tested limits. The part is parametrically
tested down to 100 μA, but is functional with no load.
8.2.2.3 Programming The Output Voltage
The SOIC version of the LP2954 regulator may be pin strapped for 5-V operation using its internal resistive
divider by tying the OUT and SENSE pins together and also tying the FEEDBACK and 5V TAP pins together.
Alternatively, it may be programmed for any voltage between the 1.23-V reference and the 30-V maximum rating
using an external pair of resistors (see Figure 19). The complete equation for the output voltage is:
VOUT = VREF × (1 + R1 / R2) + (IFB × R1) (2)
where VREF is the 1.23-V reference and IFB is the FEEDBACK pin bias current (−20 nA typical). The minimum
recommended load current of 1 μA sets an upper limit of 1.2 MΩon the value of R2 in cases where the regulator
must work with no load (see Minimum Load). IFB produces a typical 2% error in VOUT which can be eliminated at
room temperature by trimming R1. For better accuracy, choosing R2 = 100 kΩreduces this error to 0.17% while
increasing the resistor program current to 12 μA. Because the typical quiescent current is 120 μA, this added
current is negligible.
*Drive with TTL-low to shutdown
Figure 19. Adjustable Regulator
15
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8.2.2.4 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 3.
PD(MAX) = (VIN(MAX) – VOUT)×IOUT (3)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 4 or Equation 5:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)) (4)
PD(MAX) = (TJ(MAX) – TA(MAX)) / RθJA (5)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
8.2.2.5 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 6 or Equation 7.
TJ(MAX) = TTOP + (ΨJT × PD(MAX))
where
• PD(MAX) is explained in Equation 5
• TTOP is the temperature measured at the center-top of the device package. (6)
TJ(MAX) = TBOARD + (ΨJB × PD(MAX))
where
• PD(MAX) is explained in Equation 5.
• TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the
package edge. (7)
For more information about the thermal characteristics ΨJT and ΨJB,Semiconductor and IC Package Thermal
Metrics; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics; and for more
information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see Thermal Characteristics of Linear
and Logic Packages Using JEDEC PCB Designs. These application notes are available at www.ti.com.
8.2.2.6 Heatsinking the TO-220 Package
A heat sink may be required with the LP2954IT depending on the maximum power dissipation and maximum
ambient temperature of the application. Under all possible operating conditions, the junction temperature must be
within the range specified under Recommended Operating Conditions.
To determine if a heat sink is required, the maximum power dissipated by the regulator, P(MAX), must be
calculated. It is important to remember that if the regulator is powered from a transformer connected to the AC
line, the maximum specified AC input voltage must be used (because this produces the maximum DC input
voltage to the regulator). Figure 20 shows the voltages and currents that are present in the circuit. The formula
for calculating the power dissipated in the regulator is also shown in Figure 20.
16
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*See External Capacitors
PD= (((VIN – VOUT) × IOUT) + (VIN × IG))
Figure 20. Basic 5-V Regulator Circuit
The next parameter which must be calculated is the maximum allowable temperature rise, TR(MAX). This is
calculated by using the formula:
TR(MAX) = TJ(MAX) −TA(MAX)
where
• TJ(MAX) is the maximum allowable junction temperature
• TA(MAX) is the maximum ambient temperature (8)
Using the calculated values for TR(MAX) and P(MAX), the required value for junction-to-ambient thermal resistance,
RθJA , can now be found:
RθJA = TR(MAX) / P(MAX) (9)
If the calculated value is 60°C/W or higher , the regulator may be operated without an external heat sink. If the
calculated value is below 60°C/W, an external heatsink is required. The required thermal resistance for this heat
sink can be calculated using the formula:
RθHA = RθJA −RθJC(bot) −RθCH
where
• RθJC(bot) is the junction-to-case thermal resistance, which is specified as 0.9°C/W maximum for the LP2954IT
• RθCH is the case-to-heat-sink thermal resistance, which is dependent on the interfacing material (if used). For
details and typical values in Table 2 and Table 3.
• Rθ(H-A) is the heatsink-to-ambient thermal resistance. It is this specification (listed on the heat-sink
manufacturers data sheet) which defines the effectiveness of the heat sink. The heat sink selected must have
a thermal resistance which is equal to or lower than the value of RθHA calculated from the above listed
formula. (10)
Table 2. Typical Values of Case-To-Heatsink Thermal
Resistance (RθCH) (Data from Aavid Engineering)
UNIT
(C°/W)
Silicone grease 1
Dry interface 1.3
Mica with grease 1.4
Table 3. Typical Values Of Case-To-Heatsink Thermal
Resistance (RθCH) (Data from Thermalloy)
UNIT
(C°/W)
Thermasil III 1.3
Thermasil II 1.5
Thermalfilm (0.002) with grease 2.2
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8.2.3 Application Curves
Figure 21. Line Transient Response Figure 22. Line Transient Response
Figure 23. Load Transient Response Figure 24. Load Transient Response
9 Power Supply Recommendations
The LP2954 is designed to operate from a minimum input voltage supply of either 2.5 V or VOUT(NOM) + 1 V,
whichever is higher. The maximum input supply voltage is 30 V, but may be limited by thermal dissipation of the
selected package. The input voltage range provides adequate headroom in order for the device to have a
regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors
with low ESR can help. improve the output noise performance.
Ground
VOUT
VIN
Input
Capacitor
Output
Capacitor
OUT
SENSE
SHUTDOWN
GND ERROR
IN
5V TAP
FEEDBACK
Error Pullup
Resistor VOUT
12 3
IN
GND
OUT
VIN
Input
Capacitor VOUT
Output
Capacitor
Ground
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all the circuit components on the same side of the circuit board and as near
as practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability.
TI also recommends a ground reference plane and is either embedded in the PCB itself or located on the bottom
side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage,
shield noise, and behaves similar to a thermal plane to spread heat from the LDO device. In most applications,
this ground plane is necessary to meet thermal requirements.
10.2 Layout Example
Figure 25. LP2954 TO-263 Board Layout
Figure 26. LP2954 SOIC Board Layout
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11 Device and Documentation Support
11.1 Related Documentation
For additional information, see the following:
•Semiconductor and IC Package Thermal Metrics
•Using New Thermal Metrics
•Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
11.2 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LP2954 Click here Click here Click here Click here Click here
LP2954A Click here Click here Click here Click here Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP2954AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2954AISX/NOPB DDPAK/
TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
LP2954IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2954ISX/NOPB DDPAK/
TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2954AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2954AISX/NOPB DDPAK/TO-263 KTT 3 500 367.0 367.0 45.0
LP2954IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2954ISX/NOPB DDPAK/TO-263 KTT 3 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2016
Pack Materials-Page 2
MECHANICAL DATA
NDE0003B
www.ti.com
MECHANICAL DATA
KTT0003B
www.ti.com
BOTTOM SIDE OF PACKAGE
TS3B (Rev F)
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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