19-5144; Rev 0; 2/10 TION KIT EVALUA BLE IL AVA A 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier The MAX3945 is a +3.3V, multirate, low-power limiting amplifier optimized for Fibre Channel and Ethernet transmission systems at data rates up to 11.3Gbps. The highsensitivity limiting amplifier limits the signal generated by a transimpedance amplifier into a CML-level differential output signal. All differential inputs and outputs (I/O) are optimally back terminated for 50I transmission line PCB design. The MAX3945's dual-path limiting amplifier has programmable filtering to optimize sensitivity for different data rates and to suppress relaxation oscillations that could occur in some optical systems. The MAX3945 incorporates two loss-of-signal (LOS) circuits and a programmable time mask for the LOS output. A 3-wire digital interface reduces the pin count and enables control of LOS threshold, LOS polarity, LOS mode, CML output level, input offset correction, receive (Rx) polarity, Rx input filter, and Rx deemphasis without the need for external components. The MAX3945 is packaged in a 3mm x 3mm, 16-pin TQFN package. Applications 1x/2x/4x/8x SFF/SFP/SFP+ MSA Fibre-Channel Optical Transceiver 10GBASE-SR/LR SFP+ Optical Transceiver 10G PON ONU MAX3945ETE+ S 130mW Power Dissipation Enables < 1W SFP+ Modules S Enables Single-Module Design Compliance with 1000BASE-SX/LX and 10GBASE-SR/LR Specifications S -25.3dBm Optical Sensitivity at 1.25Gbps Using a 10.32Gbps ROSA S Selectable 1GHz/2.1GHz/2.5GHz/3GHz Input Filters at RATE_SEL = 0 Setting S Supports SFF-8431 SFP+ MSA and SFF-8472 Digital Diagnostic S Total Power Dissipation of 130mW at 3.3V Power Supply with RSSI Monitor-Based LOS S Total Power Dissipation of 154mW at 3.3V Power Supply with Rx Input-Based LOS S 4mVP-P Input Sensitivity at 11.3Gbps S 4psP-P DJ at 11.3Gbps with RATE_SEL = 1 S 4psP-P DJ at 8.5Gbps with RATE_SEL = 1 S 5psP-P DJ at 4.25Gbps with RATE_SEL = 0, BW1 = 1, BW0 = 1 S 9.0psP-P DJ at 1.25Gbps with RATE_SEL = 0, BW1 = 0, BW0 = 0 S 26ps Rise and Fall Time with RATE_SEL = 1 S 52ps Rise and Fall Time with RATE_SEL = 0 Ordering Information PART Features TEMP RANGE PIN-PACKAGE -40NC to +85NC 16 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. S CML Output with Level Adjustment and Squelch Mode S Programmable CML Output Deemphasis S CML Output Polarity Select S LOS Polarity Select S Programmable Masking Time for the LOS Output Typical Application Circuit appears at end of data sheet. S LOS Assert/Deassert Level Adjustment S Choice of Rx Input-Based LOS or RSSI Monitor- Based LOS S 3-Wire Digital Interface Compatible with Maxim's SFP+ Family of Products ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX3945 General Description MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier ABSOLUTE MAXIMUM RATINGS VCC. ......................................................................-0.3V to +4.0V Voltage Range at SDA, SCL, CSEL, LOS, CAZ, RPMIN.................................. -0.3V to (VCC + 0.3V) Voltage Range at ROUT+, ROUT-.........(VCC - 2V) to (VCC + 0.3V) Voltage Range at RIN+, RIN-......... (VCC - 1.7V) to (VCC + 0.3V) Current Range Into LOS....................................... -1mA to +5mA Current Range Into SDA...................................... -1mA to +1mA Current Out of ROUT+, ROUT-...........................................40mA Continuous Power Dissipation (TA = +70NC) 16-Pin TQFN (derate 14.7mW/NC above +70NC)..........1.176W Operating Junction Temperature Range.......... -55NC to +150NC Storage Temperature Range............................. -65NC to +160NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, CCAZ = 0.1FF, TA = -40NC to +85NC. Registers are set to default values, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Includes the CML output current, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, LOS1_EN = 1, LOS2_EN = 0 46.6 62 Includes the CML output current, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, LOS1_EN = 0, LOS2_EN = 1 39.4 UNITS POWER SUPPLY Power-Supply Current Power-Supply Voltage ICC VCC Power-Supply Noise mA 2.85 52.5 3.63 f < 10MHz 100 10MHz < f < 20MHz 10 V mVP-P GENERAL Input Data Rate 1.06 Input/Output SNR 14.1 10.32 BER 11.3 Gbps 10E-12 POWER-ON RESET (POR) POR Deassert Threshold 2.55 POR Assert Threshold 2.75 2.3 2.45 75 100 125 RATE_SEL = 1, input transition time 25ps, 10.32Gbps, PRBS23-1 pattern 4 8 RATE_SEL = 0, input transition time 260ps, 1.25Gbps, K28.5 pattern 1 2 V V INPUT SPECIFICATIONS Differential Input Resistance RIN+/RIN- RIN_DIFF Input Sensitivity (Note 1) VINMIN Input Overload VINMAX SDD11 Input Return Loss SCC11 RPMIN Input-Current High IIH I mVP-P 1.2 VP-P DUT is powered on, f P 5GHz 10 DUT is powered on, f P 16GHz 7 DUT is powered on, 1GHz < f P 5GHz 13 DUT is powered on, 1GHz < f P 16GHz 5 LOS1_EN = 0 and LOS2_EN = 1, VRPMIN = 2V 50 2 _______________________________________________________________________________________ dB dB nA 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier (VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, CCAZ = 0.1FF, TA = -40NC to +85NC. Registers are set to default values, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS External RPMIN Filter Capacitor MIN TYP MAX 100 UNITS pF OUTPUT SPECIFICATIONS Differential Output Resistance ROUT+/ROUT- ROUTDIFF SDD22 Output Return Loss SCC22 Differential Output-Voltage High Differential Output-Voltage Medium 75 DUT is powered on, f P 16GHz 7 DUT is powered on, 1GHz < f P 5GHz 10 DUT is powered on, 1GHz < f P 16GHz 6 tR/tF I dB 5mVP-P P VIN P 1200mVP-P, RATE_SEL = 0, SET_CML[7:0] = 169d (decimal) 595 800 1005 10mVP-P P VIN P 1200mV, RATE_SEL = 1, SET_CML[7:0] = 181d 595 800 1005 10mVP-P P VIN P 1200mVP-P, RATE_SEL = 1, SET_CML[7:0] = 91d 300 400 515 mVP-P 255 Decimal mVP-P mVP-P 60 Differential Output Signal When Squelched (Note 1) 125 13 DUT is powered on, f P 5GHz SET_CML DAC Range Data Output Transition Time (20% to 80%) (Note 1) 100 Outputs AC-coupled, SET_CML[7:0] = 181d, at 8.5Gbps, SQ_EN = 1 6 15 60mVP-P P VIN P 400mVP-P at 10.32Gbps, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, input transition time 25ps, pattern 11110000 26 35 10mVP-P P VIN P 1200mVP-P at 1.25Gbps, RATE_SEL = 0, VDIFF_ROUT = 800mVP-P, input transition time 260ps, pattern 11110000 52 90 10mVP-P P VIN P 1200mVP-P at 8.5Gbps, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, input transition time 28ps 4 8 60mVP-P P VIN P 400mVP-P at 10.32Gbps, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, input transition time 28ps 4 9 60mVP-P P VIN P 400mVP-P at 11.3Gbps, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P, RXDE_EN = 0, input transition time 28ps 4 9 10mVP-P P VIN P 1200mVP-P at 1.25Gbps, RATE_SEL = 0, BW1 = 0, BW0 = 0, VDIFF_ROUT = 800mVP-P, input transition time 260ps 9 30 10mVP-P P VIN P 1200mVP-P at 4.25Gbps, RATE_SEL = 0, BW1 = 1, BW0 = 1, VDIFF_ROUT = 800mVP-P, input transition time 28ps 5 10 ps TRANSFER CHARACTERISTICS Deterministic Jitter (Notes 1, 2) DJ psP-P _______________________________________________________________________________________ 3 MAX3945 ELECTRICAL CHARACTERISTICS (continued) MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, CCAZ = 0.1FF, TA = -40NC to +85NC. Registers are set to default values, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC, unless otherwise noted.) PARAMETER Random Jitter (Note 1) SYMBOL CONDITIONS RJ Input = 60mVP-P at 10.32Gbps, RATE_SEL = 1, RXDE_EN = 0, input transition time 28ps, pattern 11110000, VDIFF_ROUT = 800mVP-P Low-Frequency Cutoff (Simulated Value) Small-Signal Bandwidth (Simulated Value) f3dB MIN TYP MAX UNITS 0.28 0.51 psRMS RATE_SEL = 0, CCAZ = 0.1FF 2 RATE_SEL = 1, CCAZ = 0.1FF 0.7 RATE_SEL = 0, BW1 = 0, BW0 = 0 1.0 RATE_SEL = 0, BW1 = 0, BW0 = 1 2.1 RATE_SEL = 0, BW1 = 1, BW0 = 0 2.5 RATE_SEL = 0, BW1 = 1, BW0 = 1 3.0 RATE_SEL = 1 kHz GHz 9 Rx INPUT-BASED LOS SPECIFICATIONS (LOS1_EN = 1 and LOS2_EN = 0) (Note 1) LOS Assert Sensitivity Range (Note 3) SET_LOS DAC Range 14 77 mVP-P 7 63 Decimal LOS Hysteresis 10log(VDEASSERT/VASSERT) 1.25 2.1 LOS Assert/Deassert Time (Note 4) 2.3 20 80 8 11 14 14 18 22 39 49 58 65 82 95 77 96 112 127 158 182 Low Assert Level Low Deassert Level Medium Assert Level Medium Deassert Level High Assert Level High Deassert Level SET_LOS[5:0] = 7d (Note 3) SET_LOS[5:0] = 32d (Note 3) SET_LOS[5:0] = 63d (Note 3) LOS Output Masking Time Range SET_LOSTIMER[6:0] = 0d for minimum and SET_LOSTIMER[6:0] = 127d for maximum 0 LOS Output Masking DAC Resolution SET_LOSTIMER[6:0] = 1d to 127d 23 35 dB Fs mVP-P mVP-P mVP-P 2920 Fs 50 Fs RSSI MONITOR-BASED LOS SPECIFICATIONS (LOS1_EN = 0 and LOS2_EN = 1) (Note 1) LOS Assert Sensitivity Range (Note 5) SET_LOS DAC Range 8.3 90 mV 4 63 Decimal LOS Hysteresis 10log(VDEASSERT/VASSERT) 1.25 2.1 LOS Assert/Deassert Time (Note 4) 2.3 20 Low Assert Level Low Deassert Level Medium Assert Level Medium Deassert Level High Assert Level High Deassert Level SET_LOS[5:0] = 4d (Note 5) SET_LOS[5:0] = 32d (Note 5) SET_LOS[5:0] = 63d (Note 5) dB 80 5.1 6.7 8.3 9.0 10.8 12.7 45 50 55 77 85 92 90 98 106 153 167 180 LOS Output Masking Time Range SET_LOSTIMER[6:0] = 0d for minimum and SET_LOSTIMER[6:0] = 127d for maximum 0 LOS Output Masking DAC Resolution SET_LOSTIMER[6:0] = 1d to 127d 23 35 4 _______________________________________________________________________________________ Fs mV mV mV 2920 Fs 50 Fs 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier (VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, CCAZ = 0.1FF, TA = -40NC to +85NC. Registers are set to default values, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUT LEVEL VOLTAGE DAC (SET_CML) Full-Scale Voltage VFS Resolution Integral Nonlinearity INL 100I differential resistive load, RXDE_EN = 0 1192 100I differential resistive load, RATE_SEL = 1, RXDE_EN = 1, RXDE1 = 1, RXDE0 = 1 (maximum deemphasis) 828 100I differential resistive load, RXDE_EN = 0 4.5 100I differential resistive load, RATE_SEL = 1, RXDE_EN = 1, RXDE1 = 1, RXDE0 = 1 (maximum deemphasis) 3.3 mVP-P mVP-P SET_CML[7:0] > 60d Q0.9 LSB 96 mVP-P LOS THRESHOLD VOLTAGE DAC (SET_LOS) Full-Scale Voltage VFS Resolution LOS1_EN = 1, LOS2_EN = 0 LOS1_EN = 0, LOS2_EN = 1 98 mV LOS1_EN = 1, LOS2_EN = 0 1.52 mVP-P LOS1_EN = 0, LOS2_EN = 1 1.56 mV INL SET_LOS[5:0] > 3d Q0.7 LSB LOS Output High Voltage VOH RLOS = 4.7kI to 10kI to VCC LOS Output Low Voltage Integral Nonlinearity CONTROL I/O SPECIFICATIONS VCC 0.5 VCC V VOL 0 0.4 V Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL 0.8 V RLOS = 4.7kI to 10kI to VCC 3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL) Input Hysteresis VHYST 0.082 Input Leakage Current IIL,IH VIN = 0V or VCC, internal pullup or pulldown (75kI typ) Output High Voltage VOH External pullup of 4.7kI to VCC Output Low Voltage VOL External pullup of 4.7kI to VCC V 85 FA VCC 0.5 VCC V 0 0.4 V 1000 kHz 3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 5) SCL Clock Frequency fSCL 0 SCL Pulse-Width High tCH 500 400 ns SCL Pulse-Width Low tCL 500 ns SDA Setup Time tDS 100 ns SDA Hold Time tDH 100 ns tD 5 ns SCL Rise to SDA Propagation Time CSEL Pulse-Width Low tCSW 500 ns _______________________________________________________________________________________ 5 MAX3945 ELECTRICAL CHARACTERISTICS (continued) MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, CCAZ = 0.1FF, TA = -40NC to +85NC. Registers are set to default values, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CSEL Leading Time Before the First SCL Edge tL 500 ns CSEL Trailing Time After the Last SCL Edge tT 500 ns SDA, SCL External Load CB Total bus capacitance on one line with 4.7kI to VCC 20 pF Note 1: Guaranteed by design and characterization, TA = -40NC to +95NC. Note 2: D eterministic jitter is measured with a repeating K28.5 pattern [00111110101100000101] for 1.25Gbps to 8.5Gbps data. At 10.32Gbps and 11.3Gbps, a repeating K28.5 plus 59 0s and K28.5 plus 59 1s pattern is used. Deterministic jitter is defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ). Note 3: LOS1_EN = 1, data rates of 1.25Gbps to 8.5Gbps with K28.5 pattern, and 6.4GHz input filter. For data rates of 10.32Gbps to 11.3Gbps, the input filter is 12.5GHz and the pattern is PRBS23-1. Note 4: M easurement includes an input AC-coupling capacitor of 100nF and CCAZ of 100nF. The signal at the RIN or RPMIN input is switched between two amplitudes: Signal_ON and Signal_OFF. 1) Receiver operates at sensitivity level plus 1dB power penalty a) Signal_OFF = 0 Signal_ON = (+8dB) + 10log(min_assert_level) b) Signal_ON = (+1dB) + 10log(max_deassert_level) Signal_OFF = 0 2) Receiver operates at overload Signal_OFF = 0 Signal_ON = 1.2VP-P max_deassert_level and min_assert_level are measured for one SET_LOS setting Note 5: LOS1_EN = 0, LOS2_EN = 1, DC voltage applied to the RPMIN input. 6 _______________________________________________________________________________________ 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier RECEIVE OUTPUT FROM OPTICAL SYSTEM, 10.32Gbps, OPTICAL INPUT -10dBm, RXDE1 = 1, RXDE0 = 0 RECEIVE OUTPUT FROM OPTICAL SYSTEM, 10.32Gbps, OPTICAL INPUT -15dBm, RXDE1 = 1, RXDE0 = 0 RECEIVE OUTPUT FROM OPTICAL SYSTEM, 10.32Gbps, OPTICAL INPUT -20dBm, RXDE1 = 1, RXDE0 = 0 OPTICAL BER CURVES (NEC NR3312) K28.5 PATTERN AT 1.25Gbps, SET_CML[7:0] = 169d, RATE_SEL = 0, BW0 = 0, BW1 = 0 K28.5 PATTERN AT 4.25Gbps, SET_CML[7:0] = 169d, RATE_SEL = 0, BW0 = 1, BW1 = 1 MAX3945 toc01 1.00E-02 8.5Gbps, PRBS9, RATE_SEL = 1 1.00E-03 4.5Gbps, PRBS9, RATE_SEL = 1 1.00E-04 MAX3945 toc05 100mV/div 4.5Gbps, PRBS9, RATE_SEL = 0, BW1 = 1, BW0 = 1 1.00E-07 1.25Gbps, PRBS9, RATE_SEL = 0, BW1 = 1, BW0 = 1 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.25Gbps, PRBS9, RATE_SEL = 0, BW1 = 0, BW0 = 0 1.00E-12 -27 -26 -25 -24 -23 -22 -21 200ps/div 50ps/div K28.5 PATTERN AT 10.3Gbps, SET_CML[7:0] = 148d, RATE_SEL = 1, RXDE_EN = 0 K28.5 PATTERN AT 11.3Gbps, SET_CML[7:0] = 148d, RATE_SEL = 1, RXDE_EN = 0 AVERAGE POWER dBm (Er~12dB) K28.5 PATTERN AT 8.5Gbps, SET_CML[7:0] = 148d, RATE_SEL = 1, RXDE_EN = 0 20ps/div MAX3945 toc09 100mVP-P MAX3945 toc08 100mVP-P MAX3945 toc07 100mVP-P BER 1.00E-05 1.00E-06 MAX3945 toc06 100mV/div 10.3Gbps, PRBS31, RATE_SEL = 1 MAX3945 toc03 MAX3945 toc04 1.00E-01 MAX3945 toc02 18ps/div 18ps/div _______________________________________________________________________________________ 7 MAX3945 Typical Operating Characteristics (VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) DEEMPHASIS VALUE vs. SET_CML DAC SETTING (RATE_SEL = 1) 1000 RXDE1 = 0, RXDE0 = 0 900 RXDE1 = 0, RXDE0 = 1 800 RXDE1 = 1, RXDE0 = 0 700 600 RXDE1 = 0, RXDE0 = 1 RXDE1 = 0, RXDE0 = 0 2 RXDE1 = 1, RXDE0 = 1 500 RXDE_EN = 0 0 100 50 150 200 250 140 DEASSERT 120 100 80 60 ASSERT 40 20 400 300 100 50 150 200 0 250 10 0 20 30 40 50 60 70 SET_CML DAC SETTING SET_CML DAC SETTING SET_LOS[5:0] DAC CODE RSSI MONITOR-BASED LOS THRESHOLDS (LOS1_EN = 0 AND LOS2_EN = 1) LOS MASKING TIME vs. DAC SETTING DETERMINISTIC JITTER vs. INPUT AMPLITUDE AT 1.25Gbps (K28.5 PATTERN, 933MHz INPUT FILTER) 120 4000 MASKING TIME (s) DEASSERT 100 80 60 ASSERT 40 MAX3945 toc15 140 RATE_SEL = 0, BW1 = 0, BW2 = 0 20 3000 DJ (ps) 160 25 MAX3945 toc14 5000 MAX3945 toc13 180 LOS THRESHOLD (mV) RXDE1 = 1, RXDE0 = 0 4 160 MAX3945 toc12 6 DEEMPHASIS LEVEL (dB) RXDE_EN = 0 RXDE1 = 1, RXDE0 = 1 LOS THRESHOLD (mVP-P) 1100 MAX3945 toc10 DIFFERENTIAL OUTPUT AMPLITUDE (mVP-P) 1200 Rx INPUT-BASED LOS THRESHOLD vs. DAC CODE (LOS1_EN = 1 AND LOS2_EN = 0) MAX3945 toc11 DIFFERENTIAL OUTPUT SIGNAL LEVEL vs. SET_CML DAC SETTING 15 2000 10 1000 20 5 0 0 0 10 20 30 40 50 60 0 70 20 40 60 80 100 200 0 120 400 600 800 1000 1200 SET_LOSTIMER[6:0] DAC CODE SIGNAL AMPLITUDE (mVP-P) DETERMINISTIC JITTER AT 10.32Gbps (PRBS7 PATTERN WITH 100 CIDs, RATE_SEL = 1) DETERMINISTIC JITTER vs. DATA RATE (INPUT = 100mVP-P) POWER-SUPPLY CURRENT vs. TEMPERATURE (SET_CML[7:0] = 91d) 20 7 DJ (ps) 6 5 4 15 DJ WITH 100mVP-P NOISE ON POWER SUPPLY 10 3 2 5 1 0 0 200 400 600 800 1000 INPUT SIGNAL AMPLITUDE (mVP-P) 1200 DJ WITH NO NOISE ON POWER SUPPLY 0 0 3 6 DATA RATE (Gbps) 9 80 MAX3945 toc18 8 K28.5 PATTERN, RATE_SEL = 1 POWER-SUPPLY CURRENT (mA) 25 MAX3945 toc16 9 MAX3945 toc17 SET_LOS[5:0] DAC CODE 10 DJ (ps) MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier 70 60 50 LOS2_EN = 0 AND LOS1_EN = 1 40 LOS2_EN = 1 AND LOS1_EN = 0 30 20 12 -40 -20 0 20 40 60 TEMPERATURE (C) 8 _______________________________________________________________________________________ 80 100 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier -20 -30 -10 SCC11 (dB) SDD22 (dB) -10 -20 -30 -40 10 100 -20 -30 -40 -40 0 FREQUENCY (GHz) 1 10 100 10 1 FREQUENCY (GHz) OUTPUT COMMON-MODE RETURN GAIN (SCC22) (INPUT POWER OF 0dBm, ENABLED) MAX3945 toc22 0 -10 TRANSIENT RESPONSE (10.3Gbps, 10 ONES 10 ZEROS PATTERN, SET_CML[7:0] = 92d) 0.25 0.20 0.15 0.10 A = 1.39dB, RXDE1 = 0, RXDE0 = 0 B = 2.12dB, RXDE1 = 0, RXDE0 = 1 C = 3.27dB, RXDE1 = 1, RXDE0 = 0 D = 4.37dB, RXDE1 = 1, RXDE0 = 1 0.05 0 -20 -0.05 D C -0.10 -30 100 FREQUENCY (GHz) MAX3945 toc23 1 0 SCC22 (dB) B A -0.15 -0.20 -0.25 -40 1 10 0 100 200 400 600 800 1000 FREQUENCY (GHz) TIME (ps) ELECTRICAL EYE DIAGRAM AFTER 6in OF FR4 AND 72in OF CABLE WITH NO DEEMPHASIS (11.3Gbps K28.5, RATE_SEL = 1, SET_CML[7:0] = 160d, RXDE_EN = 0) ELECTRICAL EYE DIAGRAM AFTER 6in OF FR4 AND 72in OF CABLE WITH DEEMPHASIS (11.3Gbps K28.5, RATE_SEL = 1, SET_CML[7:0] = 160d, RXDE_EN = 1, RXDE0 = 1, RXDE1 = 1) MAX3945 toc24 MAX3945 toc25 80mV/div 100mV/div SDD11 (dB) -10 0 MAX3945 toc20 0 MAX3945 toc19 0 INPUT COMMON-MODE RETURN GAIN (SCC11) (INPUT POWER OF 0dBm, ENABLED) OUTPUT RETURN GAIN (SDD22) (INPUT POWER OF 0dBm, ENABLED) MAX3945 toc21 INPUT RETURN GAIN (SDD11) (INPUT POWER OF 0dBm, ENABLED) 20ps/div 20ps/div _______________________________________________________________________________________ 9 MAX3945 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier CSEL SDA SCL TOP VIEW RPMIN 12 11 10 9 VCCR 13 8 VCCR RIN- 14 7 ROUT- 6 ROUT+ 5 VCCR MAX3945 RIN+ 15 *EP CAZ 1 2 3 4 LOS + VEE VCCR 16 VEE MAX3945 Pin Configuration THIN QFN (3mm x 3mm) *THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Pin Description PIN NAME FUNCTION 1 CAZ Offset-Correction Loop Capacitor. A capacitor connected between this pin and the adjacent VEE pin sets the time constant of the offset-correction loop. The offset correction can be disabled through the digital interface by setting bit AZ_EN = 0 and by connecting this pin to ground. 2, 3 VEE Ground for Limiting Amplifier 4 LOS Loss-of-Signal Output. This output is an open-drain output. LOS is asserted when the level of the input signal drops below the preset threshold set by SET_LOS[5:0]. LOS is deasserted when the signal level is above the threshold. The polarity of the LOS output can be inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting LOS1_EN = 0 and LOS2_EN = 0. See Table 8. 5, 8, 13, 16 VCCR Power Supply. Provides supply voltage to the limiting amplifier. All pins must be connected to the supply voltage. 6 ROUT+ Noninverted Output, CML. Back terminated for 50I load. 7 ROUT- Inverted Output, CML. Back terminated for 50I load. 9 SCL Serial-Clock Input, TTL/CMOS. This pin has a 75kI internal pulldown. 10 SDA Serial-Data Bidirectional I/O. TTL/CMOS input and open-drain output. This pin has a 75kI internal pullup, but it requires an external 4.7kI pullup resistor to meet the 3-wire digital timing specification. (Data line collision protection is implemented.) 11 CSEL Chip-Select Input, TTL/CMOS. Internally pulled down by a 75kI resistor. CSEL = 1 starts an SPI cycle, while CSEL = 0 ends the SPI cycle and resets the control state machine. 12 RPMIN 14 RIN- Inverted Data Input, CML, with 50I Termination 15 RIN+ Noninverted Data Input, CML, with 50I Termination -- EP High-Impedance Receive Power-Monitor Input. Connect to ground when not used. Exposed Pad. Must be soldered to circuit ground. 10 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier bandwidth for a given data rate. Table 1 summarizes the RATE_SEL, BW1, and BW0 control bit functions. The high data-rate mode (RATE_SEL = 1) is recommended for operation up to 11.3Gbps. The MAX3945 is designed to operate from 1.0625Gbps to 11.3Gbps. It consists of a dual-path limiter, offsetcorrection circuitry, CML output stage, and LOS circuitry. The characteristics of the MAX3945 can be controlled through the on-chip 3-wire interface. The registers that control the part's functionality are RXCTRL1, RXCTRL2, RXSTAT, SET_CML, SET_LOS, MODECTRL, and SET_ LOSTIMER. The MAX3945 provides integrated DACs to allow the use of low-cost controller ICs. Figure 1 shows simplified input and output structures. The polarity of ROUT+/ROUT- relative to RIN+/RIN- is programmed by the RX_POL bit, as shown in Table 2. Offset-Correction Circuitry The offset-correction circuitry is provided to remove PWD caused by intrinsic offset voltages within the differential amplifier stages. An external 0.1FF capacitor connected between the CAZ pin and ground sets the offset-correction loop cutoff frequency to approximately 2kHz when RATE_SEL = 0 and to approximately 0.7kHz when RATE_SEL = 1. The offset-correction loop can be disabled using the AZ_EN bit, as shown in Table 3. Dual-Path Limiter The limiting amplifier features a low data-rate path (1.0625Gbps to 4.25Gbps) and a high data-rate path (up to 11.3Gbps), allowing for overall system optimization. Figure 2 shows the functional diagram. Data path selection is controlled by the RATE_SEL bit. The low data-rate path further features a programmable filter that provides optimization for 1.0625Gbps, 1.25Gbps, 2.125Gbps, and 4.25Gbps operation. It is important to tailor the bandwidth of the first stages to get the best receive sensitivity and to reduce the maximum receive CML Output Stage CML Output Enable and Squelch The CML output stage is optimized for differential 100I loads. The output stage is controlled by a combination of the RX_EN and SQ_EN bits and the internal LOS status. See Table 4. Table 1. Rate Select and Bandwidth Control RXCTRL1[3:1] OPERATION MODE DESCRIPTION BW1 BW0 RATE_SEL DATA RATE (Gbps) FILTER BANDWIDTH (MHz) RISE/FALL TIME (ps) 0 0 0 1.0625 to 1.25 1000 52 0 1 0 2.125 2100 52 1 0 0 2.125 2500 52 1 1 0 4.25 3000 52 X X 1 11.3 9000 26 Table 2. Signal Polarity Control RX_POL Table 3. Offset-Correction Enable/Disable Control OPERATION MODE DESCRIPTION 0 Inversed polarity of the differential signal path 1 Normal polarity of the differential signal path AZ_EN OPERATION MODE DESCRIPTION 0 Autozero loop is disabled 1 Autozero loop is enabled Table 4. CML Output Stage Operation Modes RX_EN SQ_EN LOS STATUS 0 X X CML output disabled OPERATION MODE DESCRIPTION 1 0 X CML output enabled 1 1 0 CML output enabled 1 1 1 CML output disabled ______________________________________________________________________________________ 11 MAX3945 Detailed Description MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier VCCR VCCR DEEMPHASIS CONTROL 50 50 ROUT+ RIN+ ROUT50 VCCR - 1V 50 RIN- VCCD VEER VEER VCCD 75k LOS SDA 376 CLAMP SCL, CSEL 75k VEET VEER VEER VCCR 2k 2k COMPARATOR RPMIN 2pF DAC Figure 1. Simplified Input/Output Structures 12 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier CAZ VCCR ROUT MAX3945 ROUT ROUT+ DIGITAL OFFSET CORRECTION AZ_EN VCCR - 1V RIN ROUTRXDE1 RXDE0 LPF 4G DEEMPHASIS 1 1 RIN 0 RIN+ 10G RINBW1 BW0 0 MX RX_POL RATE_SEL LOSS OF SIGNAL RX_EN SQ_EN OUTPUT CTRL LOGIC RPMIN LOS VCCR LOS_POL RPULL SDA 3-WIRE INTERFACE SCL CSEL RPULL LOS2/1_EN CONTROL LOGIC INTERNAL REGISTER 6b DAC SET_LOS 7b DAC SET_LOSTIMER 8b DAC SET_CML RPULL VEE Figure 2. Functional Diagram CML Output Deemphasis The CML output stage is optimized for differential 100I transmission lines on a standard FR4 board. The RXDE1 and RXDE0 bits add programmable analog output deemphasis to compensate for FR4 board losses and SFP connector losses. Table 5 describes the deemphasis control settings. Programmable CML Output Amplitude The 8-bit SET_CML register controls the amplitude of the CML output stage. The maximum programmable output level depends on the operational mode of the MAX3945. These output levels (which assume an ideal 100I differential load) and their corresponding control bits are described in Table 6. Table 7 shows the output DAC resolution dependency. ______________________________________________________________________________________ 13 MAX3945 VCCR MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Table 5. Output Signal Deemphasis Control RXCTRL2[1] RXCTRL1[7:6] OPERATION MODE DESCRIPTION DEEMPHASIS (dB) RXDE_EN RXDE1 RXDE0 MODE 0 X X Deemphasis block is disabled 1 0 0 Deemphasis block is enabled Level 1 0.3 1 0 1 Deemphasis block is enabled Level 2 1.1 1 1 0 Deemphasis block is enabled Level 3 2.1 1 1 1 Deemphasis block is enabled Level 4 4.3 0 Table 6. CML Output Amplitude Range (Typical) RXCTRL1[7:6] OUTPUT AMPLITUDE (mVP-P) RXCTRL1[1] RXCTRL2[1] RATE_SEL RXDE_EN 0 X X X Low data-rate path 400 to 1192 1 0 X X High data-rate path 400 to 1147 1 1 0 0 High data-rate path with deemphasis 400 to 1041 1 1 0 1 High data-rate path with deemphasis 400 to 987 1 1 1 0 High data-rate path with deemphasis 400 to 908 1 1 1 1 High data-rate path with deemphasis 400 to 828 MODE RESOLUTION (mVP-P) RXDE1 RXDE0 MODE Table 7. CML Output DAC Resolution (Typical) RXCTRL1[1] RXCTRL2[1] RATE_SEL RXDE_EN RXDE1 RXCTRL1[7:6] RXDE0 0 X X X Low data-rate path 4.5 1 0 X X High data-rate path 4.5 1 1 0 0 High data-rate path with deemphasis 4.1 1 1 0 1 High data-rate path with deemphasis 3.9 1 1 1 0 High data-rate path with deemphasis 3.6 1 1 1 1 High data-rate path with deemphasis 3.3 14 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier LOS2_EN LOS1_EN 0 0 LOS circuitry is disabled and powered down OPERATION MODE DESCRIPTION X 1 LOS circuitry is enabled and Rx input amplitude is detected 1 0 LOS circuitry is enabled and RPMIN input amplitude is detected LOS Circuitry The LOS circuitry has two operational modes controlled by the LOS1_EN and LOS2_EN bits (see Table 8). In the first mode, the LOS block detects the differential amplitude of the input signal and compares it against a preset threshold controlled by the 6-bit SET_LOS register. In the second mode, the LOS block compares the voltage at the RPMIN pin to a preset threshold also controlled by the 6-bit SET_LOS register. The second mode enables low-power LOS detection based on average photodiode current. 50mV/div 2mV/div 400s/div Figure 3. LOS Response to a Short Burst of Input Signal The LOS assert threshold is approximately 1.5mVP-P x SET_LOS[5:0]. The LOS deassert level is approximately 1.6 times the assert level to avoid LOS chatter. LOS polarity, squelch, and LOS masking time are unaffected by the selection of LOS1_EN or LOS2_EN. Programmable LOS Output Masking Time This feature masks false input signals that can occur after a loss-of-light event in a fiber optic link. These false input signals, caused by some transimpedance amplifier implementations, can corrupt the LOS output and cause system-level link diagnostic errors. 50mV/div 2mV/div 400s/div Figure 4. LOS Response to a Short Burst of Input Signal (Any changes in LOS are masked until the end of the LOS masking period.) The LOS output masking time can be programmed from 0 to 4500Fs in 35Fs steps using the 7-bit SET_LOSTIMER[6:0] register. The output mask timer is initiated on the first transition of the LOS signal and prevents any further changes in the LOS output signal until the end of the programmed LOS timing period. The LOS output masking time should be carefully chosen to extend beyond any expected input glitch. Figure 3 shows the LOS signal changing after approximately 800Fs to a change in the input signal where the LOS output masking time function is not used. Figure 4 shows masking of the LOS signal by the LOS output masking time function to a change in the input signal. ______________________________________________________________________________________ 15 MAX3945 Table 8. LOS Control MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Table 9. Digital Communication Word Structure BIT 15 14 13 12 11 10 9 Register Address 8 7 6 RWN 5 4 3 2 1 0 Data that is written or read. Table 10. Register Descriptions and Addresses ADDRESS NAME H0x00 RXCTRL1 Receiver Control Register 1 FUNCTION H0x01 RXCTRL2 Receiver Control Register 2 H0x02 RXSTAT H0x03 SET_CML CML Output Level Setting Register H0x04 SET_LOS LOS Threshold Assert Level Setting Register Receiver Status Register H0x0E MODECTRL H0x12 SET_LOSTIMER General Control Register LOS Timer Setting Register 3-Wire Digital Communication General The MAX3945 implements a proprietary 3-wire digital interface. An external controller generates the clock. The 3-wire interface consists of an SDA bidirectional data line, an SCL clock signal input, and a CSEL chip-select input (active high). The external master initiates a data transfer by asserting the CSEL pin. The master starts to generate a clock signal after the CSEL has been set to 1. All data transfers are most significant bit (MSB) first. Protocol Each operation consists of 16-bit transfers (15-bit address/data, 1-bit RWN). The bus master generates 16 clock cycles to SCL. All operations transfer 8 bits to the MAX3945. The RWN bit determines if the cycle is read or write. See Table 9. Register Addresses The MAX3945 contains seven registers available for programming. Table 10 shows the registers and addresses. Write Mode (RWN = 0) The master generates 16 total clock cycles at SCL. The master outputs a total of 16 bits (MSB first) to the SDA line at falling edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing, and Table 11 defines the various timing parameters. Read Mode (RWN = 1) The master generates 16 total clock cycles at SCL. The master outputs a total of 8 bits (MSB first) to the SDA line at falling edge of the clock. The SDA line is released after the RWN bit has been transmitted. The slave outputs 8 bits of data (MSB first) at rising edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing. Mode Control Normal mode allows read-only instruction for all registers except MODECTRL. Normal mode is the default mode. Setup mode allows the master to write unrestricted data into any register except the RXSTAT register. To enter setup mode, the MODECTRL register (address = H0x0E) must be set to H0x12. After the MODECTRL register has been set to H0x12, the next operation is unrestricted. The setup mode is automatically exited after the next operation is finished. This sequence must be repeated if further unrestricted settings are necessary. 16 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier MAX3945 WRITE MODE CSEL tL tT tCH tCL SCL 0 1 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 RWN D7 D6 10 11 12 13 14 15 tDS SDA A6 A5 D5 D4 D3 D2 D1 D0 tDH READ MODE CSEL tL tT tCH tCL SCL 0 1 2 3 4 5 6 7 8 9 tDS SDA A6 A5 10 11 12 13 14 15 tD A4 A3 A2 A1 A0 RWN D7 D6 D5 D4 D3 D2 D1 D0 tDH Figure 5. Timing for the 3-Wire Digital Interface Table 11. Interface Timing Parameters SYMBOL DEFINITION tL CSEL leading time before the first SCL edge tCH SCL pulse-width high tCL SCL pulse-width low tD SCL rise to SDA propagation time tDS SDA setup time tDH SDA hold time tT CSEL trailing time after last SCL edge Register Descriptions Receiver Control Register 1 (RXCTRL1) Bit # Name Default Value 7 6 5 4 3 2 1 0 RXDE1 RXDE0 X* SOFTRES BW1 BW0 RATE_SEL X* 0 0 1 0 1 1 1 1 ADDRESS H0x00 *Do not change default setting. Bits 7 and 6: RXDE[1:0]. These 2 bits are used to control deemphasis of the output waveform. See Table 5 for the bit settings and corresponding deemphasis levels. Bit 4: SOFTRES. When this bit is set to 1 during a 3-wire interface write operation, all registers are set to the default state when CSEL goes low. Bits 3 and 2: BW[1:0]. When RATE_SEL = 0, these 2 bits control the bandwidth of the limiting amplifier. See Table 1 for the settings and corresponding filter selection. Bit 1: RATE_SEL. RATE_SEL selects between the low bandwidth data path (1.0625Gbps to 4.25Gbps) and the high bandwidth data path (4.25Gbps to 11.3Gbps). When RATE_SEL is set to 1, the high bandwidth path is chosen. When RATE_SEL is set to 0, the low bandwidth path is chosen. ______________________________________________________________________________________ 17 MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Receiver Control Register 2 (RXCTRL2) Bit # Name Default Value 7 6 5 4 3 2 1 0 LOS2_EN LOS1_EN LOS_POL RX_POL SQ_EN RX_EN RXDE_EN AZ_EN 0 1 1 1 0 1 0 1 ADDRESS H0x01 Bit 7: LOS2_EN. Enables or disables the RSSI monitor-based LOS circuitry, in combination with the LOS1_EN bit. The below table shows when the RSSI monitor-based LOS is disabled and enabled. LOS2_EN LOS1_EN RX_EN 0 0 X Disabled and powered down Rx INPUT-BASED LOS Disabled and powered down RSSI MONITOR-BASED LOS 0 1 1 Enabled Disabled and powered down X 1 0 Disabled and powered down Disabled and powered down 1 1 1 Enabled Disabled and powered down 1 0 0 Disabled and powered down Enabled 1 0 1 Disabled and powered down Enabled Bit 6: LOS1_EN. Controls the Rx input-based LOS circuitry. When RX_EN is set to 0, the LOS detector is also disabled. 0 = disabled 1 = enabled Bit 5: LOS_POL. Controls the polarity of the LOS pin. 0 = inverse 1 = normal Bit 4: RX_POL. Controls the polarity of the CML output. 0 = inverse 1 = normal Bit 3: SQ_EN. When SQ_EN = 1, the CML output is squelched when LOS is asserted. 0 = disabled 1 = enabled Bit 2: RX_EN. Enables or disables the receive circuitry. 0 = disabled 1 = enabled Bit 1: RXDE_EN. Enables or disables the deemphasis on the CML output. 0 = disabled 1 = enabled Bit 0: AZ_EN. Enables or disables the autozero circuitry. 0 = disabled 1 = enabled 18 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Bit # 7 6 5 4 3 2 1 (STICKY) 0 (STICKY) Name X X X X X X POR_2d LOS_2d Default Value X X X X X X X X ADDRESS H0x02 Bit 1: POR_2d. When the VCC supply voltage is below 2.3V, the POR circuitry sets POR_2d high. When the supply voltage is above 2.75V, the POR circuitry deasserts, but the POR_2d bit remains high until it is read. Bit 0: LOS_2d. Copy of the LOS status. This is a sticky bit, which means that it is cleared on a read. The first 0-to-1 transition is latched until the bit is read by the master or POR occurs. CML Output Level Setting Register (SET_CML) Bit # Name Default Value 7 6 5 4 3 2 1 0 SET_CML[7] SET_CML[0] SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1] (MSB) (LSB) 0 1 0 1 1 1 0 ADDRESS H0x03 0 Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set up to 255 for maximum CML output amplitude. See Table 13 for equations to determine CML output level vs. SET_CML. LOS Threshold Assert Level Setting Register (SET_LOS) Bit # 7 6 5 4 3 2 1 0 ADDRESS Name X X SET_LOS[5] (MSB) SET_LOS[4] SET_LOS[3] SET_LOS[2] SET_LOS[1] SET_LOS[0] (LSB) H0x04 Default Value X X 0 0 1 1 0 0 Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code for both the Rx input-based LOS and the RSSI monitor-based LOS. ______________________________________________________________________________________ 19 MAX3945 Receiver Status Register (RXSTAT) MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier General Control Register (MODECTRL) Bit # Name 7 6 MODECTRL[7] Default Value (MSB) 5 4 3 2 1 0 MODECTRL[6] MODECTRL[5] MODECTRL[4] MODECTRL[3] MODECTRL[2] MODECTRL[1] 0 0 0 0 0 0 0 ADDRESS MODECTRL[0] (LSB) H0x0E 0 Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation. LOS Timer Setting Register (SET_LOSTIMER) Bit # 7 6 Name X LOSTIMER[6] 5 4 3 2 1 SET_ SET_ SET_ SET_ SET_ LOSTIMER[5] LOSTIMER[4] LOSTIMER[3] LOSTIMER[2] LOSTIMER[1] 0 0 0 0 0 SET_ (MSB) Default Value X 0 0 ADDRESS SET_ LOSTIMER[0] (LSB) H0x12 0 Bits 6 to 0: SET_LOSTIMER[6:0]. The SET_LOSTIMER register is a 7-bit register that can be set from 0 to 127. See the Typical Operating Characteristics section for a typical timer period vs. DAC code. Table 12. Register Map REGISTER FUNCTION/ ADDRESS Receiver Control Register 1 Address = H0x00 REGISTER NAME RXCTRL1 NORMAL MODE SETUP MODE BIT NUMBER/ TYPE BIT NAME DEFAULT VALUE NOTES R RW 7 RXDE1 0 Rx deemphasis MSB control with RXDE_EN = 1 R RW 6 RXDE0 0 Rx deemphasis LSB control with RXDE_EN = 1 R RW 5 X 1 Must be set to 1 R RW 4 SOFTRES 0 Soft reset control bit R RW 3 BW1 1 R RW 2 BW0 1 Input bandwidth control with RATE_SEL = 0: 00: 1GHz 01: 2.1GHz 10: 2.5GHz 11: 3GHz R RW 1 RATE_SEL 1 Rate-select control 0: 1G/4G mode 1: fast mode R RW 0 X 1 Must be set to 1 20 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R Receiver Control Register 2 Address = H0x01 Receiver Status Register Address = H0x02 RXCTRL2 SETUP MODE RW BIT NUMBER/ TYPE 7 BIT NAME LOS2_EN DEFAULT VALUE NOTES 0 RSSI monitorbased LOS 0: disabled 1: enabled when LOS1_EN = 0 R RW 6 LOS1_EN 1 Rx input-based LOS 0: disabled 1: enabled R RW 5 LOS_POL 1 LOS polarity 0: inverse 1: normal R RW 4 RX_POL 1 Rx polarity 0: inverse 1: normal R RW 3 SQ_EN 0 Squelch 0: disabled 1: enabled R RW 2 RX_EN 1 Rx control 0: disabled 1: enabled R RW 1 RXDE_EN 0 Rx deemphasis 0: disabled 1: enabled R RW 0 AZ_EN 1 Rx autozero control 0: disabled 1: enabled R R 1 (sticky) POR_2d X POR -> VCC low limit violation R R 0 (sticky) LOS_2d X Copy of LOS status RXSTAT ______________________________________________________________________________________ 21 MAX3945 Table 12. Register Map (continued) MAX3945 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Table 12. Register Map (continued) REGISTER FUNCTION/ ADDRESS CML Output Level Setting Register Address = H0x03 LOS Threshold Assert Level Setting Register Address = H0x04 General Control Register Address = H0x0E LOS Timer Setting Register Address = H0x12 REGISTER NAME SET_CML SET_LOS MODECTRL SET_LOSTIMER NORMAL MODE SETUP MODE BIT NUMBER/ TYPE BIT NAME DEFAULT VALUE NOTES R RW 7 SET_CML[7] 0 MSB output level DAC R RW 6 SET_CML[6] 1 R RW 5 SET_CML[5] 0 R RW 4 SET_CML[4] 1 R RW 3 SET_CML[3] 1 R RW 2 SET_CML[2] 1 R RW 1 SET_CML[1] 0 R RW 0 SET_CML[0] 0 LSB output level DAC R RW 5 SET_LOS[5] 0 MSB LOS threshold DAC R RW 4 SET_LOS[4] 0 R RW 3 SET_LOS[3] 1 R RW 2 SET_LOS[2] 1 R RW 1 SET_LOS[1] 0 R RW 0 SET_LOS[0] 0 LSB LOS threshold DAC RW RW 7 MODECTRL[7] 0 MSB mode control RW RW 6 MODECTRL[6] 0 RW RW 5 MODECTRL[5] 0 RW RW 4 MODECTRL[4] 0 RW RW 3 MODECTRL[3] 0 RW RW 2 MODECTRL[2] 0 RW RW 1 MODECTRL[1] 0 RW RW 0 MODECTRL[0] 0 LSB mode control R RW 6 SET_LOSTIMER[6] 0 MSB LOS timer R RW 5 SET_LOSTIMER[5] 0 R RW 4 SET_LOSTIMER[4] 0 R RW 3 SET_LOSTIMER[3] 0 R RW 2 SET_LOSTIMER[2] 0 R RW 1 SET_LOSTIMER[1] 0 R RW 0 SET_LOSTIMER[0] 0 22 LSB LOS timer 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier Programming CML Output Levels See Tables 13 and 14. For each value of the bits RXDE1 and RXDE0 in Table 13, the value of deemphasis does vary with the SET_CML[7:0] setting. In Table 13, the values of deemphasis are given for the setting SET_CML[7:0] = 120d. The variation of deemphasis for other values of SET_CML[7:0] is shown in the Typical Operating Characteristics (see the Deemphasis Value vs. SET_CML DAC Setting (RATE_SEL = 1) graph). Note that even though RXDE_EN = 0, there is still some deemphasis for RATE_SEL = 1 for values of amplitude control below SET_CML[7:0] = 170d. Select the Coupling Capacitor For AC-coupling, the coupling capacitors CIN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input low frequency cutoff (fIN) is decreased: fIN = 1/[2G(50)(CIN)]. The recommended value of CIN and COUT is 0.1FF for the MAX3945. Select the Offset-Correction Capacitor The capacitor between CAZ and ground determines the time constant of the signal path DC-offset cancellation loop. A 0.1FF capacitor between CAZ and ground is recommended for the MAX3945. Applications Information Layout Considerations Use good, high-frequency layout techniques and multiple-layer boards with uninterrupted ground planes to minimize EMI and crosstalk. Exposed-Pad Package The exposed pad on the 16-pin TQFN provides a very low-thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3945 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information. Table 13. CML Output Amplitude Equations (Typical) RXCTRL1[1] RXCTRL2[1] RATE_SEL RXDE_EN RXDE1 RXCTRL1[7:6] RXDE0 0 X X X 0 1 0 X X 0.72 4.5mVP-P x SET_CML 1 1 0 0 1.17 -4mVP-P + 4.1mVP-P x SET_CML 1 1 0 1 1.89 -7mVP-P + 3.9mVP-P x SET_CML 1 1 1 0 2.48 -10mVP-P + 3.6mVP-P x SET_CML 1 1 1 1 3.86 -13mVP-P + 3.3mVP-P x SET_CML DEEMPHASIS (dB) (SET_CML[7:0] = 120d) EQUATION FOR (VROUT+ - VROUT-) 45mVP-P + 4.5mVP-P x SET_CML Table 14. SET_CML DAC Codes for 400mVP-P and 800mVP-P Output Levels RXCTRL1[1] RXCTRL2[1] RATE_SEL RXDE_EN RXDE1 RXCTRL1[7:6] RXDE0 400mVP-P SET_CML DAC CODE 800mVP-P 0 X X X 80 169 1 0 X X 91 181 1 1 0 0 98 194 1 1 0 1 106 208 1 1 1 0 115 225 1 1 1 1 126 245 ______________________________________________________________________________________ 23 MAX3945 Design Procedure 1.0625Gbps to 11.3Gbps, SFP+ Dual-Path Limiting Amplifier MAX3945 Typical Application Circuit SFP CONNECTOR SFP+ OPTICAL RECEIVER +3.3V SUPPLY FILTER HOST BOARD HOST FILTER VCC_RX 0.1F +3.3V 4.7k EP VEE VCCR LOS RIN+ ROUT+ 0.1F MAX3945 11.3Gbps RINIRPMIN 10G PIN FLEX ROSA SerDes CIN 0.1F CAZ ROUT- 0.1F COUT 0.1F ZDIFF = 100 RPMIN RRPMIN 2k 100pF SCL SDA CSEL 3-WIRE INTERFACE POWER-ON RESET 3-WIRE INTERFACE ADC SFP+ CONTROLLER I2C MODE_DEF2 (SDA) MODE_DEF1 (SCL) RATE SELECT Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 TQFN-EP T1633+5 21-0136 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.