TOSHIBA TC58256FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M x 8BITS) CMOS NAND E7PROM DESCRIPTION The TC58256 is a single 3.3-V 256-Mbit (276,648,128) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E?PROM) organized as 528 bytes X 32 pages X 2048 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes X 32 pages). The TC58256 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non- volatile memory data storage. FEATURES e Organization @ Power supply Memory cell array 528 X 64K X 8 Vcc = 3.3V10.3V Register 528 X 8 e Access time Page size 528 bytes Cell array-register 25 us max Block size (16K + 512) bytes Serial Read cycle 50 ns min @ Modes @ Operating current Read, Reset, Auto Page Program Read (50-ns cycle) 10 mA typ. Auto Block Erase, Status Read Program (avg.) 10 mA typ. @ Mode control Erase (avg.) 10 mA typ. Serial input/output Standby 100 vA Command control e Packages TC58256FT : TSOP I 48-P-1220-0.50 (Weight: 0.53 typ.) PIN ASSIGNMENT (TOP VIEW) PIN NAMES Ned 2 O ie ENc VO1 tos | VO Port q a rE . Ned 2 ie CNC cE Chip Enable Ncqg 5 44 pl/08 WE Write Enable GND 6 43 1/07 R/BY 7 42 pl/O6 RE Read Enable Re g 10 pie CLE Command Latch Enable NcCq 10 39 HNC ALE Address Latch Enable NCq 11 3g BNC Vec4q 12 37 p cc WP Write Protect Vest ia a R/B Ready/Busy NCQ 15 34 BNC GND Ground input CLE 16 33 ANC ALE 17 32 plV/O4 Vec Power Supply WE 18 31 pl/O3 WPd 19 390 H/O2 Vss Ground NCq 20 29 HI/O1 NCQ 21 28 HNC NCQ 22 27 ANC NCq 23 26 HNC Ncq 24 25 BNC 961001EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-02-24 1/33BLOCK DIAGRAM Voc Vcc GND | (ae | 01 O<> VO K Address register | > Column buffer to i control Ke 7 > Column decoder 08 O>} ircurt Command register YZ, Data register 4 ! > Sense amp ae | Vv cE O> R b : WiRd|: CLE O> a f|jo e/: ALE O>| Logic Control d y $ Memory WE c control circuit c d d g cell array __ $s : RE O> 8 6|o |: WP O> gs |: R/B O ABSOLUTE MAXIMUM RATINGS SYMBOL ITEM RATING UNIT Vec Power Supply Voltage -0.6 to 4.6 V Vin Input Voltage -0.6 to 4.6 V Vuio Input /Output Voltage -0.6 V~V.- + 0.3 V(=4.6 V) V Pp Power Dissipation 0.3 Ww TSOLDER Soldering Temperature (10s) 260 C TstG Storage Temperature -55 to 150 C Topr Operating Temperature -40 to 85 C CAPACITANCE *(Ta = 25C, f = 1 MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT Cin Input Vin = OV - 10 pF Cout Output Vout = OV - 10 pF * This parameter is periodically sampled and is not tested for every device. 2000-02-24 2/33TOSHIBA TC58256FTI VALID BLOcks !1) SYMBOL PARAMETER MIN TYP. MAX UNIT Nye Number of Valid Blocks 2008 - 2048 Blocks (1) The TC58256 occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT Vec Power Supply Voltage 3.0 3.3 3.6 V Vin High Level Input Voltage 2.0 - Vcc + 0.3 V ViL Low Level Input Voltage -0.3* - 0.8 Vv * 2V (pulse width = 20 ns) DC CHARACTERISTICS (Ta = -40 to 85C, Vcc = 3.3V t 0.3V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT lie Input Leakage Current Vin = OV to Vcc - - +10 vA ILo Output Leakage Current Vout = 0.4V to Vec - - +10 vA leco1 Operating Current (Serial Read) CE = Vi, lout = OMA, teycle = 50 ns - 10 30 mA leco3 Operating Current (Command Input) teycle = 50 ns - 10 30 mA lccoa Operating Current (Data Input) teycle = 50 ns - 10 30 mA lecos Operating Current (Address Input) teycle = 50 ns - 10 30 mA leco7 Programming Current - - 10 30 mA Iccog Erasing Current - - 10 30 mA lecs1 Standby Current CE = Vin - - 1 mA lecs2 Standby Current CE = Vcc - 0.2V - - 100 pA Vou High Level Output Voltage lon = -400 vA 2.4 - - Vv VoL Low Level Output Voltage lol = 2.1MA - - 0.4 V lo. (R/B) | Output Current of R/B Pin VoL = 0.4V - 8 - mA 2000-02-24 3/33TOSHIBA TC58256FTI AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C, Vcc = 3.3V + 0.3V) SYMBOL PARAMETER MIN MAX UNIT NOTES teLs CLE Setup Time 0 - ns teLH CLE Hold Time 10 - ns tes CE Setup Time 0 - ns tcH CE Hold Time 10 - ns twp Write Pulse Width 25 - ns tats ALE Setup Time 0 - ns taLH ALE Hold Time 10 - ns tps Data Setup Time 20 - ns toy Data Hold Time 10 - ns twe Write Cycle Time 50 - ns twH WE-High Hold Time 15 - ns tww WP High to WE Low 100 - ns tre Ready-to-RE Falling Edge 20 - ns trp Read Pulse Width 35 - ns tre Read Cycle Time 50 - ns trEA RE Access Time (Serial Data Access) - 35 ns tceH CE-High Time for Last Address in Serial Read Cycle 100 - ns (2) treaip | RE Access Time (ID Read) - 35 ns tou Data Output Hold Time 10 - ns truz RE-High-to-Output-High Impedance - 30 ns tcHz CE-High-to-Output-High Impedance - 20 ns trEH RE-High Hold Time 15 - ns tir Output-High-Impedance-to-RE Rising Edge 0 - ns trsto RE Access Time (Status Read) - 35 ns testo CE Access Time (Status Read) - 45 ns trHw RE High to WE Low 0 - ns twuc WE High to CE Low 30 - ns twur WE High to RE Low 30 - ns tari ALE Low to RE Low (ID Read) 100 - ns tcr CE Low to RE Low (ID Read) 100 - ns tr Memory Cell Array to Starting Address - 25 ps twe WE High to Busy - 200 ns tar2 ALE Low to RE Low (Read Cycle) 50 - ns tre RE Last Clock Rising Edge to Busy (in Sequential Read) - 200 ns tcry CE High to Ready (When interrupted by CE in Read Mode) - 600 + tr (R/B) ns (1) trst Device Reset Time (Read/Program/Erase) - 6/10/500 ps AC TEST CONDITIONS Input level : 24V/0.4V Input pulse rise and fall time : 8ns Input comparison level >: 15V/1.5V Output data comparison level >: 15V/1.5V Output load : ITTL+Cyz (100 pF) 2000-02-24 4/33TOSHIBA TC58256FTI Note :(1) CE High to Ready time depends on the pull-up resistor tied to the R/B pin. (Refer to Application Note(7) toward the end of this document.) (2) Sequentral Read is terminated when tcry is grater than or equal to 100ns. If the RE to CE delay is less than 30ns, R/B signal stays Ready. tceyH 2 100 ns < > * * Vin or Vit fa RE \ / \ / \ 2 : 0 to 30ns Busy signal is not output. 525 526 527 R/B \ Busy PROGRAMMING AND ERASING CHARACTERISTICS (Ta = -40 to 85C, Vcc = 3.3V t 0.3V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tproG Average Programming Time 200 1000 YS N Number of Programming Cycles on Same Page 10 (1) tBERASE Block Erasing Time 3 5 ms P/E Number of Program/Erase Cycles 1x 105 (2) (1) Refer to Application Note 12 toward the end of this document. (2) Refer to Application Note 15 toward the end of this document. 2000-02-24 5/33TOSHIBA TC58256FTI TIMING DIAGRAMS Latch Timing Diagram for Command/Address /Data [ CLE ALE CE E Setup Time Hold Time WE / _ tps | toy _ 1/01 to 8 > Vin or Vit Command Input Cycle Timing Diagram CLE teLs teLH a tcH Y; cE T _iwe_ ae taLs ms taLH au 7/p y T tps tby 1/01 to8 y V; : Vin or ViL 2000-02-24 6/33TOSHIBA TC58256FTI Address Input Cycle Timing Diagram CLE ALE 1/01 to 8 teLs Ls twe twe Y R Y A tes tWH tWH twp R taLs v twp A Y twp R Y Ph, taALH CLE ALE /01 p tps tps tps <-| tDH tbH <> -| tDH AO to 7 A9 to 16 A17 to 24 Vv > Vin or Vit Data Input Cycle Timing Diagram tcLH | tcH | q _ tats _ twe tWH 4 { mH tps tou tps tou tps tou Din Din1 Diy 527 to 8 > Vin or Vit 2000-02-24 7/33TOSHIBA TC58256FTI Serial Read Cycle Timing Diagram tre 4 < - a +> ] VN TREH trp . > trp trp RE \ \ t tcuz tou tou <> TREA <> TREA <> TREA tou a trHz - trHz > <<. 1/01 to 8 ut trR +> VN R/B Status Read Cycle Timing Diagram teLs CLE ~< > teLs \ >{< tCLH tes \ TD VY t twp <> testo WE \ f + t \ F~._ twice touz ~ tWHR x ton RE tir \ { tos jae > <> <> oH <> trHz *RSTO Status 1/01 to8 70H* Ld output RB / * 70H represents the hexadecimal number 70. > Vin or Vit 2000-02-24 8/33TOSHIBA TC58256FTI Read Cycle (1) Timing Diagram CLE teLy teLs tes tcH ce D iy OU OU ALE / tar2 tery _ nL <8, fRR tre TaLH <> <> >t trea Pour} _{ Dour {nour ow N N+1 N+2 Column address N* tre R/B N y / > Vin or Vit Read Cycle (1) Timing Diagram: When Interrupted by CE CLE tcLy tes I} tes tcH eIiIA BA DB twe we a, \_/ L, \ i. tr ~ tcHz fais. taLH_ y tar2 a <> <> OH <P] ALE t Yj. t <_> lws_ tre t taLH <_* <> je RO_ WY tos | ton tos |tpy 22S }toy tos] toy = eco S <> ~< tREA trHz Dout Dout Dout N N+1 N+2 1 Column address N* R/B N y * Read operation using 00H command N: 0 to 255 > Vin or Vit 2000-02-24 9/33TOSHIBA TC58256FTI Read Cycle (2) Timing Diagram CLE tas teu ei FD ADA we PLS \ fp Ly : tats _ twa . AR 4 SS > > _ taLH ~ ALE _ ] Lim taLH RO RE \ tps t tos t ~_/T\VSI\VS DH DH <> tRR >1<-trEA 01 A0 to VW Ad to WAT7 to\ (Dour) D D to 8 O1H Aq Al6 ara) OUT OUT Dout Column address 256+M 256+M+1 927 N* RB t * Read Operating using 01H command N:0 to 255 > Vin or Vit Read Cycle (3) Timing Diagram CLE tas teu tes tcH JI ey Tb Dd a WWS tas tws tar2 _ TALH _ wt ZZ tALH > tre RE \ ee Y R bet tbH tbH <> tre >< tREA 1/01 AO to AY to A17 to to 8 50H a7 J Al6 x A24_) (Pous}-fDou7 Column address 512+M 512+M+1 527 N* R/B \ y * Read Operating using 01H command N:0 to 15 > Vin or Vit 2000-02-24 10/33TOSHIBA TC58256FTI Sequential Read (1) Timing Diagram CLE 2 2 2 . \ 2 2 2 2 22 2 we ONE V0! X= XR nancy HEHE RH) Ha) | ag |~ Column Page tr < tr ~ address address N M R/B \ J \ Page M Page M+1 access access > Vin or Vit Sequential Read (2) Timing Diagram \ 2 2 2 2 2 2 11 7K XE E a Tt {0 )-{1) {2 a) 256 256 256 < Column Page : + + tr address adr ress N N+1 N+2 N R/B \ J \ Page M Page M +1 access access > Vin or Vit 2000-02-24 11/33TOSHIBA TC58256FTI Sequential Read (3) Timing Diagram CLE / \ CE ALE 1/01 to 8 2 2 2 2 Yk 50H XY A0 toY AY to A17 to A7 Xx A16 A24 ) Column Page address address N M a2t Page M+ 1 access : Vin or ViL 2000-02-24 12/33TC58256FTI ZA \__ a > tproG << < Status output, twe Status output xxx <x KKK Status Read command 13/33 2000-02-24 / (a //m 7. i + AN Lal LA Z4 \_I KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK KKKKRK : Do not input data while data is being output. tBERASE Busy KKKKRK KKKKRK KKKKRK 4 : Do not input data while data is being output. TOSHIBA Auto-Program Operation Timing Diagram teLs tcH att nS PNT VINA DD 3 taLs ang <= aT tALH, | tcLH A < > teLs CLE ye > taALH ALE 80H 1/01 to 8 > Vin or Vit Auto Block Erase Timing Diagram \Z = + att wi YU > ALE to 8 Erase Start command Setup command : Vin or ViLTOSHIBA ID Read Operation Timing Diagram ter tari, ALE RE tps | +_/ <> ton 1/01 TREAID TREAID Address input Maker code Device code > Vin or Vit 2000-02-24 14/33TOSHIBA TC58256FTI PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode TCS8256F TI command into the internal command register. The command is latched Nc into the command register from the I/O port on the rising edge of the WE C4! a8 ENC NCY 2 47 4p signal while CLE is High. Ncq 3 46 HNC NC Address Latch Enable: ALE NCd aa bv08 The ALE signal is used to control loading of either address information GND & 6 asp V OG R/BO 7 42 fp or input data into the internal address/data register. REG 8 41 bWV/O5 Address information is latched on the rising edge of WE if ALE is High. ceEq 9 40 HNC Input data is latched if ALE is Low. Ncq 10 39 PNC __ NCq 11 38 BNC Chip Enable: CE VecG 12 37 BYcc , . . Vss4 13 36 BVss The device goes into a low-power Standby mode when CE goes High Ncq 14 35 ANC during a Read_operation. The CE signal is ignored when device is in NCY 15 34 PC Busy state (R/B = L), such as during a Program or Erase operation, and CLE4 ic 33 04 will not enter Standby mode even if the CE input goes High. The CE aed 18 31 bV/O3 signal must stay Low during the Read mode Busy state to ensure that wpd 19 390 b/02 memory array data is correctly transferred to the data register. Ncq 20 29 H ve. NCq 21 A Write Enable: WE NCA 22 27 FNC TT N The WE signal is used to control the acquisition of data from the YO jNcqg 24 25 ANC port. _ Figure 1. Pinout Read Enable: RE The RE signal controls serial data output. Data is available trp, after the falling edge of RE. The internal column address counter is also incremented (Address= Address + 1) on this falling edge. V/Q Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: R/B The R/B output signal is used to indicate the operating condition of the device. The R/B signal is in Busy state (R/B = L) during the Program, Erase and Read operations and will return to Ready state (R/B = H) after completion of the operation. The output buffer for this signal is an open drain. 2000-02-24 15/33TOSHIBA TC58256FTI Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy ------ tite or for other uses. ( et ! > 32pages = 1 block < 1 page = 528 bytes epee ! ! 1 block = 528 bytes X 32 pages = (16K + 512) bytes = 2048 block ! Capacity = 528 bytes X 32 pages X 2048 blocks An address is read in via the I/O port over a 8/0 three consecutive clock cycles, as shown in Table 1. | Figure 2. Schematic Cell Layout Table 1. Addressing 1/08 1/07 1/06 /O5 1/04 1/03 1/02 /01 AO to A7: Column address First cycle A7 A6 A5 A4 A3 A2 Al AO AQ to A24: Page address A14 to A24: Block address | Al Al Al4 Al A12 All Al A ( . ) Second cycle 6 3 0 9 {AQ to A13: NAND address in block Third cycle A24 A23 A22 A21 A20 A19 A18 Al7 *: A8 is automatically set to Low or High by a 00H command or a 01H command. Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE, WE, RE and WP signals, as shown in Table 2. Table 2. Logic Table CLE ALE CE WE RE WP Command Input H L L LA H * Data Input L L L LA H * Address Input L H L LA H * Serial Data Output L L L H YT * During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H Program, Erase Inhibit * * * * * L H: Vin, L: ViL, * Vinor Vit 2000-02-24 16/33TOSHIBA TC58256FTI Table 3. Command table (HEX) First Cycle Second Cycle Acceptable while Busy Serial Data Input 80 - Read Mode (1) 00 - Read Mode (2) 01 - Read Mode (3) 50 - Reset FF - O Auto Program 10 - Auto Block Erase 60 DO Status Read 70 - O ID Read 90 - HEX data bit assignment (Example) Serial data input: 80H ~ ~ ~ ~ Lilolojololololjo| VO8 7 6 5 a 3 2 WO' Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are not needed for sequential page Read operations. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE 1/01 TO 1/08 Power Output Select L L L H L Data output Active Output Deselect L L L H H High impedance Active Standby L L H H * High impedance Standby H: Vin L: Vit *: Vin or Vit 2000-02-24 17/33TOSHIBA TC58256FTI DEVICE OPERATION Read Mode (1) Read mode (1) is set when a "00H" command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. Re LINN R/B N Busy M om \ / vo {oo)-{){){_) 444-4) -------- - oo A data transfer operation from the cell array to the P register starts on the rising edge of WE in the third cycle M| 527 (after the address information has been latched). The device L__ 4 > will be in Busy state during this transfer period. The CE iw signal must stay Low after the third address input and Select page _, > during Busy state. N A Cell array After the transfer period the device returns to Ready _ a= w- state. Serial data can be output synchronously with the RE clock from the start pointer designated in the address input Figure 3. Read mode (1) operation cycle. Read _ Mode (2) ce [| \ e \A AFA we VU VU WW ALE i \ RE LIVI R/B N Busy M os \ / 0 CHO) 42-4) - -------- Start-address input M 236 | = ; The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer is to be set Select page \ after column address 256, use Read mode (2). N AB * aL. Cell array However, for a Sequential Read, output of the next page starts y : re ) from column address 0. Figure 4. Read mode (2) operation 2000-02-24 18/33TOSHIBA TC58256FTI Read Mode (3) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. CLE I \ e \A WDA UTA 4 \ 527 ~Y Figure 5. Read mode (3) operation > Addresses bits AO to A3 are used to set the start pointer for the redundant memory cells, while A4 to A7 are ignored. Once a "50H" command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address. (An "QOH" command is necessary to move the pointer back to the 0-to-511 main memory cell location.) 2000-02-24 19/33TOSHIBA TC58256FTI Sequential Read (1)(2)(3) This mode allows the sequential reading of pages without additional address input. oH) SS te KS te SS te GD Address input q___ Data output < Data output < > R/B Busy Busy Busy 0 527 (01H) (50H) 512 527 LF > Lt > T > > Sequential Read (1) Sequential Read (2) Sequential Read (3) Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal. ** Column address 527 on the last page 2000-02-24 20/33TOSHIBA TC58256FTI Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a "70H" command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT 1/01 Pass / Fail Pass: 0 Fail: 1 702 | Wot Used |e We ee ee ones on a 1/03 Not Used 0 1/04 Not Used 0 1/05 Not Used 0 1/06 Not Used 0 1/07 Ready / Busy Ready: 1 Busy: 0 1/08 Write Protect Protect: 0 Not Protected: 1 An application example with multiple devices is shown in Figure 6. CE, CE> CE3 CEy CEn 41 d d d d Device Device Device Device Device 1 2 3 N N+ 1 R/B \ Busy CEN \ / \ / RE \ / \ / 0 _-(7)-_{<)_{7mi) Q Status on Status on Device 1 Device N Figure 6. Status Read timing application example System Design Note: If the R/B pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2000-02-24 21/33TOSHIBA TC58256FTI Auto Page Program The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) Data input Program command Status Read command Data input command Address input 0 to 527 R/B \ / R/B automatically returns to Ready after completion of the operation. Data input Program Reading & verification 7 The data is transferred (programmed) from the register to the Selected selected page on the rising edge of WE following input of the page "10H" command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is Figure 7. Auto Page Program operation reached. Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command "DOH" which follows the Erase Setup command "60H". This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Pass E> fon) 60 { ) 70 Block address Erase Start Status Read input: 2 cycles command command R/B \ Busy | Fail 2000-02-24 22/33TOSHIBA TC58256FTI Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The address and data registers are set as follows after a Reset: - Address Register: All "0" - Data Register: All "1" - Operation Mode: Wait state The response to an "FFH" Reset command input during the various device operations is as follows: * When a Reset (FFH) command is input during programming C80 ) { 10 ) { FF )} { 00 ) NS NLS NS ; Register set Internal Vpp >: R/B trst (max 10 ys) | Figure 8. * When a Reset (FFH) command is input during erasing @ _@)- Internal erase of ~_L. . Register set . voltage +_: _ A 7 trst (max 500 ps) R/B Figure 9. When a Reset (FFH) command is input during a Read operation Go) CO RIB \ | trst (max 6 ps) Figure 10. * When a Status Read command (70H) is input after a Reset CGF) U7=EerowN |1/O status: Pass/Fail Pass _ Ready / Busy > Ready R/B \ | However, the following operation is prohibited. If the following operation is executed, correct resetting of the address and data register cannot be guaranteed. C | Co |/Ostatus: Ready/Busy > Busy R/B \ | Figure 11. + When two or more Reset commands are input in succession (1) (2) (3) SL, FF CFF) CFF) R/B \ | The second command is invalid, but the third CFF) command is Figure 12. 2000-02-24 23/33TOSHIBA TC58256FTI ID Read The TC58V64FT/DC contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE | \ <\_ ZZ Za. ALE [oY vant en eee TREAID +4 ID Read command Address Maker code Device code 00 A Vv For the specifications of the access times treaip, tcr and tar; refer to the AC Characteristics. Figure 13. ID Read timing Table 6. Code table 1/08 1/07 1/06 1/05 1/04 1/03 1/02 1/01 Hex Data Maker code 1 0 0 1 1 0 0 0 98H Device code 0 1 1 1 0 1 0 1 75H 2000-02-24 24/33TOSHIBA TC58256FTI APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (2) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (3) Pointer control for "00H", "01H" and "50H" The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of the pointer, and Figure 14 is a block diagram of their operations. 0 255 256 511 512 527 Table 7. Pointer Destination Read Mode | Command Pointer SY Seen SY oe eecceccsesttttin bhd..d (1) 00H 0 to 255 \ [ / (2) 01H 256 to 511 \ (3) 50H 512 to 527 00H > 01H > Pointer control 50H > Figure 14. Pointer control The pointer is set to region A by the "00H" command, to region B by the "01H" command, and to region C by the "50H" command. (Example) The "00H" command must be input to set the pointer back to region A when the pointer is pointing to region C. (anay 00H { 50H ) Address Start point Address Start point Address = Start point A area A area C area fone as __. OO So OF SO Address Start point Address Start point Address Start point C area C area A area 01H ~-" NN _/ Address Start point Address Start point B area A area To program region C only, set the start point to region C using the 50H command. {80H ) { ) 10H 50H S]*_,_JSESE TN Or "OOS " Address DIN J Programming region C only Start point C area (faoun 00 Co1H) (80H ) *(10H } Address DIN J Programming regions B and C Start point B area Figure 15. Example of How to Set the Pointer 2000-02-24 25/33TOSHIBA TC58256FTI (4) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Program Execution command "10H" or the Reset command "FFH". C20) Ee we LPLPLrui WY Address input R/B re Figure 16. If a command other than "10H" or "FFH" is input, the Program operation is not performed. { Xx } ) C80 ) { 10 ) Command Other Programming cannot be executed. than "10H" or "FFH" For this operation the "FFH" command is needed. (5) Status Read during a Read operation [A] ) Command Coo el we VS 2 RIB \ 3 [ : RE Address N Status Read Lh LI \l~ a command input Status Read Status output Figure 17. The device status can be read out by inputting the Status Read command "70H" in Read mode. Once the device has been set to Status Read mode by a "70H" command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command "00H" is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary . (6) Auto programming failure Fail nN rn /O C80 \_ C19) C70) C2 TO Address Data Address Data M input N input 10 \ \ If the programming result for page address M is Fail, do not try to program the M page to address N in another block. Because the previous input data has been lost, the same input sequence of 80H command, address and data is necessary. Figure 18. 2000-02-24 26/33TOSHIBA TC58256FTI (7) R/B: termination for the Ready/Busy pin (R/B) A pull-up resistor needs to be used for termination because the R/B buffer consists of an open drain circuit. V cc Ready | Vee R Devi _ 1. B evice + RB : usy 5, : r Vcc =3.3V Vss 1.5 8s - Ta=25C 15ns C_ = 100 pF ar Figure 19. t + P t, 1.0 4s 10 ns : f 0.5 ps 5 ns This data may vary from device to device. We recommend that you use this data as a l l reference when selecting a resistor value. 0 1kQ 2kQ 3kQ 4kQ R (8) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. (FF) Power on Reset Figure 20. (9) Power-on/off sequence: power-on/off. The following The WP signal is useful for protecting against data corruption at timing sequence is necessary: ) 3.0V ; t 2.8V )) Dont Ny care i CE, WE, RE : Mi : ViL Vit : Operation Vo =| uv A Figure 21. Power-on/off Sequence 2000-02-24 27/33TOSHIBA TC58256FTI (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE I I fan DIN Co) (10> Wp I t I R/B es tww 100 ns min Disable Programming wee LL fis DIN -+C20) (10) we L ; R/B es tww 100 ns min Enable Erasing WE I 1 fr DIN 3) (vo ) Wp el I RO tww 100 ns min Disable Erasing WE I I fu. DIN 7G) (bdo } R/B les tww 100 ns min 2000-02-24 28/33TOSHIBA TC58256FTI (11) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip. Read _ operation ST S\NAU a \ v0 { >{_){_ x 00H, 01H or 50H Address input R/B \ Internal read operation starts when WE goes High in the third cycle. Ignored Figure 22. Program operation wT ALE / \ yo {on}{_){_}{_{_)} {XX son | Address input Data input Ignored Figure 23. 2000-02-24 29/33TOSHIBA TC58256FTI (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 10 segments. Each segment can be programmed individually as follows: First programming Data Pattern 1 Second programming Tenth programming Data pattern 10 Data Result Data Pattern?) || wetter te tte ee neta seen een eee teen nese eter ee ree Data Pattern 10 Pattern 2 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1"). (13) Note regarding the RE signal The internal column address counter is incremented synchronously with the RE clock in Read mode. Therefore, once the device has been set to Read mode by a "00H", "01H" or "50H" command, the internal column address counter is incremented by the RE clock independently of the address input timing. If the RE clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array register) will occur and the device will enter Busy state. (Refer to Figure 25.) Address input _ 7 TE) OOD Figure 25. Hence the RE clock input must start after the address input. 2000-02-24 30/33TOSHIBA TC58256FTI (14) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: Check if the device has any bad blocks after device installation into the system. Do not try to access bad blocks. A bad block does not + BadBlock affect the performance of good blocks because it is isolated from the Bit line by the Select gate. The number of valid blocks is as follows: MIN TYP. MAX UNIT > Bad Block Valid (Good) Blocks 2008 - 2048 Block Figure 26. Figure 28 shows the flow for bad block testing (15) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase Block Replacement Page Programming Failure Status Read after Program Block Replacement Single Bit* | programming Failure | (1) Block Verify after Program Retry "4 30" (2) ECC e ECC: Error Correction Code Hamming Code etc. Example: 1-bit correction & 2-bit detection @ Block Replacement Program Error occurs When an error hoppens in Block A, try to reprogram the data into another (Block B) by Buffer \ memory \ Block A loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another > , Block B appropriate scheme). Figure 27. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). 2000-02-24 31/33TOSHIBA TC58256FTI BAD BLOCK TEST FLOW C : Checkerboard pattern Cc: Inverted checkerboard pattern Blank check : 1 Block Read (FFH) Test Start 32-Page Fail C- Patt Prog Pass Read (00H) Fail BNo. = BNo.+ 1}-\J Pass Block Fail No Erase Bad 2-Pag Fail C- Patt Prog Yes Pass Read (00H) Fail Pass Block Fail Erase No B No. = 2048 Yes [=< Test End Figure 28. 2000-02-24 32/33TOSHIBA TC58256FTI PACKAGE DIMENSIONS @ Plastic TSOP TSOP I 48 P12200.50 Unit: mm eo Oo 1 raf m48 oo 4 fr Oo Ca br =| O SS oa i A cu a N Cy iT OQ; ci a] r Cy Tr) 4 | iu i to =n TT =| 4 cy a wo on = t ail a Coy . |] om co i k}O cy 1} cy rr eet iT yy iT ca TT i 24 cH a 1 3 25 & 18.440.1 < . 6 1.00.1 | || 0.1+0.05 ; 20.0+0.2 . 1.2MAX 10 Te) o D << _ Oo 2000-02-24 33/33