74HC27D,652 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with

Low-Power Schottky TTL (LSTTL).

The 74HC27; 74HCT27 provides the 3-input NOR function.

2. Features

■Multiple package options

■Complies with JEDEC standard no. 7A

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A115-A exceeds 200 V

■Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Ordering information

74HC27; 74HCT27

Triple 3-input NOR gate

Rev. 03 — 7 January 2008 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC27N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HC27D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

74HC27DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width

5.3 mm SOT337-1

74HC27PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm SOT402-1

74HC27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

74HCT27N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT27D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

Product data sheet Rev. 03 — 7 January 2008 2 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

4. Functional diagram

74HCT27DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width

5.3 mm SOT337-1

74HCT27PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm SOT402-1

74HCT27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

Table 1. Ordering information

…continued

Type number Package

Temperature range Name Description Version

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

mna936

1B 1Y

112

2B 2Y

3B 3Y

mna935

≥ 1

mna937

Product data sheet Rev. 03 — 7 January 2008 3 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

supply pin or input

Fig 4. Pin conﬁguration DIP14, SO14, (T)SSOP14 Fig 5. Pin conﬁguration DHVQFN14

74HC27

74HCT27

1A VCC

1B 1C

2A 1Y

2B 3C

2C 3B

2Y 3A

GND 3Y

001aag759

7 8

001aag760

74HC27

74HCT27

Transparent top view

2Y 3A

2C 3B

2B 3C

2A 1Y

1B 1C

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

1A 1 data input

1B 2 data input

2A 3 data input

2B 4 data input

2C 5 data input

2Y 6 data output

GND 7 ground (0 V)

3Y 8 data output

3A 9 data input

3B 10 data input

3C 11 data input

1Y 12 data output

1C 13 data input

VCC 14 supply voltage

Product data sheet Rev. 03 — 7 January 2008 4 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.

8. Recommended operating conditions

Table 3. Function table[1]

Inputs Outputs

nA nB nC nY

LLLH

XXHL

XHXL

HXXL

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input clamping current VI < −0.5 V or VI>V

CC + 0.5 V [1] -±20 mA

IOK output clamping current VO<−0.5 V or VO>V

CC + 0.5 V [1] -±20 mA

IOoutput current −0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 50 mA

IGND ground current −50 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation [2]

DIP14 package - 750 mW

SO14, (T)SSOP14 and

DHVQFN14 packages - 500 mW

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

Type 74HC27

VCC supply voltage 2.0 5.0 6.0 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

Product data sheet Rev. 03 — 7 January 2008 5 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

9. Static characteristics

tr, tfinput rise and fall times VCC = 2.0 V - - 1000 ns

VCC = 4.5 V - 6.0 500 ns

VCC = 6.0 V - - 400 ns

Tamb ambient temperature −40 - +125 °C

Type 74HCT27

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

tr, tfinput rise and fall times VCC = 4.5 V - 6.0 500 ns

Tamb ambient temperature −40 - +125 °C

Table 5. Recommended operating conditions

…continued

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Static characteristics type 74HC27; 74HCT27

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74HC27

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI=V

IH or VIL

IO=−20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO=−20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO=−20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI=V

IH or VIL

IO=20µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO=20µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO=20µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC = 6.0 V --±0.1 - ±1.0 - ±1.0 µA

ICC supply current VI=V

CC or GND; IO=0A;

VCC = 6.0 V - - 2.0 - 20 - 40 µA

CIinput

capacitance - 3.5 - - - - - pF

Product data sheet Rev. 03 — 7 January 2008 6 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

10. Dynamic characteristics

74HCT27

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI=V

IH or VIL; VCC = 4.5 V

IO=−20 µA 4.4 4.5 - 4.4 - 4.4 - V

IO=−4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI=V

IH or VIL; VCC = 4.5 V

IO=20µA - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC = 5.5 V --±0.1 - ±1.0 - ±1.0 µA

ICC supply current VI=V

CC or GND;

VCC = 5.5 V; IO=0A - - 2.0 - 20 - 40 µA

∆ICC additional

supply current per input pin;

VI=V

CC −2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V;

IO=0A

nA, nB or nC inputs - 150 540 - 675 - 735 µA

CIinput

capacitance - 3.5 - - - - - pF

Table 6. Static characteristics type 74HC27; 74HCT27

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Table 7. Dynamic characteristics type 74HC27; 74HCT27

GND = 0 V; for load circuit see Figure 7.

Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit

Min Typ Max Max

(85 °C) Max

(125 °C)

74HC27

tpd propagation delay nA, nB, nC to nY; see Figure 6 [1]

VCC = 2.0 V - 28 90 115 135 ns

VCC = 4.5 V - 10 18 23 27 ns

VCC = 5.0 V; CL=15pF - 8 - - - ns

VCC = 6.0 V - 8 15 20 23 ns

tttransition time see Figure 6 [2]

VCC = 2.0 V - 19 75 95 110 ns

VCC = 4.5 V - 7 15 19 22 ns

VCC = 6.0 V - 6 13 16 19 ns

Product data sheet Rev. 03 — 7 January 2008 7 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in µW):

PD=C

PD ×VCC2×fi×N+∑ (CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

11. Waveforms

CPD power dissipation

capacitance per package; VI= GND to VCC [3] -24- - -pF

74HCT27

tpd propagation delay nA, nB, nC to nY; see Figure 6 [1]

VCC = 4.5 V - 12 21 26 32 ns

VCC = 5.0 V; CL=15pF - 10 - - - ns

tttransition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns

CPD power dissipation

capacitance per package;

VI= GND to VCC −1.5 V [3] -30- - -pF

Table 7. Dynamic characteristics type 74HC27; 74HCT27

GND = 0 V; for load circuit see Figure 7.

Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit

Min Typ Max Max

(85 °C) Max

(125 °C)

Measurement points are given in Table 8.

VOL and VOH are typical voltage output drop that occur with the output load.

Fig 6. Input (nA, nB, nC) to output (nY) propagation delays and output transition times

001aag761

nA, nB, nC input

GND

VOH

VOL

nY output

tTHL tTLH

tPHL tPLH

Table 8. Measurement points

Type Input Output

VMVMVXVY

74HC27 0.5VCC 0.5VCC 0.1VCC 0.9VCC

74HCT27 1.3 V 1.3 V 0.1VCC 0.9VCC

Product data sheet Rev. 03 — 7 January 2008 8 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig 7. Load circuit for measuring switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

PULSE

GENERATOR

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC27 VCC 6 ns 15 pF, 50 pF 1 kΩopen

74HCT27 3 V 6 ns 15 pF, 50 pF 1 kΩopen

Product data sheet Rev. 03 — 7 January 2008 9 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

12. Package outline

Fig 8. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 03 — 7 January 2008 10 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

Fig 9. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 03 — 7 January 2008 11 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

Fig 10. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 03 — 7 January 2008 12 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

Fig 11. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 7 January 2008 13 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

Fig 12. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 03 — 7 January 2008 14 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT27_3 20080107 Product data sheet - 74HC_HCT27_CNV_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Added type number 74HC27BQ and 74HCT27BQ (DHVQFN14 package)

74HC_HCT27_CNV_2 19970828 Product speciﬁcation - -

Product data sheet Rev. 03 — 7 January 2008 15 of 16

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

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reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

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malfunction of an NXP Semiconductors product can reasonably be expected

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damage. NXP Semiconductors accepts no liability for inclusion and/or use of

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therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

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Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC27; 74HCT27

Triple 3-input NOR gate

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 January 2008

Document identifier: 74HC_HCT27_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Contact information. . . . . . . . . . . . . . . . . . . . . 15

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16