1.5A 260kHz/520kHz Boost Regulators The CS5171/2/3/4 are 260kHz/520kHz switching reg- ulators with a 1.5A high efficien- cy integrated switch. These parts operate over a wide input volt- age range of 2.7V to 30V. The flexibility of the design allows the chips to be operated in most power supply configurations, such as boost, flyback, forward, inverting, and sepic. The ICs utilize current mode architec- ture, which allows and line regulati n aswell a as a Part Number Pacsregt Cate a C$5171 260kHz CS5173 520kHz Application Diagram 3.3V to 5V/400mA Boost Converter practical means for current limit. Combining high frequency oper- ation with a highly integrated regulator circuit provides for an extremely compact power sup- ply solution. The circuit design includes provisions | for feature NH er positive or voltage regulation. parts are pin to pin com- patible with LT1372/ 1373. Feedback Voltage Polarity positive positive CS5171/2/3/4 | Dt Vout CO sv MBRS120T3 0.01 uF + C3 ssO ATS 22uF VIN 22H 3.3VC} PS 22uF +C2 lA Cherry Semiconductor Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 8/19/99 1 A cuenry Company B/E/Z7/TZTSSDCS5171/2/3/4 Absolute Maximum Ratings N/A 200mA IC Power Input 40V NFB (CS5172/4 only) Negative Feedback Input {t ient, 10ms) 10V 10V Analog Ground Junction Temperature Range, Ty ..c cece neeeneeieaneeaneneeeneieeeseeeneneeneesseiseeneneneeieisanenseneneanenenaneey -40C to 150C Storage Temperature Range, TsTORAGE ts tteiteeneeseiseiceeeceineeeeneeines Tee ceeeeeeeeseeseeeeaeseeaeesaaeees -65 to 150C Lead Temperature Soldering: Reflow (SMD styles only) ..... sec, max above 183C, 230C peak ESD, Human Body Model ....cscccccssesseeseessssssssseeesesesseenggaenseliiuthess fio Neccssssssscsessecsesasesssssssscseesssnesisscsensseneeeey 2kV ESD, Machine Model ..cccccccccccssscscsssscscssssssssssssssesseqeeesS bbe ed Geccces Gases Qtlescsacecsssacsesecscessecsssesesessesecassesaseesesaeeesecaseessaeeeessaeesecaaeess 200V Electrical Characteristics: -40C < T, < 85C; -40C < Tj < 125C; 2.7V < Vcc < 30V; For all CS5171/2/3/4 specifications unless otherwise stated. M Positive and Negative Error Amplifiers FB Reference Voltage Vc tied to FB measure at FB 1.257 1.276 1.295 Vv (CS5171/3 only) FB Input Current (CS5171/3 only) FB Reference Voltag: Line Regulation Vc=0.8V 01 03 IV (CS5171/3 only) Positive and Negative Error Note 1 400 600 800 uMho Amp Transconductance Negative Error Amp Gain Note 1 100 180 320 V/VElectrical Characteristics: -40C < T, < 85C; -40C < Tj < 125C; 2.7V < Vcc < 30V; For all CS5171/2/3/4 specifications unless otherwise stated. b//Z/TZTSSD Mf Positive and Negative Error Amplifiers continued Vc Sink Current FB = 1.5V or NFB = -3.125V, Vc =1.5V 200 625 1500 pA Vc Low Clamp Voltage FB = 1.5V or NFB =-3.125V, 0.35 0.5 0.65 Vv Vc sinks 50uA HB Oscillator Base Operating Frequency CS5171/2, FB =1V or NFB =-2V 240 260 280 kHz Base Operating Frequency CS5173/4, FB = 1V or NFB =-2V 480 520 560 kHz Maximum Duty Cycle eny"re uces to 20% of the FB Frequency Shift Threshold, ; .. base frequency @ Sync/Shutdown Sync Range CS5171/2 280 500 kHz Sync Pulse Transition Rise time = 20ns 2.5 Vv Threshold Shutdown Threshold @ Power Switch Switch Saturation Voltage Iswrrcu = 1.54 0.8 1.0 Iswrrcu = 10mA 0.09 0.3 Vv Minimum Pulse Width FB = OV, Isw = 2.5A, NFB = 3.0V 100 180 200 nsCS5171/2/3/4 Electrical Characteristics: -40C < T, < 85C; -40C < Tj < 125C; 2.7V < Vcc < 30V; For all CS5171/2/3/4 Rcartetne unless Amare stated. @ Power Switch: continued Alec/ AIVew 0< Iow <15A 10 20 mA/A H General Operating Current Minimum Operation Input Voltage Thermal Hysteresis Note 1 25 C Note 1: Guaranteed by design, not 100% tested in production. Package Pin Description 1 Ve Loop compensation pin. The Vc pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensa- tion can be implemented by a simple RC network as shown in the applica- tion diagram as R1 and Cl. 2 (CS5172/4 only) No connection. 3 (CS5172/4 only) NFB Negative regulator feedback pin. This pin provides sensing of a negative voltage output and is referenced to -2.5V. When the voltage at this pin goes above -1.2V, chip switching frequency reduces to 20% of the nominal fre- quency. Leave it floating when only regulating a positive voltage. 5 Vee Input power supply pin. This pin supplies power to the part and should have a bypass capacitor attached. 7 PGnd Power ground. Provides ground to the emitter of the power switching transistor. Connection to a good ground plane is essentialBlock Diagram Voc THERMAL Shut DOV | SHUTDOWN r REGULATOR Vew PWM LATCH 50uS OSCILLATOR s Q DRIVER TIMER R ss GOI] ome FREQUENCY SHIFT 5:1 e-----P-------------------- ! 200k \ SLOPE ! COMPENSATION I NEGATIVE ! ! 2.0V = ERROR AMP ; I I 250K VJ I I NFB CQ), PN ! RAMP ) PaND I oss172/4 - T SUMMER 1 only J | ' PWM COMPARATOR = + FB C85171/3 POSITIVE ERROR AMP l l ! l l l only l I 1.276V = l l l Vc PIN1 FW etelalemaibaererittelsyn| Current Mode Control Vin 9 Oscillator Vo E R PWM Comparator PWM LATCH z SUMMER XI Slope Compensation Power Switch Rt 100ms2 Figure 1. Current Mode Control Scheme The CS517X family incorporates a current mode control scheme, in which the PWM ramp signal is derived from power switch current. This ramp signal is compared to the output of the error amplifier to control the on time of the power switch. The oscillator is only used here as a fixed frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over the conventional voltage mode controller. First, derived directly from the inductor, the ramp signal will respond immediately to line voltage changes. This elimi- nates the delay caused by the output filter and error ampli- fier, which is commenly Suffered in voltage mode. The sec- ond benefit cmnes i am inherent pulse-by-pulse current lingitini merly clamping the peak switching current. Firtally; since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows both simpler compensation and a higher gain bandwidth over a comparable voltage mode circuit. Without discrediting its apparent merits, current mode control comes with its own peculiar problems, mainly, sub- harmonic oscillation at duty cycle over 50%. The CS517X family solves this problem by adopting slope compensa- tion in which a fixed ramp generated by the oscillator is b//Z/TZTSSDCS5171/2/3/4 Application Information: continued added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advan- tages of current mode control. Oscillator and Shutdown Sync Tl I Current Ramp _r rT LU 7 id LU Figure 2. Timing Diagram of Sync and Shut Down. The oscillator is trimmed to guarantee an 8% frequency accuracy. As shown in Figure 1, the output of the oscillator - turns on the power switch at a frequency of 260kHag (CS5171/2) or 520kHz (CS5173/4). The p Switch i is ~ turned off by the output of the PWM orkparator. The maximum duty cycle can be as high 'as 90%. A TTL compatible sync input at the SS pin is capable of syncing up to 1.8 times the base oscillator frequency. As shown in Figure 2, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator does so. The sync signal also resets the oscillator. The sync operation allows multiple power supplies to operate at the same frequency. A logic low sus- tained for typically 50us at the SS pin will shut down the ICs and reduce the supply current to 50uA. An additional feature includes frequency shift to 20% of the nominal frequency when either the NFB or FB pins trigger the threshold. During overload, power up, or short circuit conditions, the minimum switch on time is limited by the PWM comparator blanking period. Extra switch off time reduces the minimum duty cycle to protect external components and the IC itself. As previously mentioned, this block olsaproduces srainp for the slope compensation to improve regulator Error Amplifier NFB CS5172/4 J negative error-amp i * C1 = Ly L-i20p | Voltage 0.01HF 1.286V Clamp Ri 5 5K C$5171/3 FB positive error-amp Figure 3. Error amplifier equivalent circuit. For CS5172/4, the NFB pin is internally referenced to -2.5V with approximately a 250kQ input impedance. For CS5171/3, the FB pin is directly connected to the inverting input of the positive error amplifier whose non-inverting input is fed by the 1.276V reference. Both amplifiers are transconductance amplifiers with high output impedance of approximately 1MQ as shown in Figure 3. The Vc pin is connected to the output of the error amplifiers and is inter- nally clamped between 0.6V and 1.7V. A typical connec- tion at the Vc pin includes a capacitor in series with a resistor to ground, forming a pole/zero for loop compen- sation. An external shunt can be connected between the Vc pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nomi : h-switch driver takes a control signal from the logic sec- tion to drive the output power switch. The switch is grounded through emitter resistors (100mQ total) to the PGnd pin. The PGnd is not connected to the IC substrate to isolate switching noise from the analog ground. The peak switching current is clamped by an internal circuit. The clamp current is guaranteed to be greater than 1.5A and varies with duty cycle due to slope compensation. The power switch can withstand a maximum voltage of 40V on the collector (Vsy pin). The saturation voltage of the switch is less than 1V to minimize power dissipation. Additionally, a 100ns blanking period is placed at the ris- ing edge of the current slope to prevent mis-triggering of the PWM Comparator. This is necessary due to the turn-on current ringing. ctr current will increase during the whole switch- ihe ycle, causing excessive current to be drawn from the input power supply. Since control ICs dont have the means to limit load current, an external current limit cir- cuit (such as fuses and relays) has to be implemented to protect the load, power supply and ICs. Ina flyback regulator application, the frequency shift built into the ICs will prevent the damage to the chip and exter- nal components. This feature will reduce the minimum duty cycle and allow the transformer secondary side to absorb enough energy before the switch turns back on.Application Information: continued 10.00 400ps 1.00 o2 ch cha S000 100 chi 1: Input voltage 2: Output voltage 3: Ve 4: Inductor Current (1A/Div) Figure 4. Start up waveforms of the boost converter shown in the Application Diagram. LOAD = 502 T.0 7 MM 40-0ps 1.00 V2 che ch4 chi 5.00V~ 100Vv 1: Input voltage 2: Output voltage 3:Ve 4: Inductor Current (1A/Div) Figure 5: First several cycles of the start up waveforms shown in Figure 5. The CS517X can be activated by either connecting the Vcc pin to a voltage source or enabling the SS pin. Start up waveforms shown in Figure 4 and Figure 5 are measured in the boost converter demonstrated in the Application Diagram. Recorded after the input voltage is turned on, these waveforms clearly show the various phases during this power up transition. Figure 4 shows the whole start up period, while Figure 5 zeros in on the very first several switching cycles. When the input voltage at the Vcc pin is below the mini- mum threshold voltage, the Vsy pin is high impedance. .. Therefore, current conducts directly from the input gow source to the output through the inductgr and diatk phase is identified in Figure 5 as the'fi swing. When the Vcc pin voltage,r Wwe the threshold, the Vow pin starts to switch to PGid. Detecting a low output voltage at the FB pin, the built-in frequency shift feature reduces the switching frequency to 20% of the nominal value. This increases switch off time during each switching cycle and reduces the average current. The peak current in this phase is clamped by the internal current limit. By applying a voltage clamp or soft start circuit at the Vc pin, this peak current can be further limited. When the feed- back voltage at the FB pin rises above 0.7V, the frequency increases to its nominal value. In this phase, the peak cur- rent decreases while the output voltage continues approaching the targeted value. Finally, after a settling period, the system enters steady-state operation. Frequency Compensation At the Vc pin, a RC network shall connect in series to per- form loop frequency compensation. Along with the transconductance amplifier output impedance, the RC net- work forms two pole and one zero system to optimize dynamic performance while maintaining stability. The locations of poles and zero are: 1 1 1 fp1= 2nRoC, fZ= 2nRiC, {P2= 2ARyCo Ro: Transconductance amplifier output resistor = 1MQ Co: Equivalent output capacitor = 120p Negative Voltage Feedback Since the negative error amplifier has finite input impedance as shown in Figure 6, its induced error has to be considered. If a voltage divider is used to scale down the negative output voltage for the NFB pin, the equation for calculating output voltage is: -VouT Negative Error-Amp <== =, Figure 6: Negative Error Amplifier and Npg pin -2.5(R1 + R2) RD -10uA xR1 -Vourt = b//Z/TZTSSDCS5171/2/3/4 Application Information: continued It is shown that if R1 is less than 10K, the deviation from the design target will be less than 0.1V. If the tolerances of the negative voltage reference and NFB pin input current are considered, the possible offset of the output Vorrser varies in the range of: -0.05 (R1 + R2) R2 | - (15uA x RI) < Vorrser < - (5A x R1) 0.05 (R1 + R2) R2 Vsw Voltage Limit In the boost circuit the Vow pin maximum voltage is set by the maximum output voltage plus output diode forward voltage. The diode forward voltage is typically 0.5V for Schottky diodes and 0.8V for ultrafast recovery diodes Vsw(mMax) = Vout(Max) + Vr where: Vp output diode forward voltage. In the flyback circuit, the peak Vsy voltage is governed by: Vewimax) = Vin(max) + (Vour + Vg) x N where N: transformer turns ratio primary over secondary. When the power switch turns off there exists a voltage spike superimposed on top of the steady-state voltage. Usually this voltage spike is caused by transformer leakage inductance charging stray capacitance between the Vsw and PGnd pins. To prevent the voltage at the Vsw pin from exceeding the maximum rating, a transient voltage sup; pressor in series with a diode is paralleled with the'prity ry windings. Another method of clampitig. switch viltage is to connect a transient volta ssdr'between the Vsw pin and ground. Magnetic Component Selection When choosing a magnetic component, one has to consider factors such as peak current, core and ferrite material, out- put voltage ripple, EMI, temperature range, physical size and cost. In boost circuits, the average inductor current is output current times voltage gain (Voyr/ Vin), assuming 100% energy transfer efficiency. In continuous conduction mode, inductor ripple current is Vin(Vout-Vin) IRIPPLE= (f)(L)(Voup) Where f is 260kHz for C$5171 /2 and 520kHz for CS5173/4. The peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor saturation. The above equation can also be referenced on selecting the value of the inductor based on the tolerance of the ripple current in the circuits. Small ripple current pro- vides the benefits of small input capacitors and greater out- put current capability. A core geometry, like a rod or bar- rel, is prone to generating high magnetic field radiation, but is relatively cheap and small. Other core geometry, such as a toroid, provides a closed magnetic loop to pre- vent EMI. Input Capacitor: a Dt | 1: Input voltage Vix ripple (AC coupled) 2: Input Current |i 3: Inductor Current I, Figure 7a: Typical igip Figure 7b: Typical input voltage and current ripple waveforms. In boost circuits, the inductor becomes part of the input fil- ter shown in Figure 7b. In continuous mode, the input cur- rent waveform is triangular and does not contain a largeApplication Information: continued pulsed current, as shown in Figure 7a. This reduces the requirements imposed on the input capacitor selection. During continuous conduction mode, the peak to peak inductor ripple current is given in the previous section. As we can see from Figure 7, the product of the inductor cur- rent ripple and the input capacitors effective series resistor (ESR) determine the V;j ripple. In most applications, capacitors in the range of 10uF to 100uF with an ESR less than 0.3Q work well up to a full 1.5A switch current. The situation is different in a flyback circuit. The input cur- rent is discontinuous and a significant pulsed current is witnessed by the input capacitors. Therefore, there are two requirements for capacitors in a flyback regulator, energy storage and filtering. To maintain a stable voltage supply to the chip, a storage capacitor larger than 20uF with low ESR is required. In addition, a small bypass capacitor may be necessary to reduce the noise generated by the inductor. To reduce the noise, insert a 1.0uF ceramic capacitor between Vix and ground as close as possible to the chip. Output Capacitor Selection ate flee eee eee 1: Output Voltage Vout ripple (AC coupled) 2: Inductor Current IL Figure 8: Typical output voltage ripple. By examining the wayefo hwn in Figure 8, we can see that the output Hlag pple comes from two major sources, namely, capacitor ESR and the charging / discharg- ing of the output capacitor. In boost circuits, when the power switch turns off, , flows into the output capacitor causing an instant AV = Ij, x ESR. At the same time, cur- rent I,-Igur charges the capacitor and increases the output voltage gradually. When the power switch is turned on, I, is shunted to the ground and Igy discharges the output capacitor. When the I, ripple is small enough, I, can be treated as the constant and is equal to input current Iyy. Summing up, the output voltage peak-peak ripple can be calculated by: (Itn-lour)(1-D) (Cour)(f) IourD + (Coun) + lin x ESR VOUT(RIPPLE) = The equation can be expressed more conveniently in terms of Vin, Vour and Ioyy for design purposes as follows: lour(Vour-Vin) =__1 VouT(RIPPLE) = Vour * (Courd(f) + Mlour)VourXESR) Vin The capacitor RMS ripple current is: (in: oT) 1-D) + (our)(D) = Tour ort IN PLE = " Although the above equations apply only for boost circuits, similar equations can be derived for flyback circuits. Circuit Layout Guidelines In any switching power supply, circuit layout is very important for proper operation. Rapidly switching currents combined with trace inductance generates voltage transi- tions that can cause problems. Therefore the following guidelines should be followed in the layout. 1. In boost circuits, high AC current circulates within the loop composed of the diode, output capacitor, and on- chip power transistor. The length of associated traces and leads should be kept as short as possible. In the fly- back circuit, high AC current loops exist on both sides of the transformer. On the primary side, the loop consists of the.inptit.capacitor, transformer, and on-chip power , While the transformer, rectifier diodes, and x put capacitors form another loop on the secondary side. Just as in the boost circuit, all traces and leads con- taining large AC currents should be kept short. 2. Separate the low current signal grounds from the power grounds. Use single point grounding or ground plane construction for the best results. 3. Locate the voltage feedback resistors as near the IC as possible to keep the sensitive feedback wiring short. Connect feedback resistors to the low current analog ground. b//Z/TZTSSDCS5171/2/3/4 cssi713 8 Vout Vo Vsw ct NC O.01ur NFB AGND 6 ss Voc 22uH Vin Sv Vo Vsw sv *22uF FB POND my MBRS120T3 C1 0.01 nF NC c3 ss ss 22uF Vn 24VA0V Figure 9: 2.4V-10V to 5V Sepic Converter. CS88172/4 Vout 8 412V D2 MBRS120T3. c3 22uF Figure 10: 5V to -12V Inverting Converter. 10Package Specification D Thermal Data 8L Lead Count Metric English SO Narrow Max Min Max Min Rec typ 45 C/W 8 Lead SO Narrow 5.00 480 .197 .189 Rea typ 165 C/W f= ft 0.25 (.010) 0.19 (.008) 1 f_ 0.40 (.016) REF: JEDEC MS-012 AAA 7 4.00 (.157) 6.20 (.244) 3.80 (.150) 5,80 (.228) 0.51 (.020) 1 . TI [ O33 (013) 1.27 (.050) BSC 1.75 (.069) MAX [ a a 1.57 (.062) \ 1.37 (.054) iW \ T/ t 0.25 (0.10) 0.10 (004) p>| Part Number Description CS5171ED8 8L SO Narrow CS5171EDR8 8L SO Narrow (tape & reel) CS5172ED8 8L SO Narrow CS5172EDR8 8L SO Narrow (tape & reel) CS5173ED8 8L SO Narrow CS5173EDR8 8L SO Narrow (tape & reel) CS5174ED8 8L SO Narrow CS5174EDR8 8L SO Narrow (tape & reel) This product is in the preproduction stages of the design process. The data sheet contains preliminary data. Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please con- tact Cherry Semiconductor Corporation for the latest available information. Rev. 8/19/99 11 1999 Cherry Semiconductor Corporation b/E/Z/TZTSSD