LM1972
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LM1972 μPot 2-Channel 78dB Audio Attenuator with Mute
Check for Samples: LM1972
1FEATURES DESCRIPTION
The LM1972 is a digitally controlled 2-channel 78dB
2• 3-Wire Serial Interface audio attenuator fabricated on a CMOS process.
• Daisy-Chain Capability Each channel has attenuation steps of 0.5dB from
• 104dB Mute Attenuation 0dB–47.5dB, 1.0dB steps from 48dB–78dB, with a
mute function attenuating 104dB. Its logarithmic
• Pop and Click Free Attenuation Changes attenuation curve can be customized through
software to fit the desired application.
APPLICATIONS The performance of a μPot is demonstrated through
• Automated Studio Mixing Consoles its excellent Signal-to-Noise Ratio, extremely low
• Music Reproduction Systems (THD+N), and high channel separation. Each μPot
• Sound Reinforcement Systems contains a mute function that disconnects the input
signal from the output, providing a minimum
• Electronic Music (MIDI) attenuation of 96dB. Transitions between any
• Personal Computer Audio Control attenuation settings are pop free.
The LM1972's 3-wire serial digital interface is TTL
KEY SPECIFICATIONS and CMOS compatible; receiving data that selects a
• Total Harmonic Distortion + channel and the desired attenuation level. The Data-
Noise: 0.003 % (max) Out pin of the LM1972 allows multiple μPots to be
daisy-chained together, reducing the number of
• Frequency response: 100 kHz (−3dB) (min) enable and data lines to be routed for a given
• Attenuation range (excluding application.
mute): 78 dB (typ)
• Differential attenuation: ±0.25 dB (max)
• Signal-to-noise ratio
(ref. 4 Vrms): 110 dB (min)
• Channel separation: 100 dB (min)
Typical Application
Connection Diagram
Figure 1. Typical Audio Attenuator Application Figure 2. 20-Lead SOIC - Top View
Circuit See DW Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1995–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM1972
SNAS094D –APRIL 1995–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Supply Voltage (VDD–VSS) 15V
Voltage at Any Pin VSS −0.2V to VDD + 0.2V
Power Dissipation (4) 150 mW
ESD SusceptabiIity (5) 2000V
Junction Temperature 150°C
Soldering Information DW Package (10 sec.) +260°C
Storage Temperature −65°C to +150°C
(1) All voltages are measured with respect to GND pins (1, 3, 5, 6, 14, 16, 19), unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. Electrical Characteristics state DC and AC electrical specifications under particular test conditions. This
assumes that the device is within the Operating Ratings. The typical value is a good indication of device performance.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PD = (TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings,
whichever is lower. For the LM1972, TJMAX = +150°C, and the typical junction-to-ambient thermal resistance, when board mounted, is
65°C/W.
(5) Human body model, 100 pF discharged through a 1.5 kΩresistor.
Operating Ratings (1)(2)
TMIN TATMAX
Temperature Range TMIN ≤TA≤TMAX 0°C ≤TA≤+70°C
Supply Voltage (VDD −VSS) 4.5V to 12V
(1) All voltages are measured with respect to GND pins (1, 3, 5, 6, 14, 16, 19), unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. Electrical Characteristics state DC and AC electrical specifications under particular test conditions. This
assumes that the device is within the Operating Ratings. The typical value is a good indication of device performance.
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Electrical Characteristics (1)(2)
The following specifications apply for all channels with VDD = +6V, VSS =−6V, VIN = 5.5 Vpk, and f = 1 kHz, unless otherwise
specified. Limits apply for TA= 25°C. Digital inputs are TTL and CMOS compatible.
Symbol Parameter Conditions LM1972 Units
(Limits)
Typical(3) Limit (4)
ISSupply Current Inputs are AC Grounded 2 4mA (max)
THD+N Total Harmonic Distortion plus Noise VIN = 0.5 Vpk @ 0dB Attenuation 0.0008 0.003 % (max)
XTalk Crosstalk (Channel Separation) 0dB Attenuation for VIN 110 100 dB (min)
VCH measured @ −78dB
SNR Signal-to-Noise Ratio Inputs are AC Grounded
@−12dB Attenuation 120 110 dB (min)
A-Weighted
AMMute Attenuation 104 96 dB (min)
Attenuation Step Size Error 0dB to −47.5dB ±0.05 dB (max)
−48dB to −78dB ±0.25 dB (max)
Absolute Attenuation Error Attenuation @ 0dB 0.03 0.5 dB (min)
Attenuation @ −20dB 19.8 19.0 dB (min)
Attenuation @ −40dB 39.5 38.5 dB (min)
Attenuation @ −60dB 59.3 57.5 dB (min)
Attenuation @ −78dB 76.3 74.5 dB (min)
Channel-to-Channel Attenuation Attenuation @ 0dB, −20dB, −40dB, −60dB ±0.5 dB (max)
Tracking Error Attenuation @ −78dB ±0.75 dB (max)
ILEAK Analog Input Leakage Current Inputs are AC Grounded 10.0 100 nA (max)
RIN AC Input Impedance Pins 4, 20, VIN = 1.0 Vpk, f = 1 kHz 40 20 kΩ(min)
60 kΩ(max)
IIN Input Current @ Pins 9, 10, 11 @ 0V < VIN < 5V 1.0 ±100 nA (max)
fCLK Clock Frequency 3 2 MHz (max)
VIH High-Level Input Voltage @ Pins 9, 10, 11 2.0 V (min)
VIL Low-Level Input Voltage @ Pins 9, 10, 11 0.8 V (max)
Data-Out Levels (Pin 12) VDD=6V, VSS=0V 0.1 V (max)
5.9 V (min)
(1) All voltages are measured with respect to GND pins (1, 3, 5, 6, 14, 16, 19), unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. Electrical Characteristics state DC and AC electrical specifications under particular test conditions. This
assumes that the device is within the Operating Ratings. The typical value is a good indication of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to Texas Instrument's AOQL (Average Output Quality Level).
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Timing Diagram
Figure 3. Timing Diagram
PIN DESCRIPTIONS
Signal Ground (3, 19):Each input has its own independent ground, GND1 and GND2.
Signal Input (4, 20): There are 2 independent signal inputs, IN1 and IN2.
Signal Output (2, 17): There are 2 independent signal outputs, OUT1 and OUT2.
Voltage Supply (13, 15): Positive voltage supply pins, VDD1 and VDD2.
Voltage Supply (7, 18): Negative voltage supply pins, VSS1 and VSS2. To be tied to ground in a single supply
configuration.
AC Ground (1, 5, 6, 14, 16): These five pins are not physically connected to the die in any way (i.e., No
bondwires). These pins must be AC grounded to prevent signal coupling between any of the pins nearby.
Pin 14 should be connected to pins 13 and 15 for ease of wiring and the best isolation, as an example.
Logic Ground (8): Digital signal ground for the interface lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.
Clock (9): The clock input accepts a TTL or CMOS level signal. The clock input is used to load data into the
internal shift register on the rising edge of the input clock waveform.
Load/Shift (10): The load/shift input accepts a TTL or CMOS level signal. This is the enable pin of the device,
allowing data to be clocked in while this input is low (0V).
Data-In (11): The data-in input accepts a TTL or CMOS level signal. This pin is used to accept serial data from
a microcontroller that will be latched and decoded to change a channel's attenuation level.
Data-Out (12): This pin is used in daisy-chain mode where more than one μPot is controlled via the same data
line. As the data is clocked into the chain from the μC, the preceding data in the shift register is shifted out
the DATA-OUT pin to the next μPot in the chain or to ground if it is the last μPot in the chain. The
LOAD/SHIFT line goes high once all of the new data has been shifted into each of its respective registers.
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Typical Performance Characteristics
Supply Current vs Supply Current vs
Supply Voltage Temperature
Figure 4. Figure 5.
Noise Floor Spectrum by FFT THD
Amplitude vs
vs Freq by FFT
Frequency VDD −VSS = 12V
Figure 6. Figure 7.
THD
vs
VOUT at
1 KHz by FFT
VDD −VSS = 12V Crosstalk Test
Figure 8. Figure 9.
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Typical Performance Characteristics (continued)
THD + N vs
Frequency and Amplitude FFT of 1 kHz THD
Figure 10. Figure 11.
THD + N
vs
FFT of 20 kHz THD Amplitude
Figure 12. Figure 13.
THD + N THD + N
vs vs
Amplitude Amplitude
Figure 14. Figure 15.
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APPLICATION INFORMATION
ATTENUATION STEP SCHEME
The fundamental attenuation step scheme for the LM1972 μPot is shown in Figure 16. This attenuation step
scheme, however, can be changed through programming techniques to fit different application requirements.
One such example would be a constant logarithmic attenuation scheme of 1dB steps for a panning function as
shown in Figure 17. The only restriction to the customization of attenuation schemes are the given attenuation
levels and their corresponding data bits shown in Table 1. The device will change attenuation levels only when a
channel address is recognized. When recognized, the attenuation level will be changed corresponding to the
data bits shown in Table 1. As shown in Figure 19, an LM1972 can be configured as a panning control which
separates the mono signal into left and right channels. This circuit may utilize the fundamental attenuation
scheme of the LM1972 or be programmed to provide a constant 1dB logarithmic attenuation scheme as shown in
Figure 17.
LM1972 Channel Attenuation
vs Digital Step Value
Figure 16. LM1972 Attenuation Step Scheme
LM1972 Channel Attenuation
vs Digital Step Value
(Programmed 1.0dB Steps)
Figure 17. LM1972 1.0dB
Attenuation Step Scheme
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LM1972 Channel Attenuation
vs Digital Step Value
(Programmed 2.0dB Steps)
Figure 18. LM1972 2.0dB Attenuation Step Scheme
Figure 19. Mono Panning Circuit
INPUT IMPEDANCE
The input impedance of a μPot is constant at a nominal 40 kΩ. To eliminate any unwanted DC components from
propagating through the device it is common to use 1 μF input coupling caps. This is not necessary, however, if
the dc offset from the previous stage is negligible. For higher performance systems, input coupling caps are
preferred.
OUTPUT IMPEDANCE
The output of a μPot varies typically between 25 kΩand 35 kΩand changes nonlinearly with step changes.
Since a μPot is made up of a resistor ladder network with a logarithmic attenuation, the output impedance is
nonlinear. Due to this configuration, a μPot cannot be considered as a linear potentiometer, but can be
considered only as a logarithmic attenuator.
It should be noted that the linearity of a μPot cannot be measured directly without a buffer because the input
impedance of most measurement systems is not high enough to provide the required accuracy. Due to the low
impedance of the measurement system, the output of the μPot would be loaded down and an incorrect reading
will result. To prevent loading from occurring, a JFET input op amp should be used as the buffer/amplifier. The
performance of a μPot is limited only by the performance of the external buffer/amplifier.
MUTE FUNCTION
One major feature of a μPot is its ability to mute the input signal to an attenuation level of 104dB as shown in
Figure 16. This is accomplished internally by physically isolating the output from the input while also grounding
the output pin through approximately 2 kΩ.
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The mute function is obtained during power-up of the device or by sending any binary data of 01111111 and
above (to 11111111) serially to the device. The device may be placed into mute from a previous attenuation
setting by sending any of the above data. This allows the designer to place a mute button onto his system which
could cause a microcontroller to send the appropriate data to a μPot and thus mute any or all channels. Since
this function is achieved through software, the designer has a great amount of flexibility in configuring the
system.
DC INPUTS
Although the μPot was designed to be used as an attenuator for signals within the audio spectrum, the device is
capable of tracking an input DC voltage. The device will track DC voltages to a diode drop above each supply
rail.
One point to remember about DC tracking is that with a buffer at the output of the μPot, the resolution of DC
tracking will depend upon the gain configuration of that output buffer and its supply voltage. It should also be
remembered that the output buffer's supply voltage does not have to be the same as the μPot's supply voltage.
This could allow for more resolution when DC tracking.
SERIAL DATA FORMAT
The LM1972 uses a 3-wire serial communication format that is easily controlled by a microcontroller. The timing
for the 3-wire set, comprised of DATA-IN, CLOCK, and LOAD/SHIFT is shown in Figure 3.Figure 22 exhibits in
block diagram form how the digital interface controls the tap switches which select the appropriate attenuation
level. As depicted in Figure 3, the LOAD/SHIFT line is to go low at least 150 ns before the rising edge of the first
clock pulse and is to remain low throughout the transmission of each set of 16 data bits. The serial data is
comprised of 8 bits for channel selection and 8 bits for attenuation setting. For both address data and attenuation
setting data, the MSB is sent first and the 8 bits of address data are to be sent before the 8 bits of attenuation
data. Please refer to Figure 20 to confirm the serial data format transfer process.
Table 1. LM1972 Micropot Attenuator
Register Set Description
MSB: LSB
Address Register (Byte 0)
0000 0000 Channel 1
0000 0001 Channel 2
0000 0010 Channel 3
Data Register (Byte 1)
Contents Attenuation Level dB
0000 0000 0.0
0000 0001 0.5
0000 0010 1.0
0000 0011 1.5
::::: ::
0001 1110 15.0
0001 1111 15.5
0010 0000 16.0
0010 0001 16.5
0010 0010 17.0
::::: ::
0101 1110 47.0
0101 1111 47.5
0110 0000 48.0
0110 0001 49.0
0110 0010 50.0
::::: ::
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Table 1. LM1972 Micropot Attenuator
Register Set Description (continued)
MSB: LSB
0111 1100 76.0
0111 1101 77.0
0111 1110 78.0
0111 1111 100.0 (Mute)
1000 0000 100.0 (Mute)
::::: ::
1111 1110 100.0 (Mute)
1111 1111 100.0 (Mute)
Figure 20. Serial Data Format Transfer Process
μPot SYSTEM ARCHITECTURE
The μPot's digital interface is essentially a shift register, where serial data is shifted in, latched, and then
decoded. As new data is shifted into the DATA-IN pin, the previously latched data is shifted out the DATA-OUT
pin. Once the data is shifted in, the LOAD/SHIFT line goes high, latching in the new data. The data is then
decoded and the appropriate switch is activated to set the desired attenuation level for the selected channel. This
process is continued each and every time an attenuation change is made. Each channel is updated, only, when
that channel is selected for an attenuator change or the system is powered down and then back up again. When
the μPot is powered up, each channel is placed into the muted mode.
μPot LADDER ARCHITECTURE
Each channel of a μPot has its own independent resistor ladder network. As shown in Figure 21, the ladder
consists of multiple R1/R2 elements which make up the attenuation scheme. Within each element there are tap
switches that select the appropriate attenuation level corresponding to the data bits in Table 1. It can be seen in
Figure 21 that the input impedance for the channel is a constant value regardless of which tap switch is selected,
while the output impedance varies according to the tap switch selected.
Figure 21. μPot Ladder Architecture
DIGITAL LINE COMPATIBILITY
The μPot's digital interface section is compatible with either TTL or CMOS logic due to the shift register inputs
acting upon a threshold voltage of 2 diode drops or approximately 1.4V.
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DIGITAL DATA-OUT PIN
The DATA-OUT pin is available for daisy-chain system configurations where multiple μPots will be used. The use
of the daisy-chain configuration allows the system designer to use only one DATA and one LOAD/SHIFT line per
chain, thus simplifying PCB trace layouts.
In order to provide the highest level of channel separation and isolate any of the signal lines from digital noise,
the DATA-OUT pin should be terminated through a 2 kΩresistor if not used. The pin may be left floating,
however, any signal noise on that line may couple to adjacent lines creating higher noise specs.
Figure 22. μPot System Architecture
DAISY-CHAIN CAPABILITY
Since the μPot's digital interface is essentially a shift register, multiple μPots can be programmed utilizing the
same data and load/shift lines. As shown in Figure 24, for an n-μPot daisy-chain, there are 16n bits to be shifted
and loaded for the chain. The data loading sequence is the same for n-μPots as it is for one μPot. First the
LOAD/SHIFT line goes low, then the data is clocked in sequentially while the preceding data in each μPot is
shifted out the DATA-OUT pin to the next μPot in the chain or to ground if it is the last μPot in the chain. Then
the LOAD/SHIFT line goes high; latching the data into each of their corresponding μPots. The data is then
decoded according to the address (channel selection) and the appropriate tap switch controlling the attenuation
level is selected.
CROSSTALK MEASUREMENTS
The crosstalk of a μPot as shown in the Typical Performance Characteristics was obtained by placing a signal on
one channel and measuring the level at the output of another channel of the same frequency. It is important to
be sure that the signal level being measured is of the same frequency such that a true indication of crosstalk
may be obtained. Also, to ensure an accurate measurement, the measured channel's input should be AC
grounded through a 1 μF capacitor.
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CLICKS AND POPS
So, why is that output buffer needed anyway? There are three answers to this question, all of which are
important from a system point of view.
The first reason to utilize a buffer/amplifier at the output of a μPot is to ensure that there are no audible clicks or
pops due to attenuation step changes in the device. If an on-board bipolar op amp had been used for the output
stage, its requirement of a finite amount of DC bias current for operation would cause a DC voltage “pop” when
the output impedance of the μPot changes. Again, this phenomenon is due to the fact that the output impedance
of the μPot is changing with step changes and a bipolar amplifier requires a finite amount of DC bias current for
its operation. As the impedance changes, so does the DC bias current and thus there is a DC voltage “pop”.
Secondly, the μPot has no drive capability, so any desired gain needs to be accomplished through a buffer/non-
inverting amplifer.
Third, the output of a μPot needs to see a high impedance to prevent loading and subsequent linearity errors
from ocurring. A JFET input buffer provides a high input impedance to the output of the μPot so that this does not
occur.
Clicks and pops can be avoided by using a JFET input buffer/amplifier such as an LF412ACN. The LF412 has a
high input impedance and exhibits both a low noise floor and low THD+N throughout the audio spectrum which
maintains signal integrity and linearity for the system. The performance of the system solution is entirely
dependent upon the quality and performance of the JFET input buffer/amplifier.
LOGARITHMIC GAIN AMPUFIER
The μPot is capable of being used in the feedback loop of an amplifier, however, as stated previously, the output
of the μPot needs to see a high impedance in order to maintain its high performance and linearity. Again, loading
the output will change the values of attenuation for the device. As shown in Figure 23, a μPot used in the
feedback loop creates a logarithmic gain amplifier. In this configuration the attenuation levels from Table 1, now
become gain levels with the largest possible gain value being 78dB. For most applications 78dB of gain will
cause signal clipping to occur, however, because of the μPot's versatility the gain can be controlled through
programming such that the clipping level of the system is never obtained. An important point to remember is that
when in mute mode the input is disconnected from the output. In this configuration this will place the amplifier in
its open loop gain state, thus resulting in severe comparator action. Care should be taken with the programming
and design of this type of circuit. To provide the best performance, a JFET input amplifier should be used.
Figure 23. Digitally-Controlled Logarithmic Gain Amplifier Circuit
Figure 24. n-μPot Daisy-Chained Circuit
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM1972M/NOPB ACTIVE SOIC DW 20 36 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR 0 to 70 LM1972M
LM1972MX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR 0 to 70 LM1972M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM1972MX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM1972MX/NOPB SOIC DW 20 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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