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FEATURES
APPLICATIONS
P0021-02
PWP HTSSOP PACKAGE
(TOP VIEW)
SCR1
Cboot2
Cboot1
V
L1
PGND
L2
V
5
A
driver
OUT
Vg
IN
SCR0
5Vg_ENABLE
ENABLE
V
GND
R
REST
A
RESET
CLP
logic
mod
OUT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DESCRIPTION
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
•Switched 5-V Regulated Output on 5Vg WithCurrent Limit•Switch-Mode Regulator
•Programmable Slew Rate and Frequency– 5 V ±2%, Normal Mode
Modulation for EMI Consideration– 5 V ±3%, Low-Power or Crossover Mode
•Reset Function With Deglitch Timer and•Switching Frequency, 440 kHz (typical)
Programmable Delay•Input Operating Range, 1.5 V to 40 V, (V
driver
)
•Alarm Function for Undervoltage Detection– 1-A Load-Current Capability
and Indication– 200-mA Load-Current Capability Down to
•Thermally Enhanced Package for Efficient2-V Input (V
driver
)
Heat Management– 120-mA Load-Current Capability Down to1.5-V Input (V
driver
)•Enable Function
•Automotive Electronic Controller PowerSupply•Low-Power Operation Mode
The TPIC74100-Q1 is a switch-mode regulator with integrated switches for voltage-mode control. With the aid ofexternal components (LC combination), the device regulates the output to 5 V ±3% for a wide input-voltagerange.
The TPIC74100-Q1 offers a reset function to detect and indicate when the 5-V output rail is outside of thespecified tolerance. This reset delay is programmable using an external timing capacitor on the REST terminal.Additionally, an alarm (A
OUT
) feature is activated when the input supply rail V
driver
is below a prescaled specifiedvalue (set by the A
IN
terminal).
The TPIC74100-Q1 has a frequency-modulation scheme to minimize EMI. The clock modulator permits amodulation of the switching frequency to reduce interference energy in the frequency band.
The 5Vg output is a switched 5-V regulated output with internal current limiting to prevent RESET from beingasserted when powering a capacitive load on the supply line. This function is controlled by the 5Vg_ENABLEterminal. If there is a short to ground on this output (5Vg output), the output self-protects by operating in achopping mode. This does, however, increase the output ripple voltage on V
OUT
during this fault condition.
Ordering Information
Part Number Package
TPIC74100QPWPRQ1 R-PDSO-G (PWP, 20-pin)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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B0130-01
Switch-Mode
ControllerWith
Dead Time
Charge
Pump
Vref
Bandgap
Ref
Vreg Osc
+
-
+
-
PORWith
Delay Timer
Vdriver
ENABLE
GND
L1
5VSupply
5Vg_Supply
-
+
L2
VOUT
Q1
Q2
Q3
Q4
RESET
Temp
Monitor
Shutdown
Regulator
Rmod Clock
Modulator
Cboot1
Cboot2
5Vg_ENABLE
AOUT
REST
PGND
SCR0
SCR1
SlewRate
Control
5Vg
Low-Power
Mode
Control
CLP
Inrush
CurrentLimit
4.7nF
22 H–
100 H
m
m
4.7nF
5kW
12kW
R1
R2
L
C
470nF
2.2nF–150nF
Charge
Pump
Bandgap
Ref
Vlogic
AIN
Vbattery
22µF–470µF
1µF–100µF
ExternalSchottky
DiodeRequired,
Max.0.4V
@1 A
@125ºC
Low-PowerMode
DigitalSignal 5kW
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
NOTE: All component values are typical.
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TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
Table 1. Terminal Functions
TERMINAL
DESCRIPTIONNAME NO. I/O
SCR1 1 I Programmable slew-rate controlCboot2 2 I External bootstrap capacitorCboot1 3 I External bootstrap capacitorV
driver
4 I Input voltage sourceL1 5 I Inductor input (an external Schottky diode
(1)
to GND must be connected to L1)PGND 6 I Power groundL2 7 I Inductor outputV
OUT
8 O 5-V regulated output5Vg 9 O Switched 5-V supplyA
IN
10 I Programmable alarm settingCLP 11 I/O Low-power operation mode (digital input)RESET 12 O Reset function (open drain)A
OUT
13 O Alarm output (open drain)REST 14 O Programmable reset timer delayR
mod
15 I Main switching frequency modulation setting to minimize EMIGND 16 I GroundV
logic
17 O Supply decoupling output (may be used as a 5-V supply for logic-level inputs)ENABLE 18 I Switch-mode regulator enable/disable5Vg_ENABLE 19 I Switched 5-V voltage regulator output enable/disableSCR0 20 I Programmable slew-rate controlExposed thermal pad of the package should be connected to GND or left floating.
(1) Maximum 0.4 V @ 1 A @ 125°C
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
over recommended operating free-air temperature range (unless otherwise noted)
(1)
Unregulated input voltage, V
(driver)
(2)
–0.5 V to 40 VUnregulated inputs, V
(AIN)
, V
(ENABLE)
(2)
–0.5 V to 40 VBootstrap voltages V
(Cboot1)
52 VV
(Cboot2)
14 VSwitch mode voltages V
(L1)
–1 V to 40 VV
(L2)
–1 V to 7 VLogic input voltages, V
(Rmod)
,V
(SCR0)
,V
(SCR1)
,V
(CLP)
, and V
(5Vg_ENABLE)
(2)
–0.5 V to 7 VLow output voltages, V
(RESET)
,V
(AOUT)
,V
(logic)
, and V
(REST)
(2)
–0.5 V to 7 VElectrostatic-discharge V
(HBMESD)
(3)
, pin 7 (L2), pin 8 (V
OUT
), pin 9 (5Vg) 800 Vsusceptibility
V
(HBMESD)
(3)
, pins 1–6 and 10–20 2 kVThermal impedance, junction-to-case, R
θJC
(4)
2°C/WThermal impedance, R
θJA
(4)
32°C/Wjunction-to-ambient
R
θJA
(5)
40°C/WContinuous power dissipation, P
D
See Dissipation
Rating TableOperating virtual junction temperature range, T
J
–40°C to 150°COperating ambient temperature range, T
A
–40°C to 125°CStorage temperature range, T
stg
–65°C to 125°CLead temperature (soldering, 10 s), T
(LEAD)
260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to ground.(3) The human body model is a 100-pF capacitor discharged through a 1.5-k Ωresistor into each terminal.(4) The thermal data is based on using 2-oz. copper trace with at least four square inches of copper footprint for heat dissipation. Thecopper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.(5) The thermal data is based on using 1-oz. copper trace with at least four square inches of copper footprint for heat dissipation. Thecopper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
R
θJA
T
A
≤25°C Power Rating Derating Factor Above T
A
= 25°C T
A
= 85°C Power Rating T
A
= 125°C Power Rating
32°C/W 3.9 W 31.25 mW/°C 2.03 W 0.781 W40°C/W 3.125 W 25 mW/°C 1.625 W 0.625 W
MIN MAX UNIT
Unregulated input voltage, V
(driver)
6 24 VUnregulated input voltages, V
(AIN)
and V
(ENABLE)
0 24 VV
(L1)
–1 17Switch-mode terminals VV
(L2)
5 5.5V
(Cboot1)
V
(driver)
+ 10Bootstrap voltages VV
(Cboot2)
8Logic levels (I/O), V
(Rmod)
, V
(logic)
,V
(SCR0)
,V
(SCR1)
,V
(5Vg_ENABLE)
,V
(RESET)
, V
(AOUT)
, V
(CLP)
, and
0 5.25 VV
(REST)
Operating ambient temperature range, T
A
–40 125 °CLogic levels (I/O), V
(SCR0)
, V
(SCR1)
, V
(CLP)
directly connected to V
(logic)
V
(logic)
V
(logic)
V
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ELECTRICAL CHARACTERISTICS
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
V
(driver)
= 6 V to 17 V, T
A
= -40°C to 125°C, unless otherwise noted
Parameters TEST CONDITIONS Min Typ Max Unit
V
(driver)
Unregulated input voltage 1.5 40 VV
(driver)
Start-up condition voltage I
O
= 600 mA 5 VC
O
= 36 µF (min) to 220 µF (max) 4 20S
OM
Soft-start ramp V/msC
O
= 220 µF (min) to 470 µF (max), see
2 20Note
(1)
I
(standby)
Standby current ENABLE = low 10 20 µAI
q
Quiescent current CLP = 0 V, V
(driver)
= 11 V, I
O
= 0 mA 100 160 µAV
O
Output voltage DC 5 VNormal mode 2%V
O
Output-voltage tolerance
Boost/buck crossover or low-power
3%modeI
O
Output current V
(driver)
≥7 V 1 AV
(driver)
= 2 V, see Note
(2)
200I
O(Boost)
Output current, boost mode mAV
(driver)
= 1.5 V, see Note
(2)
120Internal peak current limit (normalI
PPn
(1)
1.75 2.5 Amode)
Internal peak current limit (low-powerI
PPl
(1)
0.75 1.25mode)I
P
Peak current V
(driver)
= 16 V, I
O
= 1 A, and L = 33 µH 1.5 ABoost/buck crossover voltageV
(driver)
See Note
(3)
5 5.9 VwindowT
ot
Thermal shutdown
(4)
160 180 200 °C
5Vg Output and ENABLE
r
DS(on)
On-state resistance 135 225 m ΩI
O
Output current 400 mAV
I
5Vg_ENABLE input-voltage range –0.5 V
O
VV
IH
5Vg_ENABLE threshold high voltage V
(5Vg)
= 5 V 2.5 3 3.5 VV
IL
5Vg_ENABLE threshold low voltage V
(5Vg)
= 0 V 1.5 2 2.5 VV
(hys)
Hysteresis voltage 0.5 1 Vr
(pd)
Internal pulldown resistor 300 500 850 k Ω
ENABLE
V
I
ENABLE input-voltage range –0.5 40 V8 V ≤V
(driver)
≤17 V 2.5 3 3.5V
IH
ENABLE threshold high voltage V6 V ≤V
(driver)
< 8 V 1.9 3 3.5V
IL
ENABLE threshold low voltage V
O
= 5 V 1.5 2 2.5 V8 V ≤V
(driver)
≤17 V 0.5 1V
(hys)
Hysteresis voltage V6 V ≤V
(driver)
< 8 V 0.1
(1) Ensured by characterization.(2) Tested with inductor having following characteristics: L = 33 µH, R
max
= 0.1 Ω, I
R
= 1.8 A. Output current must be verified in applicationwhen inductor R
max
(ESR) is increased.(3) Ensured by characterization. For further details, see the Buck/Boost Transitioning section.(4) Ensured by characterization; hysteresis 15°C (typical)
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TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)V
(driver)
= 6 V to 17 V, T
A
= -40°C to 125°C, unless otherwise noted
Parameters TEST CONDITIONS Min Typ Max Unit
RESET
V
(th)
RESET threshold voltage 4.51 4.65 4.79 VV
(RESET)
RESET tolerance 3%C
(REST)
= 10 nF 8 10 12t
(RESET)
RESET time msC
(REST)
= 100 nF, see Note
(5)
80 100 120I
sink
= 5 mA 450V
OL
RESET output low voltage mVI
sink
= 1 mA 84t
(deglitch)
RESET deglitch time See Note
(5)
8 10 12.5 µs
Alarm
V
I
Alarm input-voltage range –0.5 40 VV
IL
Alarm threshold low voltage 2.2 2.3 2.35 VV
IH
Alarm threshold high voltage 2.43 2.5 2.58 VV
(hys)
Hysteresis voltage 200 mVI
sink
= 5 mA 450V
OL
Alarm output low voltage mVI
sink
= 1 mA 84
Low-Power Mode (Pulse Mode) PFM
I
O(LPM)
Load current in low-power mode V
(driver)
< 7 V 50 mAI
I(avg)
Average input current V
(driver)
= 11 V, I
O
= 5 mA, CLP = low 3.55 mAV
O
Output-voltage tolerance V
O
= 5 V 2.4% 3%
Digital Low-Power Mode (CLP)
High-level CLP input thresholdV
IH
Normal mode 2.6 Vvoltage
Low-level CLP input thresholdV
IL
Low-power mode 1.15 Vvoltage
Switching Parameters
f
(sw)
Switching frequency V
(Rmod)
= 0 V, modulator OFF 440 kHzf
(sw)
= 440 kHz 18%f
(sw)ac
Operating-frequency accuracy
f
(sw)
= 440 kHz 20%f
(sw)min
Modulation minimum frequency 270 330 445 kHzf
(sw)max
Modulation maximum frequency 450 550 680 kHzf
(mod)span
Modulation span 220 kHzf
(mod)
Modulation frequency R
mod
= 12 k Ω±1% 28 kHzf
(mod)ac
Modulation-frequency accuracy 12%
(5) Ensured by characterization.
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PRINCIPLES OF OPERATION
Functional Principle
Description of the Functional Terminals
Switch-Mode Input/Output Terminals (L1, L2)
Supply Terminal (V
driver
)
mode, the RMS current is
IOUT D*D2
Ǹ
, where D is the duty cycle and its maximum RMS current value is
Internal Supply Decoupling Terminal (V
logic
)
Input Voltage Monitoring Terminal (A
IN
)
Upper:
Lower:
V =2.5V×
(driver)
R1+R2
R1
V =2.3V×
(driver)
R1+R2
R1
.
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
The TPIC74100-Q1 is a buck/boost switch-mode regulator that operates in a power-supply concept to ensure astable output voltage with input voltage excursions and specified load range.
The device provides an alarm indicator and reset output to interface with systems that require supervisoryfunction.
The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switchingtransistor (Q1) to minimize EMI.
An internal low-r
DS(on)
switch has a current-limit feature to prevent inadvertent reset when turning on the 5Vgoutput.
The external inductor for the switch-mode regulator is connected between terminals L1 and L2. This inductor isplaced close to the terminals to minimize parasitic effects. For stability, an inductor with 20 µH to 100 µH shouldbe used.
The input voltage of the device is connected to the V
driver
terminal. This input line requires a filter capacitor tominimize noise. A low-ESR aluminum or tantalum input capacitor is recommended. The relevant parameters forthe input capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately1.5 times the maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck
reached when D = 50% with I
RMS
= I
OUT
/2. In boost mode, the RMS current is 0.3 × ∆I, where ∆I is thepeak-to-peak ripple current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with thealuminum or tantalum capacitors.
The V
logic
terminal is used to decouple the internal power-supply noise by use of a 470-nF capacitor. Thisterminal can also be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE,CLP, and 5Vg_ENABLE).
The A
IN
terminal is used to program the threshold voltage for monitoring and detecting undervoltage conditionson the input supply. A maximum of 40 V may be applied to this terminal and the voltage at this terminal mayexceed the V
(driver)
input voltage without effecting the device operation. The resistor divider network isprogrammed to set the undervoltage detection threshold on this terminal (see the application schematic). Theinput has a typical hysteresis of 200 mV with a typical upper limit threshold of 2.5 V and a typical lower limitthreshold of 2.3 V. When V
(AIN)
falls below 2.3 V, V
(AOUT)
is asserted low; when V
(AIN)
exceeds 2.5 V, V
(AOUT)
is inthe high-impedance state.
The equations to set the upper and lower thresholds of V
(AIN)
are:
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Input Undervoltage Alarm Terminal (A
OUT
)
Reset Delay Timer Terminal (REST)
Reset Terminal (RESET)
Main Regulator Output Terminal (V
OUT
)
Low-Power-Mode Terminal (CLP)
Switch-Output Terminal (5Vg)
5Vg-Enable Terminal (5Vg_ENABLE)
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
The A
OUT
terminal is an open-drain output that asserts low when the input voltage falls below the set thresholdon the A
IN
input.
The REST terminal sets the desired delay time to assert the RESET terminal low after the 5-V supply hasexceeded 4.65 V (typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors inthe range of 2.2 nF to 150 nF. The delay time is calculated using the following equation:RESET delay = C
(REST)
× 1 ms, where C
(REST)
has nF units
The RESET terminal is an open-drain output. The power-on reset output is asserted low until the output voltageexceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLEterminal is low, RESET is immediately asserted low regardless of the output voltage.
The V
OUT
terminal is the output of the switch-mode regulated supply. This terminal requires a filter capacitor withlow-ESR characteristics to minimize output ripple voltage. For stability, a capacitor with 22 µF to 470 µF shouldbe used. The total capacitance at pin V
OUT
and pin 5Vg must be less than or equal to 470 µF.
The CLP terminal controls the low-power mode of the device. An external low digital signal switches the deviceto low-power mode or normal mode when the input is high.
The 5Vg terminal switches the 5-V regulated output. The output voltage of the regulator can be enabled ordisabled using this low-r
DS(on)
internal switch. This switch has a current-limiting function to prevent generation ofa reset signal at turnon caused by the capacitive load on the output or overload condition. When the switch isenabled, the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor isfully charged. This deviation depends on the characteristics of the capacitors on V
OUT
and 5Vg.
The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg.
For the functional terminal, 5Vg_ENABLE results in the following table:5Vg_ENABLE Function
0 5Vg is offOpen (internal pulldown = 500 k Ω) 5Vg is off1 5Vg is on
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S0174-01
5Vg_ENABLE
Switch
Control
PeakCurrentLimit
Gate
Driver
5Vg
Q1
Q2
Q3
Q4
Vdriver
L1 L2
33µH
VOUT
VOUT
47µF
100µF
5Vg
SlewRateControl
RESET
ChargePump
RESET Deglitch
RESET
typ~V – 100mV
OUT
VOUT
typ4.65V
Buck/Boost
GateDriver
Slew-Rate Control Terminals (SCR0, SCR1)
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
Figure 1. Current-Limit Switched Output 5Vg
The slew rate of the switching transistor Q1 is set using the SCR0 and SCR1 terminals.
The following table shows the values of the slew rate (SR):SCR1 SCR0 SR
Q1
0 0 Slow0 1 Medium-slow1 0 Medium-fast1 1 Fast
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Modulator Frequency Setting (Terminal R
mod
)
Ground Terminal (PGND)
Enable Terminal (ENABLE)
Bootstrap Terminals (Cboot1 and Cboot2)
Functional Modes
Clock Modulator
Buck/Boost Transitioning
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
See the converter efficiency plots in the Typical Characteristics section to determine power dissipation.
The R
mod
terminal adjusts the clock modulator frequency. A resistor of R
mod
= 12 k Ωgenerates a modulationfrequency of 28 kHz. The modulator function may be disabled by connecting R
mod
to GND and the deviceoperates with the nominal frequency. The modulator function cannot be activated during IC operation, only at ICstart-up.
The PGND terminal is the power ground for the device.
The ENABLE terminal allows the enabling and disabling of the switch mode regulator. A maximum of 40 V maybe applied to this terminal to enable the device and increasing it above the V
(driver)
input voltage does not affectthe device operation.
The functionality of the ENABLE terminal is described in the following table:ENABLE Function
0 Vreg is off.Open Undefined1 Vreg is on.
An external bootstrap capacitor is required for driving the internal high-side MOSFET switch. A 4.7-nF ceramiccapacitor is typically required.
To minimize EMI issues associated with the switch-mode regulator, the device offers an integrated clockmodulator. The function of the clock modulator is to modulate the switching frequency and to distribute theenergy over the wave band.
The average switching frequency is 440 kHz (typical) and varies between 330 kHz and 550 kHz at a rate set bythe R
mod
resistor. A typical value of 12 k Ωon the R
mod
terminal relates to a 28-kHz modulation frequency. Theclock modulator function can only be activated during IC start-up, not during IC operation.
The equation for the modulation frequency is as follows:
f
(mod)
(Hz) = (–2.2 × R
mod
) + 54.5 kHz, when R
mod
= 8 k Ωto 16 k Ω
The operation mode switches automatically between buck and boost modes depending on the input voltage ofV
(driver)
and output load conditions. During start up, when V
(driver)
is less than 5.8 V (typical), the device starts inboost mode and continues to run in boost mode until V
(driver)
exceeds 5.8 V; at which time, the device switchesover to buck mode. In buck mode, the device continues to run in buck mode until it is required to switch back toboost to hold regulation. This crossover window to switch to boost mode is when V
(driver)
is between 5.8 V and5 V and depends on the loading conditions. When V
driver
drops below 5.8 V but the device is holding regulation(~2%), the device remains in buck mode. However, when V
(driver)
is within the 5.8-V to 5-V window and V
OUTdrops to 4.9 V, the device crosses over to boost mode to hold regulation. In boost mode, the device remains inboost mode until V
(driver)
exceeds 5.8 V; at which time, the device enters the buck mode. When the device is
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Buck SMPS
S0182-01
Switch
Control
Current
Control
FB
SMPS
Q1
Q2
Q3
Q4
Input
Voltage
L1
L2
33µH
Vdriver
VOUT
22µF–470µF
Boost SMPS
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
operating in boost mode and V
(driver)
is in the crossover window of 5.8 V to 5 V, the output regulation maycontain a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on theloading and improves with a higher loading condition. When the device is operated with low-power mode active(CLP = low) and high output currents (>50 mA), the buck/boost transitioning can cause a reset signal at theRESET pin.
In buck mode, the duty cycle of transistor Q1 sets the voltage V
OUT
. The duty cycle of transistor Q1 varies 10%to 99% depending on the input voltage, V
(driver)
. If the peak inductor current (measured by Q1) exceeds 450 mA(typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates throughQ2 as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle.
To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1off and Q2 on and vice versa.
In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce powerdissipation.
The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of thetransistors does not change.
Figure 2. Buck/Boost Switch Mode Configuration
In boost mode, the duty cycle of transistor Q3 controls the output voltage V
OUT
. The duty cycle is internallyadjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurswhen V
(driver)
is below 5 V.
To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. Aninherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa.
In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of theboost-mode operation (serves as a supply line).
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Extension of the Input Voltage Range on V
(driver)
Low-Power Mode
Temperature and Short-Circuit Protection
Switch Output Terminal (5Vg) Current Limitation
Soft Start
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
The switch timings of transistors Q1 and Q2 are not considered. In boost mode, the logical control of thetransistors does not change.
To ensure a stable 5-V output voltage with the output load in the specified range, the V
(driver)
supply must begreater than or equal to 5 V for greater than 1 ms (typical). After a period of 1 ms (typical), the logic may besupplied by the V
OUT
regulator and the V
(driver)
supply may be capable of operating down to 1.5 V.
The switch-mode regulator does not start at V
(driver)
less than 5 V.
To reduce quiescent current and to provide efficient operation, the regulator enters a pulsed mode.
The device enters this mode by a logic-level low on this terminal.
Automatic low-power mode is not available.The low-power-mode function is not available in boost mode. Thedevice leaves low-power mode during boost mode regardless of the logic level on the CLP terminal.
To prevent thermal destruction, the device offers overtemperature protection to disable the IC. Also, short-circuitprotection is included for added protection on V
OUT
and 5Vg.
A charge pump drives the internal FET, which switches the primary output voltage V
OUT
to the 5Vg pin.Protection is implemented to prevent the output voltage from dropping below its specified value while enablingthe secondary output voltage. An explanation of the block diagram (see Figure 1) is given by the followingexample:
•Device is enabled, output voltage V
OUT
is up and stable.•5Vg is enabled (pin 5Vg_ENABLE set to high) with load resistance connected to 5Vg pin.•If output voltage V
OUT
drops below typical ( V
OUT
– 100 mV), the charge pump of the 5Vg FET is switched offand the FET remains on for a while as the gate voltage drops slowly.•If V
OUT
drops below the RESET threshold of 4.65 V (typical), the FET of the secondary output voltage 5Vg isswitched off (gate drawn to ground level).•A deglitch time ensures that a device reset does not occur if V
OUT
drops to the reset level during the 5Vgturnon phase.•If V
OUT
rises above typical (V
OUT
– 100 mV), the charge pump of the 5Vg FET is switched on and drives thegate of the 5Vg FET on.
On power up, the device offers a soft-start feature which ramps the output of the regulator at a slew of 10 V/ms.When a reset occurs, the soft start is reenabled. Additionally, if the output capacitor is greater than 220 µF(typical), the slew rate decreases to a value set by the internal current limit. In boost mode, the soft-start featureis not active.
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TYPICAL CHARACTERISTICS
IO − Output Current − mA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
II − Input Current − mA
G002
TA = 125°
TA = 25°
Maximum
V(driver) = 11 V
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
NOTE: Maximum characteristic specified by design.
Figure 3. Low-Power Mode Current, I
O
= 0 mA–10 mA
NOTE: Maximum characteristic specified by design.
Figure 4. Low-Power-Mode Current, I
O
= 0 mA–1 mA
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VI − Input Voltage − V
0
100
200
300
400
500
600
700
800
900
1000
1100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IO − Output Current − mA
G003
TA = 25°
TA = 125°
IO − Output Current − mA
50
55
60
65
70
75
80
85
100 150 200 250 300 350 400 450 500 550 600
Efficiency − %
G004
SCR: 11, V(driver) = 11 V
SCR: 10, V(driver) = 11 V
SCR: 01, V(driver) = 11 V
SCR: 00, V(driver) = 11 V
SCR: 11, V(driver) = 17 V
SCR: 10, V(driver) = 17 V
SCR: 01, V(driver) = 17 V
SCR: 00, V(driver) = 17 V
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
NOTES:
(1) Typical representation of input voltage vs output load current at T
A
= 25°C and 125°C, after the correct power-up sequence isinvoked.
(2) The dip in the output current at 5.8 V is caused by the buck/boost transition of the IC.(3) The output current is clipped to 1 A by the measurement setup.Figure 5. Typical Input Voltage (V
(driver)
)vsMaximum Output Load Current (I
O
)
NOTE: The average converter efficiency with four different slew rate controls (SCRx) on the Q1 switching FET with input voltageV
(driver)
= 11 V and 17 V, T
A
= 125°C.
Figure 6. Converter Efficiency
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V(L1)
InputCurrent
(200mA/div)
G005
G010
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 7. Input Current With Slope Control, SCR0 = 0, SCR1 = 0,Input-Current Slew Rate = 2.8 A/µs, I
L
= 500 mA, V
(driver)
= 15 V
Figure 8. Input Current With Slope Control, SCR1 = 0, SCR0 = 1,Input-Current Slew Rate = 6.25 A/µs, I
L
= 500 mA, V
(driver)
= 15 V
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G011
G008
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 9. Input Current With Slope Control, SCR1 = 1, SCR0 = 0,Input-Current Slew Rate = 9.4 A/µs, I
L
= 500 mA, V
(driver)
= 15 V
Figure 10. Input Current With Slope Control, SCR0 = 1, SCR1 = 1,Input-Current Slew Rate = 18.8 A/µs, I
L
= 500 mA, V
(driver)
= 15 V
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G009
G012
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 11. Low-Power-Mode Operation, I
L
= 15 mA, C
O
= 47 µF
Figure 12. Nominal Switching Frequency of Q1 Switch (446 kHz)
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G013
G006
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)With Modulation Function Disabled, I
L
= 200 mA
(Reference L1 Terminal, see Figure 13 through Figure 15 )
Figure 13. Minimum Switching Frequency (333 kHz)With Modulation Enabled, R
mod
= 12 k Ω, I
L
= 200 mA
Figure 14. Maximum Switching Frequency (555 kHz)With Modulation Enabled, R
mod
= 12 k Ω, I
L
= 200 mA
18
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G007
VO
11V,IL =700mA
5V,IL =700mA
2V,IL =225mA
V(driver)
G014
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)(Reference L1 Terminal, see Figure 13 through Figure 15 )
Figure 15. Modulation Frequency (Full Span) of 28 kHz
Figure 16. Input Voltage Excursions (Similar to Low-Crank Conditions)
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G015
G016
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)(Reference L1 Terminal, see Figure 13 through Figure 15 )
Figure 17. Switch-Mode Regulator Transition From Buck Mode to Boost Mode, I
L
= 400 mA
Figure 18. Switch-Mode Regulator Transition From Boost Mode to Buck Mode, I
L
= 400 mA
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L O G 1 0 d B /d iv
ModulationOff
Modulation=28kHz
G017
L O G 1 0 d B / d iv
SlewRate=11
SlewRate=00
G018
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)(Reference L1 Terminal, see Figure 13 through Figure 15 )
NOTE: These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatlydepending on board layout and external components and must be verified in actual application.Figure 19. Conducted Emissions on Test Board Showing Effects of Switching-Frequency Modulation
NOTE: These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatlydepending on board layout and external components and must be verified in actual application.Figure 20. Conducted Emissions on Test Board Showing Effects of Minimum and Maximum Slew Rate Settings
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APPLICATION INFORMATION
M0026-01
PackageThermalPad
SolderPad(LandPattern)
ThermalVias
PackageOutline
M0027-01
PowerPad
PackageSolderPad
PackageSolderPad
(BottomTrace)
ThermalVia
ComponentTraces
ThermalIsolation
PowerPlaneOnly
1,5748mm
0-mm 0,071-mmBoard
Base
–
andBottomPad
0,5246-mm 0,5606-mm–
PowerPlane
(1-oz.Cu)
1,0142-mm 1,0502-mm–
GroundPlane
(1-oz.Cu)
1,5038-mm 1,5748-mm–
ComponentTrace
(2-oz.Cu)
2Plane
4Plane
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelinesmust be followed when laying out this device on the PCB.
The following information is to be used as a guideline only.
For further information see the PowerPAD Thermally Enhanced Package technical brief (SLMA002 ).
The following are guidelines for mounting the PowerPAD™ IC on a multilayer PCB with a ground plane.
Figure 21. Package and PCB Land Configuration for a Multilayer PCB
Figure 22. Multilayer Board (Side View)
In a multilayer board application, the thermal vias are the primary method of heat transfer from the packagethermal pad to the internal ground plane.
The efficiency of this method depends on several factors (die area, number of thermal vias, thickness of copper,etc.). See the PowerPAD Thermally Enhanced Package technical brief (SLMA002).
22
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M0028-01
UseasMuchCopper Area
asPossibleforHeatSpread
PackageThermalPad
PackageOutline
IMPORTANT
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
APPLICATION INFORMATION (continued)
Figure 23. Land Configuration for Single-Layer PCB
Layout recommendation is to use as much copper area for the power-management section of a single-layerboard as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copperareas) by using a low-thermal-impedance attachment method (solder paste or thermal-conductive epoxy). Inboth of these cases, it is advisable to use as much copper and as many traces as possible to dissipate the heat.
When this attachment method is not implemented correctly, this product may operate inefficiently. Power dissipation capabilitymay be adversely affected when the device is incorrectly mounted onto the circuit board.
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S0183-01
GND
Rmod
REST
AIN
Vdriver
Cboot2
Cboot1
L1 L2
VOUT
PGND
RESET
SCR1
SCR0
TPIC74100B
ENABLE
Vlogic
AOUT
5V
Vbattery
5V
5Vg_ENABLE
5Vg 5V
CLP
4.7nF4.7nF
L
CR2
R1
470nF
2.2nF–150nF
Optional
Connection
5kW
5kW
1 µF–100µF
22µF–470µF
12 kW
22µH–100µH
Layout Guidelines for Switch-Mode Power Supply
Inductor
Filter Capacitors
Traces and Ground Plane
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
A. To minimize voltage ripple on the output due to transients, it is recommended to use a low-ESR capacitor on theV
OUT
line.B. The L and C component values are system application dependent for EMI consideration.
Figure 24. Application Schematic
The following guidelines are recommended for PCB layout of the TPIC74100-Q1 device.
Use a low-EMI inductor with a ferrite-type closed core. Other types of inductors may be used; however, theymust have low-EMI characteristics and be located away from the low-power traces and components in thecircuit.
Input ceramic filter capacitors should be located in the close proximity of the V
driver
terminal. Surface-mountcapacitors are recommended to minimize lead length and reduce noise coupling.
All power (high-current) traces should be thick and as short as possible. The inductor and output capacitorsshould be as close to each other as possible. This reduces EMI radiated by the power traces due to highswitching currents.
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Buck Mode
L+ǒVIN *VOUTǓ VOUT
fSW DIL VIN
(1)
IL,max +IOUT )DIL
2
(2)
DVOUT +DIL ǒESR)1
8 fSW COUTǓ
(3)
COUT +Ipk(ton )toff)
8 Vripple
(4)
Boost Mode
L+ǒVOUT *VINǓ VIN
fSW DIL VOUT
(5)
Ip+IL,max +IIN )DIL
2
(6)
DVOUT +Ip ESR)
IOUT ǒ1*VIN
VOUTǓ
fSW COUT
(7)
TPIC74100-Q1BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
In a two-sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noiseand ground-loop errors. The ground connection for the input and output capacitors and IC ground should beconnected to this ground plane.
In a multilayer PCB, the ground plane is used to separate the power plane (where high switching currents andcomponents are placed) from the signal plane (where the feedback trace and components are) for improvedperformance.
Also, arrange the components such that the switching-current loops curl in the same direction. Place thehigh-current components such that during conduction, the current path is in the same direction. This preventsmagnetic field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.
•Select inductor ripple current DIL: for example ∆I
L
= 0.2 × I
OUT•Calculate inductor L:
where f
SW
is the regulator switching frequency.•Inductor peak current:
•Output voltage ripple:
Usually, the first term is dominant.
•Select inductor ripple current ∆I
L
: for example ∆I
L
= 0.2 × I
IN•Calculate inductor L:
where f
SW
is the regulator switching frequency.•Inductor peak current:
•Output voltage ripple:
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PACKAGE OPTION ADDENDUM
www.ti.com 19-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPIC74100QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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