3
UCC1839
UCC2839
UCC3839
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, 0°C to 70°C for the UCC3839, –40°C to 85° for the
UCC2839 and –55°C to 125°C for the UCC1839. VLINE = 10V, RG = 400Ω. TA=T
J.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Precision Reference
REF TJ= 25°C 4.95 5 5.05 V
IREF = 0mA to 1mA, VLINE = 10V to 20V 4.9 5.1 V
VA+/REF 0.298 0.3 0.302 V/V
VDD Regulator
VDD IDD = 0mA to –15mA, VLINE = 10V to 40V 7 7.5 8 V
IVDD VLINE = 10V to 40V, CA– = 0V, CA+ = 1V, VA– = 2.9V, CS+
= CS– = 0, IREF = 0 1.3 2 mA
Note 1: Guaranteed by design. Not 100% tested in production.
CA–: Current Error Amplifier Negative Input.
CAO: Current Error Amplifier Output. Output source cur-
rent is limited, and output sink current is guaranteed to
be greater than the VAO output source current. Current
loop compensation components are generally connected
to CAO and CA–.
CA+: Current Error Amplifier Positive Input.
CS–: Current Sense Amplifier Negative Input.
CSO: Current Sense Amplifier Output. Internally set gain
VOUT/VIN = 8 VIN = 0V results in CSO = 1V.
CS+: Current Sense Amplifier Positive Input.
GM: Gm (transconductance) Programming Pin. Resistor
RGM = 400Ωto GND.
GND: Chip Ground.
LED: Output of LED Driver. Connect LED from VDD pin
to LED.
REF: 5V Precision Reference Buffer Output. Minimum
Decoupling Capacitance = 0.01µF
VA–: Voltage Error Amplifier Negative Input. Voltage Er-
ror Amplifier is internally referenced to 1.5V
VAO: Voltage Error Amplifier Output. In a two loop aver-
age current mode control configuration, VAO is con-
nected to CA+ and is the current command signal. VAO
is internally clamped not to exceed 5V for short circuit
control. In a single loop voltage mode control configura-
tion with a parallel average short circuit current control
loop, VAO is connected directly to CAO. Output source
current is limited, and output sink current is guaranteed
to be greater than the CAO output source current.
VDD: 7.5V Regulator output. Supply for most of the
chip. Minimum Decoupling Capacitance = 0.01µF
VGATE: External FET Gate Control Voltage.
PIN DESCRIPTIONS
Fig. 1 shows a typical secondary side average current
mode controller configuration using the UCC3839. In this
configuration, output voltage is sensed and regulated by
the voltage error amplifier. Its output, VAO provides the
reference for the current error amplifier at the CA+ pin.
VAO can be connected to CA+ directly or through a re-
sistive divider depending on the particular application re-
quirements.
Average current mode control needs accurate output cur-
rent information which is provided by a low value current
sense resistor. The voltage proportional to the con-
verter’s output current is sensed and amplified by the
precision current sense amplifier of the chip. The
onboard current sense amplifier has a gain of 8 and is in-
tended for differential sensing of the shunt voltage with a
common mode voltage range from 0V up to 5V. The out-
put of the current sense amplifier, CSO is 1V for zero in-
put which guarantees that the circuit can control currents
down to 0A.
The CSO signal is fed to the CA– input of the current er-
ror amplifier through a resistor. The current error ampli-
fier takes the VAO and CSO signals and generates the
error signal for the pulse width modulator.
APPLICATION INFORMATION