34.807IRELESS
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless.
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rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
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under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34.807IRELESS
www.stnwireless.com
1. General description
The ISP1102A Universal Serial Bus (USB) transceiver is fully compliant with Ref. 1
“Universal Serial Bus Specification Rev. 2.0”. The ISP1102A can transmit and receive
USB data at full-speed (12 Mbit/s).
The transceiver allows USB Application-Specific Integrated Circuits (ASICs) and
Programmable Logic Devices (PLDs) with power supply voltages from 1.65 V to 3.6 V to
interface with the physical layer of the USB. The transceiver has an integrated 5 V-to-3.3 V
voltage regulator for direct powering through USB supply line VBUS. The transceiver has
an integrated voltage detector to detect the presence of the VBUS voltage (VCC(5V0)). When
VCC(5V0) or VREG3V3 is lost, the DP and DM pins can be shared with other serial
protocols.
The transceiver is a bidirectional differential interface and is available in HBCC16
package.
The transceiver is ideal for use in portable electronic devices, such as mobile phones,
digital still cameras, Personal Digital Assistants (PDAs) and Information Appliances (IAs).
2. Features
nComplies with Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
nSupports data transfer at full-speed (12 Mbit/s)
nIntegrated 5 V-to-3.3 V voltage regulator to power through USB line VBUS
nVBUS voltage presence indication on pin VBUSDET
nVP and VM pins function in bidirectional mode, allowing pin count saving for the ASIC
interface
nUsed as USB device transceiver or USB host transceiver
nStable RCV output during Single-Ended Zero (SE0) condition
nTwo single-ended receivers with hysteresis
nLow-power operation
nSupports I/O voltage range from 1.65 V to 3.6 V
n±12 kV ElectroStatic Discharge (ESD) protection at the DP, DM, VCC(5V0) and GND
pins
nFull industrial operating temperature range from 40 °C to +85 °C
nAvailable in HBCC16 lead-free and halogen-free package
ISP1102A
Advanced Universal Serial Bus transceiver
Rev. 01 — 15 February 2007 Product data sheet
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 2 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
3. Applications
nPortable electronic devices, such as:
uMobile phone
uDigital still camera
uPersonal Digital Assistant (PDA)
uInformation Appliance (IA)
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number Package
Name Description Version
ISP1102AW HBCC16 plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 × 3 × 0.65 mm SOT639-2
Fig 1. Block diagram
004aaa843
VCC(IO) VCC(5V0)
VOLTAGE
REGULATOR
3.3 V
1.5 k
33 (1 %)
33 (1 %)
LEVEL
SHIFTER
ISP1102A
SOFTCON
VREG3V3
GND
VPU3V3
DP
DM
OE_N
RCV
VP/VPO
VM/VMO
VBUSDET
SUSPEND
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 3 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration HBCC16 (top view)
ISP1102AW
Transparent top view
OE_N
SOFTCON
VPU3V3
VCC(5V0)
n.c.
VCC(IO)
VBUSDET
RCV
VP/VPO
VM/VMO
SUSPEND
VREG3V3
n.c.
n.c.
DP
DM
004aaa844
1
2
3
4
5
13
12
11
10
9
16
15
14
6
7
8
Table 2. Pin description
Symbol[1] Pin Type[2] Description
OE_N 1 I input for output enable (CMOS level with respect to VCC(IO), active LOW); enables
the transceiver to transmit data on the USB bus
input pad; push pull; CMOS
RCV 2 O differential data receiver output (CMOS level with respect to VCC(IO)); driven LOW
when input SUSPEND is HIGH; the output state of RCV is preserved and stable
during an SE0 condition
output pad; push pull; 4 mA output drive; CMOS
VP/VPO 3 I/O single-ended DP receiver output VP (CMOS level with respect to VCC(IO)); for
external detection of SE0, error conditions, speed of connected device; this pin
also acts as drive data input VPO; see Table 3 and Table 4
bidirectional pad; push-pull input; 3-state output; 4 mA output drive; CMOS
VM/VMO 4 I/O single-ended DM receiver output VM (CMOS level with respect to VCC(IO)); for
external detection of SE0, error conditions, speed of connected device; this pin
also acts as drive data input VMO; see Table 3 and Table 4
bidirectional pad; push-pull input; 3-state output; 4 mA output drive; CMOS
SUSPEND 5 I suspend input (CMOS level with respect to VCC(IO)); a HIGH level enables
low-power state while the USB bus is inactive and drives output RCV to a LOW
level
input pad; push pull; CMOS
n.c. 6 - not connected
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 4 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
[1] Symbol names with an underscore N (for example, OE_N) indicate active LOW signals.
[2] I = input; O = output; I/O = digital input/output; AI/O = analog input/output.
VCC(IO) 7 - supply voltage for digital I/O pins (1.65 V to 3.6 V); when VCC(IO) is not connected,
the DP and DM pins are in 3-state; this supply pin is totally independent of
VCC(5V0) and VREG3V3 and must never exceed the VREG3V3 voltage
VBUSDET 8 O VBUS indicator output (CMOS level with respect to VCC(IO))
When VBUS > 4.1 V, then VBUSDET = HIGH
When VBUS < 3.6 V, then VBUSDET = LOW
When SUSPEND = HIGH, then the VBUSDET function is invalid
Connect a 1 µF-to-10 µF decoupling capacitor (4.7 µF capacitor is used on the
ISP1102 evaluation board)
output pad; push pull; 4 mA output drive; CMOS
DM 9 AI/O negative USB data bus connection (analog, differential)
DP 10 AI/O positive USB data bus connection (analog, differential)
n.c. 11 - not connected
n.c. 12 - not connected
VREG3V3 13 - internal regulator option: regulated supply voltage output (3.0 V to 3.6 V) during
5 V operation; a decoupling capacitor of at least 0.1 µF is required
regulator bypass option: used as a supply voltage input (3.3 V ±10 %) for 3.3 V
operation
VCC(5V0) 14 - internal regulator option: supply voltage input (4.0 V to 5.5 V); can directly be
connected to USB line VBUS
regulator bypass option: connect to VREG3V3
VPU3V3 15 - pull-up supply voltage (3.3 V ± 10 %); connect an external 1.5 k resistor on DP
(full-speed)
This pin function is controlled by the SOFTCON input:
SOFTCON = LOW — VPU3V3 floating (high-Z); ensures zero pull-up current
SOFTCON = HIGH — VPU3V3 = 3.3 V; internally connected to VREG3V3
SOFTCON 16 I software controlled USB connection input; a HIGH level applies 3.3 V to
pin VPU3V3, which is connected to an external 1.5 kpull-up resistor; this allows
USB connect or disconnect signaling to be controlled by software
input pad; push pull; CMOS
GND exposed
die pad - ground supply; down bonded to the exposed die pad (heat sink); to be connected
to the PCB ground
Table 2. Pin description
…continued
Symbol[1] Pin Type[2] Description
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 5 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
7. Functional description
7.1 Function selection
[1] Signal levels on the DP and DM pins are determined by other USB devices and external pull-up or pull-down resistors.
[2] In suspend mode (SUSPEND = HIGH), the differential receiver is inactive and output RCV is always LOW. The resume signaling is
detected through single-ended receivers VP/VPO and VM/VMO.
7.2 Operating functions
[1] RCV* denotes the signal level on output RCV just before the SE0 state occurs. This level is stable during
the SE0 period.
7.3 Power supply configurations
The ISP1102A can be used with various power supply configurations, which can be
changed dynamically. Table 7 provides an overview of the power supply configurations.
Normal mode — VCC(IO) is connected. VCC(5V0) is connected only, or VCC(5V0) and
VREG3V3 are connected.
For the 5 V operation, VCC(5V0) is connected to a 5 V source (4.0 V to 5.5 V). The internal
voltage regulator then produces 3.3 V for USB connections.
For the 3.3 V operation, both VCC(5V0) and VREG3V3 are connected to a 3.3 V source
(3.0 V to 3.6 V).
VCC(IO) is independently connected to a voltage source (1.65 V to 3.6 V), depending on
the supply voltage of the external circuit.
Table 3. Function selection
SUSPEND OE_N DP, DM RCV VP/VPO VM/VMO Function
LOW LOW driving or
receiving active VPO input VMO input normal driving (differential
receiver active)
LOW HIGH receiving[1] active VP output VM output receiving
HIGH LOW driving inactive[2] VPO input VMO input driving during suspend
(differential receiver inactive)
HIGH HIGH high-Z[1] inactive[2] VP output VM output low-power state
Table 4. Driving function using differential input data interface (pin OE_N = LOW)
VM/VMO VP/VPO Data
LOW LOW SE0
LOW HIGH differential logic 1
HIGH LOW differential logic 0
HIGH HIGH illegal state
Table 5. Receiving function (pin OE_N = HIGH)
DP, DM RCV VP/VPO VM/VMO
Differential logic 0 LOW LOW HIGH
Differential logic 1 HIGH HIGH LOW
SE0 RCV*[1] LOW LOW
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 6 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
Sharing mode — VCC(IO) is connected only, VCC(5V0) is < 3.6 V, and VREG3V3 is < 2.4 V.
In this mode, the DP and DM pins are 3-stated and the ISP1102A allows external signals
of up to 3.6 V to share the DP and DM lines. The internal circuits of the ISP1102A ensure
that virtually no current (maximum 10 µA) is drawn through the DP and DM lines. The
power consumption through pin VCC(IO) drops to the low-power (suspended) state level.
Pins VBUSDET and RCV are driven to LOW to indicate this mode. The VBUSDET
function is ignored during suspend mode of the ISP1102A.
Some hysteresis is built into the detection of VREG3V3 lost.
Remark: Sharing mode is not possible in the regulator bypass option.
[1] VP/VPO and VM/VMO are bidirectional pins.
Table 6. Pin states in sharing modes
Pin Sharing mode
VCC(5V0) < 3.6 V
VREG3V3 < 2.4 V
VCC(IO) 1.65 V to 3.6 V input
VPU3V3 high-Z (off)
DP, DM high-Z
VP/VPO, VM/VMO[1] LOW
RCV LOW
VBUSDET LOW
OE_N, SUSPEND, SOFTCON high-Z
Table 7. Power supply configuration overview
VCC(5V0) VCC(IO) Configuration Special characteristics
Connected connected normal mode -
< 3.6 V connected sharing mode DP, DM and VPU3V3: high-Z
VP/VPO and VM/VMO: driven LOW
RCV: driven LOW
VBUSDET: driven LOW
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 7 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
7.4 Power supply input options
The ISP1102A has two power supply input options.
Internal regulator — Pin VCC(5V0) is connected to 4.0 V to 5.5 V. The internal regulator is
used to supply the internal circuitry with 3.3 V (nominal). The VREG3V3 pin becomes a
3.3 V output reference.
Regulator bypass — Pins VCC(5V0) and VREG3V3 are connected to the same supply.
The internal regulator is bypassed and the internal circuitry is supplied directly from
pin VREG3V3. The voltage range is 3.0 V to 3.6 V to comply with Ref. 1 “Universal Serial
Bus Specification Rev. 2.0”.
The supply voltage range for each input option is specified in Table 8.
Table 8. Power supply input options
Input option VCC(5V0) VREG3V3 VCC(IO)
Internal regulator supply input for internal regulator
(4.0 V to 5.5 V) voltage reference output
(3.3 V, 300 µA) supply input for digital I/O pins
(1.65 V to 3.6 V)
Regulator bypass connected to VREG3V3 with
maximum voltage drop of 0.3 V
(2.7 V to 3.6 V)
supply input (3.0 V to 3.6 V) supply input for digital I/O pins
(1.65 V to 3.6 V)
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 8 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
8. ElectroStatic Discharge (ESD)
8.1 ESD protection
For the HBCC package, the pins that are connected to the USB connector (DP, DM,
VCC(5V0) and GND) have a minimum of ±12 kV ESD protection. The ±12 kV measurement
is limited by the test equipment. Capacitors of 4.7 µF connected from VREG3V3 to GND
and VCC(5V0) to GND are required to achieve this ±12 kV ESD protection (see Figure 3).
8.2 ESD test conditions
A detailed report on test set up and results is available on request.
Fig 3. Human body ESD test model
RD
1500
RC
1 M
HIGH VOLTAGE
DC SOURCE
4.7 µF 4.7 µF
VCC(5V0)
VREG3V3
DEVICE UNDER
TEST
CS
100 pF storage
capacitor
charge current
limit resistor discharge
resistance
GND
A
B
004aaa145
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 9 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
9. Limiting values
[1] Testing equipment limits measurement to only ±12 kV. Capacitors needed on VCC(5V0) and VREG3V3 (see Section 8).
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model).
10. Recommended operating conditions
11. Static characteristics
Table 9. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC(5V0) supply voltage (5.0 V) 0.5 +6.0 V
VCC(IO) IO supply voltage 0.5 +4.6 V
VIinput voltage 0.5 VCC(IO) + 0.5 V V
Ilu latch-up current VI=1.8 V to +5.4 V - 100 mA
Vesd electrostatic discharge voltage pins DP, DM, VCC(5V0) and GND;
ILI < 3 µA[1][2] 12000 +12000 V
all other pins; ILI < 1 µA[2] 2000 +2000 V
Tstg storage temperature 40 +125 °C
Table 10. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC(5V0) supply voltage (5.0 V) 4.0 5.0 5.5 V
VCC(IO) IO supply voltage 1.65 - 3.6 V
VIinput voltage 0 - VCC(IO) V
VIA(I/O) input voltage on analog I/O pins on pins DP and DM 0 - 3.6 V
Tjjunction temperature 40 - +125 °C
Tamb ambient temperature 40 - +85 °C
Table 11. Static characteristics: supply pins
V
CC(5V0)
= 4.0 V to 5.5 V or V
(VREG3V3)
= 3.0 V to 3.6 V; V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; see Table 8 for valid voltage
level combinations; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(VREG3V3) voltage on pin VREG3V3 internal regulator option; Iload
300 µA[1][2] 3.0 3.3 3.6 V
ICC supply current transmitting and receiving at
12 Mbit/s; CL= 50 pF on pins DP
and DM
[3] -48mA
ICC(IO) supply current on pin VCC(IO) transmitting and receiving at
12 Mbit/s [3] -12mA
ICC(idle) idle and SE0 supply current idle: VDP > 2.7 V, VDM < 0.3 V;
SE0: VDP < 0.3 V, VDM < 0.3 V [4] - - 300 µA
ICC(IO)static static supply current on
pin VCC(IO)
idle, SE0 or suspend - - 20 µA
ICC(susp) suspend supply current SUSPEND = HIGH [4] --20µA
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 10 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
[1] Iload includes the pull-up resistor current through pin VPU3V3.
[2] The minimum voltage is 2.7 V in suspend mode.
[3] Maximum value characterized only, not tested in production.
[4] Excluding any load current and VPU3V3 or VSW source current to the 1.5 k and 15 k pull-up and pull-down resistors (200 µA typ.).
[5] When VCC(IO) < 2.7 V, the minimum value for VREG(3V3)th = 2.0 V for supply present condition.
ICC(IO)sharing sharing mode supply current
on pin VCC(IO)
VCC(5V0) < 3.6 V - - 20 µA
Iload(sharing)DM sharing mode load current
on pin DM VCC(5V0) < 3.6 V; SOFTCON =
LOW; VDM = 3.6 V --10µA
Iload(sharing)DP sharing mode load current
on pin DP VCC(5V0) < 3.6 V; SOFTCON =
LOW; VDP = 3.6 V --10µA
VCC(5V0)th supply voltage detection
threshold (5.0 V) 1.65 V VCC(IO) 3.6 V
supply lost - - 3.6 V
supply present 4.1 - - V
VCC(5V0)hys supply voltage detection
hysteresis (5.0 V) VCC(IO) = 1.8 V - 70 - mV
VCC(IO)th supply voltage detection
threshold on pin VCC(IO)
V(VREG3V3) = 2.7 V to 3.6 V
supply lost - - 0.5 V
supply present 1.4 - - V
VCC(IO)hys supply voltage detection
hysteresis on pin VCC(IO)
V(VREG3V3) = 3.3 V - 0.45 - V
VREG(3V3)th regulated supply voltage
detection threshold (3.3 V) 1.65 V VCC(IO) V(VREG3V3);
2.7 V V(VREG3V3) 3.6 V
supply lost - - 0.8 V
supply present [5] 2.4 - - V
VREG(3V3)hys regulated supply voltage
detection hysteresis (3.3 V) VCC(IO) = 1.8 V - 0.45 - V
Table 11. Static characteristics: supply pins
…continued
V
CC(5V0)
= 4.0 V to 5.5 V or V
(VREG3V3)
= 3.0 V to 3.6 V; V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; see Table 8 for valid voltage
level combinations; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 12. Static characteristics: digital pins
V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCC(IO) = 1.65 V to 3.6 V
Input levels
VIL LOW-level input voltage - - 0.3VCC(IO) V
VIH HIGH-level input voltage 0.6VCC(IO) -- V
Output levels
VOL LOW-level output voltage IOL = 100 µA - - 0.15 V
IOL = 2 mA - - 0.4 V
VOH HIGH-level output voltage IOH = 100 µAV
CC(IO) 0.15 V - - V
IOH = 2 mA VCC(IO) 0.4 V - - V
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 11 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
[1] If VCC(IO) V(VREG3V3), then the leakage current will be higher than the specified value.
Capacitance
Cin input capacitance pin to GND - - 10 pF
Example 1: VCC(IO) = 1.8 V ± 0.15 V
Input levels
VIL LOW-level input voltage - - 0.5 V
VIH HIGH-level input voltage 1.2 - - V
Output levels
VOL LOW-level output voltage IOL = 100 µA - - 0.15 V
IOL = 2 mA - - 0.4 V
VOH HIGH-level output voltage IOH = 100 µA 1.5 - - V
IOH = 2 mA 1.25 - - V
Leakage current
ILI input leakage current [1] 1-+1µA
Example 2: VCC(IO) = 2.5 V ± 0.2 V
Input levels
VIL LOW-level input voltage - - 0.7 V
VIH HIGH-level input voltage 1.7 - - V
Output levels
VOL LOW-level output voltage IOL = 100 µA - - 0.15 V
IOL = 2 mA - - 0.4 V
VOH HIGH-level output voltage IOH = 100 µA 2.15 - - V
IOH = 2 mA 1.9 - - V
Leakage current
ILI input leakage current [1] 5-+5µA
Example 3: VCC(IO) = 3.3 V ± 0.3 V
Input levels
VIL LOW-level input voltage - - 0.9 V
VIH HIGH-level input voltage 2.15 - - V
Output levels
VOL LOW-level output voltage IOL = 100 µA - - 0.15 V
IOL = 2 mA - - 0.4 V
VOH HIGH-level output voltage IOH = 100 µA 2.85 - - V
IOH = 2 mA 2.6 - - V
Leakage current
ILI input leakage current [1] 5-+5µA
Table 12. Static characteristics: digital pins
…continued
V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 12 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
[1] VOH(min) = V(VREG3V3) 0.2 V.
[2] Includes external resistors of 33 Ω± 1 % on both pins DP and DM.
[3] This voltage is available at pins VREG3V3 and VPU3V3.
[4] The minimum voltage is 2.7 V in suspend mode.
12. Dynamic characteristics
Table 13. Static characteristics: analog I/O pins DP and DM
V
CC(5V0)
= 4.0 V to 5.5 V or V
(VREG3V3)
= 3.0 V to 3.6 V; V
GND
= 0 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Input levels
Differential receiver
VDI differential input sensitivity |VDP VDM|0.2 - - V
VCM differential common mode
voltage includes VDI range 0.8 - 2.5 V
Single-ended receiver
VIL LOW-level input voltage - - 0.8 V
VIH HIGH-level input voltage 2.0 - - V
Vhys hysteresis voltage 0.4 - 0.7 V
Output levels
VOL LOW-level output voltage RL= 1.5 k to 3.6 V - - 0.3 V
VOH HIGH-level output voltage RL= 15 k to GND [1] 2.8 - 3.6 V
Leakage current
ILZ off-state leakage current 1- +1µA
Capacitance
Cin input capacitance pin to GND - - 20 pF
Resistance
ZDRV driver output impedance steady-state drive [2] 34 39 44
ZINP input impedance 10 - - M
Rsw(VPU3V3) switch-on resistance on pin
VPU3V3 --10
Termination
VTERM termination voltage for upstream port pull-up
(RPU)[3][4] 3.0 - 3.6 V
Table 14. Dynamic characteristics: analog I/O pins DP and DM
V
CC(5V0)
= 4.0 V to 5.5 V or V
(VREG3V3)
= 3.0 V to 3.6 V; V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; see Table 8 for valid voltage
level combinations; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Driver characteristics
tFR rise time CL= 50 pF to 125 pF; 10 % to
90 % of |VOH VOL|; see Figure 4 4 - 20 ns
tFF fall time CL= 50 pF to 125 pF; 90 % to
10 % of |VOH VOL|; see Figure 4 4 - 20 ns
FRFM differential rise time/fall
time matching excluding the first transition from
Idle state 90 - 111.1 %
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 13 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
[1] Characterized only, not tested. Limits guaranteed by design.
VCRS outputsignalcrossover
voltage excluding the first transition from
idle state; see Figure 5 [1] 1.3 - 2.0 V
Driver timing
tPLH(drv) driver propagation
delay (LOW to HIGH) VPO, VMO to DP, DM; see
Figure 5 and Figure 8 --18ns
tPHL(drv) driver propagation
delay (HIGH to LOW) VPO, VMO to DP, DM; see
Figure 5 and Figure 8 --18ns
tPHZ driver disable delay
from HIGH level OE_N to DP, DM; see Figure 6
and Figure 9 --15ns
tPLZ driver disable delay
from LOW level OE_N to DP, DM; see Figure 6
and Figure 9 --15ns
tPZH driver enable delay to
HIGH level OE_N to DP, DM; see Figure 6
and Figure 9 --15ns
tPZL driver enable delay to
LOW level OE_N to DP, DM; see Figure 6
and Figure 9 --15ns
Receiver timings
Differential receiver
tPLH(rcv) receiver propagation
delay (LOW to HIGH) DP, DM to RCV; see Figure 7 and
Figure 10 --15ns
tPHL(rcv) receiver propagation
delay (HIGH to LOW) DP, DM to RCV; see Figure 7 and
Figure 10 --15ns
Single-ended receiver
tPLH(se) single-ended
propagation delay
(LOW to HIGH)
DP, DM to VP/VPO, VM/VMO;
see Figure 7 and Figure 10 --18ns
tPHL(se) single-ended
propagation delay
(HIGH to LOW)
DP, DM to VP/VPO, VM/VMO;
see Figure 7 and Figure 10 --18ns
Table 14. Dynamic characteristics: analog I/O pins DP and DM
…continued
V
CC(5V0)
= 4.0 V to 5.5 V or V
(VREG3V3)
= 3.0 V to 3.6 V; V
CC(IO)
= 1.65 V to 3.6 V; V
GND
= 0 V; see Table 8 for valid voltage
level combinations; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 14 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
Fig 4. Rise time and fall time Fig 5. Timing of VPO and VMO to DP and DM
Fig 6. Timing of OE_N to DP and DM Fig 7. Timing of DP and DM to RCV, VP/VPO and
VM/VMO
004aaa572
VOL
tFR, tLR tFF, tLF
VOH 90 %
10 % 10 %
90 %
004aaa573
VOL
VOH
tPHL(drv)
tPLH(drv)
VCRS VCRS
0.9 V
0.9 V
1.8 V
0 V
logic input
differential
data lines
004aaa574
VOL
VOH
tPZH
tPZL tPHZ
tPLZ
VOH 0.3 V
VOL + 0.3 V
VCRS
0.9 V
0.9 V
1.8 V
0 V
logic
input
differential
data lines
tPLH(se) tPHL(se)
004aaa575
VOL
VOH
tPHL(rcv)
tPLH(rcv)
VCRS VCRS
0.9 V
0.9 V
2.0 V
0.8 V
logic output
differential
data lines
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 15 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
13. Test information
Load capacitance CL= 50 pF (minimum or maximum timing)
Fig 8. Load on pins DP and DM
V = 0 V for tPZH and tPHZ
V= V
(VREG3V3) for tPZL and tPLZ
Fig 9. Load on pins DP and DM for enable time and disable time
Fig 10. Load on pins VM/VMO, VP/VPO and RCV
004aaa037
CL
test point
15 k
DP/DM
VPU3V3
1.5 k
33
DUT
V
33
D.U.T. 500
50 pF
004aaa517
DP or
DM
test point
004aaa709
25 pF
test point
D.U.T.
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 16 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
14. Package outline
Fig 11. Package outline SOT639-2 (HBCC16)
2.5
A1bA2
UNIT DEhe1
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
01-11-13
03-03-12
IEC JEDEC JEITA
mm 0.8 0.10
0.05 0.7
0.6 3.1
2.9 1.45
1.35
3.1
2.9
1.45
1.35
0.33
0.27
DIMENSIONS (mm are the original dimensions)
SOT639-2 MO-217
Dh
0.33
0.27
b1
0.38
0.32
b3
0.38
0.32
b2
2.45
e3
E
0.23
0.17
f
0.5
we yy
1
0.1 0.05 0.2
2.5
e2
2.45
e4
0.08
v
0 2.5 5 mm
scale
SOT639-2
HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm
A
max.
detail X
y
y1C
e
e
e1
e3
Dh
e4
D
E
X
C
BA
16
113
59
e2
1/2 e3
1/2 e4
Eh
A1
A2
A
b2
b1
b3
b
f
terminal 1
index area
AC
CB
vM
wM
AC
CB
vM
wM
AC
CB
vM
wM
AC
CB
vM
wM
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 17 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
15. Packing information
The ISP1102AW (HBCC16 package) is delivered on a Type A carrier tape, see Figure 12.
The tape dimensions are given in Table 15.
The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not designed for
use in a baking process.
The cumulative tolerance of 10 successive sprocket holes is ±0.02 mm. The camber must
not exceed 1 mm in 100 mm.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
Fig 12. Carrier tape dimensions
Table 15. Type A carrier tape dimensions for the ISP1102AW
Dimension Value Unit
A0 3.3 mm
B0 3.3 mm
K0 1.1 mm
P1 8.0 mm
W 12.0 ± 0.3 mm
004aaa728
type B
type A
B0
4
W
K0
A0
4K0
A0
P1
B0
P1
elongated
sprocket hole
direction of feed
W
direction of feed
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 18 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus
reducing the process window
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 19 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
Table 16. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 17. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 20 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
For further information on temperature profiles, refer to Application Note
AN10365
“Surface mount reflow soldering description”
.
17. Abbreviations
18. References
[1] Universal Serial Bus Specification Rev. 2.0
[2] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
(JESD22-A114D)
19. Revision history
Table 18. Abbreviations
Acronym Description
ASIC Application-Specific Integrated Circuit
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
SE0 Single-Ended Zero
USB Universal Serial Bus
Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ISP1102A_1 20070215 Product data sheet - -
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 21 of 24
NXP Semiconductors ISP1102A
Advanced USB transceiver
20. Legal information
20.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
21. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 22 of 24
continued >>
NXP Semiconductors ISP1102A
Advanced USB transceiver
22. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 3. Function selection . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Driving function using differential input data
interface (pin OE_N = LOW) . . . . . . . . . . . . . . .5
Table 5. Receiving function (pin OE_N = HIGH) . . . . . . .5
Table 6. Pin states in sharing modes . . . . . . . . . . . . . . .6
Table 7. Power supply configuration overview . . . . . . . . .6
Table 8. Power supply input options . . . . . . . . . . . . . . . .7
Table 9. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 10. Recommended operating conditions . . . . . . . . .9
Table 11. Static characteristics: supply pins . . . . . . . . . . .9
Table 12. Static characteristics: digital pins . . . . . . . . . . .10
Table 13. Static characteristics: analog I/O pins
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 14. Dynamic characteristics: analog I/O pins
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 15. Type A carrier tape dimensions for the
ISP1102AW . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 16. SnPb eutectic process (from J-STD-020C) . . .19
Table 17. Lead-free process (from J-STD-020C) . . . . . .19
Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . .20
ISP1102A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 15 February 2007 23 of 24
continued >>
NXP Semiconductors ISP1102A
Advanced USB transceiver
23. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Fig 2. Pin configuration HBCC16 (top view) . . . . . . . . . .3
Fig 3. Human body ESD test model. . . . . . . . . . . . . . . . .8
Fig 4. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .14
Fig 5. Timing of VPO and VMO to DP and DM . . . . . . .14
Fig 6. Timing of OE_N to DP and DM . . . . . . . . . . . . . .14
Fig 7. Timing of DP and DM to RCV, VP/VPO and
VM/VMO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 8. Load on pins DP and DM. . . . . . . . . . . . . . . . . . .15
Fig 9. Load on pins DP and DM for enable time and
disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 10. Load on pins VM/VMO, VP/VPO and RCV . . . . .15
Fig 11. Package outline SOT639-2 (HBCC16). . . . . . . . .16
Fig 12. Carrier tape dimensions. . . . . . . . . . . . . . . . . . . .17
Fig 13. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
NXP Semiconductors ISP1102A
Advanced USB transceiver
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 February 2007
Document identifier: ISP1102A_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
24. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5
7.2 Operating functions. . . . . . . . . . . . . . . . . . . . . . 5
7.3 Power supply configurations. . . . . . . . . . . . . . . 5
7.4 Power supply input options. . . . . . . . . . . . . . . . 7
8 ElectroStatic Discharge (ESD) . . . . . . . . . . . . . 8
8.1 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 8
8.2 ESD test conditions . . . . . . . . . . . . . . . . . . . . . 8
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
10 Recommended operating conditions. . . . . . . . 9
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 12
13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 15
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Packing information. . . . . . . . . . . . . . . . . . . . . 17
16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 18
16.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 18
17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
21 Contact information. . . . . . . . . . . . . . . . . . . . . 21
22 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
23 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24