2003 Microchip Technology Inc. DS21795A-page 1
93AA66A/B/C, 93LC66A/B/C,
93C66A/B/C
Device Selection Table
Features
Low power CMOS technology
ORG pin to select word size for ‘66C version
512 x 8-bit organization ‘A’ ver. devices (no ORG)
256 x 16-bit organization ‘B’ ver. devices (no
ORG)
Self-timed ERASE/WRITE cycles (including
auto-erase)
Automatic ERAL before WRAL
Power on/off data protection circuitry
Industry standard 3-wire serial I/O
Device status signal (READY/BUSY)
Sequential READ function
1,000,000 E/W cycles
Data retention > 200 years
Temperature ranges supported:
Pin Function Table
Description
The Microchip Technology Inc. 93XX66A/B/C devices
are 4K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA66C, 93LC66C or 93C66C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA66A, 93LC66A or 93C66A devices are available,
while the 93AA66B, 93LC66B and 93C66B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, non-volatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
Package Types (not to scale)
Part Number VCC Range ORG Pin Word Size Temp Ranges Packages
93AA66A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT
93AA66B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT
93LC66A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93LC66B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93C66A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93C66B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93AA66C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS
93LC66C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS
93C66C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No internal connection
ORG Memory Configuration
VCC Power Supply
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
PDIP/SOIC
(P, SN)
CS
CLK DI
DO
1
2
3
4
8
7
6
5
V
CC
NC ORG*
V
SS
ROTATED SOIC
(ex: 93LC66BX)
TSSOP/MSOP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
(ST, MS)
SOT-23
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
(OT)
* ORG pin is NC on A/B devices
4K Microwire®-Compatible Serial EEPROM
Microwire is a registered trademark of National Semiconductor.
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
DC CHARACTERISTICS
NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
All parameters apply over the specified
ranges unless otherwise noted.
VCC = range by device (see Table on Page 1)
Industrial (I): TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Param.
No. Symbol Parameter Min Typ Max Units Conditions
D1 VIH1
VIH2
High level input voltage 2.0
0.7 VCC
VCC +1
VCC +1
V
V
VCC 2.7V
VCC < 2.7V
D2 VIL1
VIL2
Low level input voltage -0.3
-0.3
0.8
0.2 VCC
V
V
VCC 2.7V
VCC < 2.7V
D3 Vol1
Vol2
Low level output voltage
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 µA, VCC = 2.5V
D4 VOH1
VOH2
High level output voltage 2.4
VCC - 0.2
V
V
IOH = -400 µA, VCC = 4.5V
IOH = -100 µA, VCC = 2.5V
D5 ILI Input leakage current ±10 µAVIN = VSS to VCC
D6 ILO Output leakage current ±10 µAVOUT = VSS to VCC
D7 CIN,
COUT
Pin capacitance (all inputs/
outputs)
——7 pFVIN/VOUT = 0V (Note 1)
TAMB = 25°C, FCLK = 1 MHz
D8 ICC write Write current
500
2
mA
µA
FCLK = 3 MHz, Vcc = 5.5V
FCLK = 2 MHz, Vcc = 2.5V
D9 ICC read Read current
100
1
500
mA
µA
µA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10 ICCS Standby current
1
5
µA
µA
I – Temp
E – Temp
CLK = Cs = 0V
ORG = DI = VSS or VCC
(Note 2) (Note 3)
D11 VPOR VCC voltage detect
93AA66A/B/C, 93LC66A/B/C
93C66A/B/C
1.5V
3.8V
V
V
(Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: READY/BUSY status must be cleared from DO, see Section 3.4.
2003 Microchip Technology Inc. DS21795A-page 3
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
VCC = range by device (see Table on Page 1)
Industrial (I): TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Param.
No. Symbol Parameter Min Max Units Conditions
A1 FCLK Clock frequency 3
2
1
MHz
MHz
MHz
4.5V VCC < 5.5V, 93XX66C only
2.5V VCC < 5.5V
1.8V VCC < 2.5V
A2 TCKH Clock high time 200
250
450
—ns
ns
ns
4.5V VCC < 5.5V, 93XX66C only
2.5V VCC < 5.5V
1.8V VCC < 2.5V
A3 TCKL Clock low time 100
200
450
—ns
ns
ns
4.5V VCC < 5.5V, 93XX66C only
2.5V VCC < 5.5V
1.8V VCC < 2.5V
A4 TCSS Chip select setup time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V
2.5V VCC < 4.5V
1.8V VCC < 2.5V
A5 TCSH Chip select hold time 0 ns 1.8V VCC < 5.5V
A6 TCSL Chip select low time 250 ns 1.8V VCC < 5.5V
A7 TDIS Data input setup time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V, 93XX66C only
2.5V VCC < 5.5V
1.8V VCC < 2.5V
A8 TDIH Data input hold time 50
100
250
—ns
ns
ns
4.5V VCC < 5.5V, 93XX66C only
2.5V VCC < 5.5V
1.8V VCC < 2.5V
A9 TPD Data output delay time 200
250
400
ns
ns
ns
4.5V VCC < 5.5V, CL = 100 pF
2.5V VCC < 4.5V, CL = 100 pF
1.8V VCC < 2.5V, CL = 100 pF
A10 TCZ Data output disable time 100
200
ns
ns
4.5V VCC < 5.5V, (Note 1)
1.8V VCC < 4.5V, (Note 1)
A11 TSV Status valid time 200
300
500
ns
ns
ns
4.5V VCC < 5.5V, CL = 100 pF
2.5V VCC < 4.5V, CL = 100 pF
1.8V VCC < 2.5V, CL = 100 pF
A12 TWC Program cycle time 6 ms ERASE/WRITE mode (AA and LC
versions)
A13 TWC 2 ms ERASE/WRITE mode
(93C versions)
A14 TEC 6 ms ERAL mode, 4.5V VCC 5.5V
A15 TWL 15 ms WRAL mode, 4.5V VCC 5.5V
A16 Endurance 1M cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which may be obtained on www.microchip.com.
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 4 2003 Microchip Technology Inc.
FIGURE 1-1: SYNCHRONOUS DATA TIMING
TABLE 1-1: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX66B OR 93XX66C WITH ORG = 1)
TABLE 1-2: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX66A OR 93XX66C WITH ORG = 0)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY)11
ERAL 1 00 10XXXXXX (RDY/BSY
)11
EWDS 1 00 0 0XXXXXX HIGH-Z 11
EWEN 1 00 1 1 X X X X X X HIGH-Z 11
READ 1 10 A7A6A5A4A3A2A1A0 D15 D0 27
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY)27
WRAL 1 00 0 1 X X X X X X D15 – D0 (RDY/BSY)27
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY)12
ERAL 1 00 10XXXXXXX (RDY/BSY
)12
EWDS 1 00 00XXXXXXX HIGH-Z 12
EWEN 1 00 11XXXXXXX HIGH-Z 12
READ 1 10 A8A7A6A5A4A3A2A1A0 D7 D0 20
WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY)20
WRAL 1 00 01XXXXXXX D7 D0 (RDY/BSY
)20
CS VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
TCSS
TDIS
TCKH TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note: TSV is relative to CS.
2003 Microchip Technology Inc. DS21795A-page 5
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is HIGH, the device
is no longer in Standby mode.
An instruction following a START condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undefined and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the Data Out pin. In order
to limit this current, a resistor should be connected
between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note: For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
VCC VSS
*ORG input is not available on A/B devices
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 6 2003 Microchip Technology Inc.
2.4 ERASE
The ERASE instruction forces all data bits of the speci-
fied address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
Note: Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2: ERASE TIMING FOR 93C DEVICES
CS
CLK
DI
DO
TCSL
CHECK STATUS
111A
NAN-1 AN-2 ••• A0
TSV TCZ
BUSY READY
HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STATUS
111A
NAN-1 AN-2 ••• A0
TSV TCZ
BUSY READY
HIGH-Z
TWC
HIGH-Z
2003 Microchip Technology Inc. DS21795A-page 7
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5 ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note: Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be 4.5V for proper operation of ERAL.
FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4: ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
TCSL
CHECK STATUS
100 10X
••• X
TSV TCZ
BUSY READY
HIGH-Z
TEC
HIGH-Z
VCC must be 4.5V for proper operation of ERAL.
CS
CLK
DI
DO
TCSL
CHECK STATUS
100 10X
••• X
TSV TCZ
BUSY READY
HIGH-Z
TEC
HIGH-Z
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 8 2003 Microchip Technology Inc.
2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX66A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All Programming modes must be
preceded by an ERASE/WRITE Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed, program-
ming remains enabled until an EWDS instruction is
executed or Vcc is removed from the device. To protect
against accidental data disturbance, the EWDS instruc-
tion can be used to disable all ERASE/WRITE
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent of
both the EWEN and EWDS instructions.
FIGURE 2-5: EWDS TIMING
FIGURE 2-6: EWEN TIMING
2.7 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string. The output data bits will toggle on
the rising edge of the CLK and are stable after the spec-
ified time delay (TPD). Sequential read is possible when
CS is held high. The memory data will automatically cycle
to the next register and output sequentially.
FIGURE 2-7: READ TIMING
CS
CLK
DI 10
000X ••• X
TCSL
1X
CS
CLK
DI 00 1 1X
TCSL
•••
CS
CLK
DI
DO
110
An ••• A0
HIGH-Z 0Dx
••• D0 Dx ••• D0 •••
Dx D0
2003 Microchip Technology Inc. DS21795A-page 9
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.8 WRITE
The WRITE instruction is followed by 8 bits (If ORG is
low or A-version devices) or 16 bits (If ORG pin is high
or B-version devices) of data which are written into the
specified address. For 93AA66A/B/C and 93LC66A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C66A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been written
with the data specified and the device is ready for
another instruction.
Note: Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-9: WRITE TIMING FOR 93C DEVICES
CS
CLK
DI
DO
101An ••• A0 Dx ••• D0
BUSY READY HIGH-Z
HIGH-Z
Twc
TCSL
TCZ
TSV
CS
CLK
DI
DO
101An ••• A0 Dx ••• D0
BUSY READY HIGH-Z
HIGH-Z
Twc
TCSL
TCZ
TSV
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 10 2003 Microchip Technology Inc.
2.9 WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA66A/B/C and 93LC66A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note: Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-11: WRAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
HIGH-Z
10001 X
••• XDx ••• D0
HIGH-Z BUSY READY
TWL
VCC must be 4.5V for proper operation of WRAL.
TCSL
TSV TCZ
CS
CLK
DI
DO
HIGH-Z
10001 X
••• XDx ••• D0
HIGH-Z BUSY READY
TWL
TCSL
TSV TCZ
2003 Microchip Technology Inc. DS21795A-page 11
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN DESCRIPTIONS
3.1 Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a RESET status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified
number of clock cycles (respectively low to high transi-
tions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new START
condition to be detected.
3.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address and data synchronously with the CLK input.
3.4 Data Out (DO)
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
Note: Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
3.5 Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX66A devices are always x8 organization and
93XX66B devices are always x16 organization.
Name SOIC/PDIP/
MSOP/TSSOP SOT-23 Rotated SOIC Function
CS 1 5 3 Chip Select
CLK 2 4 4 Serial Clock
DI 3 3 5 Data In
DO 4 1 6 Data Out
VSS 527 Ground
ORG/NC 6 N/A 8 Organization / 93XX66C
No Internal Connection / 93XX66A/B
NC 7 N/A 1 No Internal Connection
VCC 8 6 2 Power Supply
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 12 2003 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Legend: XX...X Part number
T Temperature
Blank Commercial
I Industrial
E Extended
YY Year code (last 2 digits of calendar year) except TSSOP
and MSOP which use only the last 1 digit
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: Custom marking available.
Example:
6-Lead SOT-23
8-Lead MSOP (150 mil) Example:
XXXXXXT
YWWNNN
3L66BI
2281L7
XXNN 3EL7
XXXXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC
XXXXYYWW
XXXXXXXX
NNN
XXXX
TYWW
8-Lead TSSOP
NNN
I/P 1L7
93LC66B
0228
Example:
Example:
I/SN 0228
93LC66B
1L7
1L7
L66B
I228
Example:
MSOP 1st Line Marking Codes
Device
93AA66A
93AA66B
93AA66C
93LC66A
93LC66B
93LC66C
93C66A
93C66B
93C66C
std mark
3A66AT
3A66BT
3A66CT
3L66AT
3L66BT
3L66CT
3C66AT
3C66BT
3C66CT
Pb-free
mark
GA66AT
GA66BT
GA66CT
GL66AT
GL66BT
GL66CT
GC66AT
GC66BT
GC66CT
T = blank for commercial, “I” for Industrial,
“E” for Extended.
TSSOP 1st Line Marking Codes
Device
93AA66A
93AA66B
93AA66C
93LC66A
93LC66B
93LC66C
93C66A
93C66B
93C66C
std mark
A66A
A66B
A66C
L66A
L66B
L66C
C66A
C66B
C66C
Pb-free
mark
GACA
GACB
GACC
GLCA
GLCB
GLCC
GCCA
GCCB
GCCC
Temperature grade is marked on line 2.
SOT23 Marking Codes
Device
93AA66A
93AA66B
93LC66A
93LC66B
93C66A
93C66B
I-temp
3BNN
3LNN
3ENN
3PNN
3HNN
3TNN
E-temp
3FNN
3RNN
3JNN
3UNN
Pb-free topside mark is same; Pb-free
noted only on carton label.
2003 Microchip Technology Inc. DS21795A-page 13
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REF
FFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0.23
0.40
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX
NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15° -
15° -
JEDEC Equivalent: MO-187
-
-
-
15°
15°
--
-
-
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 14 2003 Microchip Technology Inc.
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
φ
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059
E1
Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000
A1
Standoff
1.301.100.90.051.043.035
A2
Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
66
n
Number of Pins
MAX
NOM
MINMAX
NOM
MINDimension Limits
MILLIMETERSINCHES*Units
1
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
exceed .005" (0.127mm) per side.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
Notes:
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
*Controlling Parameter
2003 Microchip Technology Inc. DS21795A-page 15
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
Mold Draft Angle Bottom β5 10 15 5 10 15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 16 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146
E1
Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004
A1
Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2003 Microchip Technology Inc. DS21795A-page 17
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
3.103.002.90.122.118.114DMolded Package Length
4.504.404.30.177.173.169
E1
Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033
A2
Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
φ
1
2
D
n
p
B
E
E1
Foot Angle φ048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 18 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21795A-page 19
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Latest Microchip Press Releases
Technical Support Section with Frequently Asked
Questions
Design Tips
Device Errata
Job Postings
Microchip Consultant Program Member Listing
Links to other useful web sites related to
Microchip Products
Conferences for products, Development Systems,
technical information and more
Listing of seminars and events
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 20 2003 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21795A93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2003 Microchip Technology Inc. DS21795A-page 21
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Device 93AA66A: 4K 1.8V Microwire Serial EEPROM
93AA66B: 4K 1.8V Microwire Serial EEPROM
93AA66C: 4K 1.8V Microwire Serial EEPROM w/ORG
93LC66A: 4K 2.5V Microwire Serial EEPROM
93LC66B: 4K 2.5V Microwire Serial EEPROM
93LC66C: 4K 2.5V Microwire Serial EEPROM w/ORG
93C66A: 4K 5.0V Microwire Serial EEPROM
93C66B: 4K 5.0V Microwire Serial EEPROM
93C66C: 4K 5.0V Microwire Serial EEPROM w/ORG
Pinout: Blank = Standard pinout
X = Rotated pinout
Tape & Reel: Blank = Standard packaging
T = Tape & Reel
Temperature Range I = -40°C to +85°C
E = -40°C to +125°C
Package MS = Plastic MSOP (Micro Small outline, 8-lead)
OT = SOT-23, 6-lead (Tape & Reel only)
P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
ST = TSSOP, 8-lead
Lead Finish: Blank = Standard 63% / 37% SnPb
G = Pure Matte Sn
Examples:
a) 93AA66C-I/MS: 4K, 512x8 or 256x16 Serial
EEPROM, MSOP package, 1.8V
b) 93AA66B-I/MS: 4K, 256x16 Serial EEPROM,
MSOP package, 1.8V
c) 93AA66AT-I/OT: 4K, 512x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
d) 93AA66CT-I/MS: 4K, 512x8 or 256x16 Serial
EEPROM, MSOP package, tape and reel, 1.8V
a) 93LC66A-I/MS: 4K, 512x8 Serial EEPROM,
MSOP package, 2.5V
b) 93LC66BT-I/OT: 4K, 256x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
c) 93LC66B-I/MS: 4K, 256x16 Serial EEPROM,
MSOP package, 2.5V
d) 93LC66BXT-I/SNG: 4K, 256x16 Serial
EEPROM, SOIC package, rotated pinout,
Industrial temperature, Pb-free finish, 2.5V
a) 93C66B-I/MS: 4K, 256x16 Serial EEPROM,
MSOP package, 5.0V
b) 93C66C-I/MS: 4K, 512x8 or 256x16 Serial
EEPROM, MSOP package, 5.0V
c) 93C66AT-I/OT: 4K, 512x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
PART NO. X/XX
Package
Temperature
Range
Device
X
Lead Finish
X
Tape & Reel
X
Pinout
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795A-page 22 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21795A - page 23
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise.
Use of Microchip’s products as critical components in life
support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, Application Maestro, dsPIC, dsPICDEM,
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
DS21795A-page 24 2003 Microchip Technology Inc.
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03/25/03
WORLDWIDE SALES AND SERVICE