STM8S003K3 STM8S003F3
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes
data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
LQFP32 7x7 TSSOP20 UFQFPN20 3x3
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbytes Flash; data retention
20 years at 55 °C after 100 cycles
RAM: 1 Kbytes
Data memory: 128 bytes of true data EEPROM;
endurance up to 100 000 write/erase cycles
Clock, reset and supply management
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
-Low power crystal resonator oscillator
-External clock input
-Internal, user-trimmable 16 MHz RC
-Internal low power 128 kHz RC
Clock security system with clock monitor
Power management:
-Low power modes (wait, active-halt, halt)
-Switch-off peripheral clocks individually
Permanently active, low consumption power-on
and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window watchdog and independent watchdog
timers
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21
high sink outputs
Highly robust I/O design, immune against current
injection
Development support
Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
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DocID018576 Rev 3
June 2012
www.st.com
Contents
1 Introduction ..............................................................................................................7
2 Description ...............................................................................................................8
3 Block diagram ..........................................................................................................9
4 Product overview ...................................................................................................10
4.1 Central processing unit STM8 .....................................................................................10
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................10
4.3 Interrupt controller .......................................................................................................11
4.4 Flash program memory and data EEPROM ................................................................11
4.5 Clock controller ............................................................................................................12
4.6 Power management ....................................................................................................13
4.7 Watchdog timers ..........................................................................................................13
4.8 Auto wakeup counter ...................................................................................................14
4.9 Beeper ........................................................................................................................14
4.10 TIM1 - 16-bit advanced control timer .........................................................................14
4.11 TIM2 - 16-bit general purpose timer ..........................................................................15
4.12 TIM4 - 8-bit basic timer ..............................................................................................15
4.13 Analog-to-digital converter (ADC1) ............................................................................15
4.14 Communication interfaces .........................................................................................16
4.14.1 UART1 ...............................................................................................16
4.14.2 SPI .....................................................................................................17
4.14.3 I²C ......................................................................................................17
5 Pinout and pin description ...................................................................................18
5.1 STM8S003K3 LQFP32 pinout and pin description ......................................................18
5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description ...............................21
5.2.1 STM8S003F3 TSSOP20 pinout and pin description ............................21
5.2.2 STM8S003F3 UFQFPN20 pinout ........................................................22
5.2.3 STM8S003F3 TSSOP20/UFQFPN20 pin description ..........................22
5.3 Alternate function remapping .......................................................................................24
6 Memory and register map .....................................................................................25
6.1 Memory map ................................................................................................................25
6.2 Register map ...............................................................................................................26
6.2.1 I/O port hardware register map ............................................................26
6.2.2 General hardware register map ..........................................................27
6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................36
7 Interrupt vector mapping ......................................................................................39
8 Option bytes ...........................................................................................................41
8.1 Alternate function remapping bits ................................................................................43
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STM8S003K3 STM8S003F3Contents
9 Electrical characteristics ......................................................................................46
9.1 Parameter conditions ...................................................................................................46
9.1.1 Minimum and maximum values ...........................................................46
9.1.2 Typical values .......................................................................................46
9.1.3 Typical curves ......................................................................................46
9.1.4 Loading capacitor .................................................................................46
9.1.5 Pin input voltage ...................................................................................46
9.2 Absolute maximum ratings ..........................................................................................47
9.3 Operating conditions ....................................................................................................49
9.3.1 VCAP external capacitor ......................................................................50
9.3.2 Supply current characteristics ..............................................................51
9.3.3 External clock sources and timing characteristics ...............................60
9.3.4 Internal clock sources and timing characteristics .................................62
9.3.5 Memory characteristics ........................................................................64
9.3.6 I/O port pin characteristics ...................................................................66
9.3.7 Reset pin characteristics ......................................................................74
9.3.8 SPI serial peripheral interface ..............................................................77
9.3.9 I2C interface characteristics .................................................................80
9.3.10 10-bit ADC characteristics ..................................................................81
9.3.11 EMC characteristics ...........................................................................85
10 Package information ...........................................................................................89
10.1 32-pin LQFP package mechanical data ....................................................................89
10.2 20-pin TSSOP package mechanical data ..................................................................90
10.3 20-lead UFQFPN package mechanical data .............................................................92
11 Thermal characteristics .......................................................................................94
11.1 Reference document .................................................................................................94
11.2 Selecting the product temperature range ..................................................................94
12 Ordering information ...........................................................................................96
13 STM8 development tools ....................................................................................97
13.1 Emulation and in-circuit debugging tools ...................................................................97
13.2 Software tools ............................................................................................................97
13.2.1 STM8 toolset ......................................................................................98
13.2.2 C and assembly toolchains ................................................................98
13.3 Programming tools ....................................................................................................98
14 Revision history ...................................................................................................99
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ContentsSTM8S003K3 STM8S003F3
List of tables
Table 1. STM8S003xx value line features ................................................................................................8
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................13
Table 3. TIM timer features ....................................................................................................................15
Table 4. Legend/abbreviations for pinout tables ...................................................................................18
Table 5. LQFP32 pin description ............................................................................................................19
Table 6. STM8S003F3 pin description ...................................................................................................22
Table 7. I/O port hardware register map ................................................................................................26
Table 8. General hardware register map ...............................................................................................27
Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................36
Table 10. Interrupt mapping ...................................................................................................................39
Table 11. Option bytes ...........................................................................................................................99
Table 12. Option byte description ...........................................................................................................41
Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices ......................................43
Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices ......................................44
Table 15. Voltage characteristics ...........................................................................................................47
Table 16. Current characteristics ...........................................................................................................47
Table 17. Thermal characteristics ..........................................................................................................48
Table 18. General operating conditions .................................................................................................49
Table 19. Operating conditions at power-up/power-down ......................................................................50
Table 20. Total current consumption with code execution in run mode at VDD = 5 V .............................51
Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................52
Table 22. Total current consumption in wait mode at VDD = 5 V ............................................................53
Table 23. Total current consumption in wait mode at VDD = 3.3 V .........................................................53
Table 24. Total current consumption in active halt mode at VDD = 5 V ..................................................54
Table 25. Total current consumption in active halt mode at VDD = 3.3 V ...............................................54
Table 26. Total current consumption in halt mode at VDD = 5 V .............................................................55
Table 27. Total current consumption in halt mode at VDD = 3.3 V ..........................................................55
Table 28. Wakeup times .........................................................................................................................56
Table 29. Total current consumption and timing in forced reset state ....................................................57
Table 30. Peripheral current consumption .............................................................................................57
Table 31. HSE user external clock characteristics .................................................................................60
Table 32. HSE oscillator characteristics .................................................................................................61
Table 33. HSI oscillator characteristics ..................................................................................................62
Table 34. LSI oscillator characteristics ...................................................................................................64
Table 35. RAM and hardware registers ..................................................................................................64
Table 36. Flash program memory and data EEPROM ...........................................................................65
Table 37. I/O static characteristics .........................................................................................................66
Table 38. Output driving current (standard ports) ..................................................................................68
Table 39. Output driving current (true open drain ports) ........................................................................68
Table 40. Output driving current (high sink ports) ..................................................................................69
Table 41. NRST pin characteristics ........................................................................................................74
Table 42. SPI characteristics ..................................................................................................................78
Table 43. I2C characteristics ..................................................................................................................80
Table 44. ADC characteristics ................................................................................................................82
Table 45. ADC accuracy with RAIN < 10 , VDD= 5 V .........................................................................82
Table 46. ADC accuracy with RAIN < 10 RAIN, VDD = 3.3 V ..............................................................83
Table 47. EMS data ................................................................................................................................86
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STM8S003K3 STM8S003F3List of tables
Table 48. EMI data .................................................................................................................................86
Table 49. ESD absolute maximum ratings .............................................................................................87
Table 50. Electrical sensitivities .............................................................................................................88
Table 51. 32-pin low profile quad flat package mechanical data ............................................................89
Table 52. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .........................................................91
Table 53. 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data ......................92
Table 54. Thermal characteristics ..........................................................................................................94
Table 55. Document revision history ......................................................................................................99
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List of tablesSTM8S003K3 STM8S003F3
List of figures
Figure 1. Block diagram ...........................................................................................................................9
Figure 2. Flash memory organization ....................................................................................................12
Figure 3. STM8S003K3 LQFP32 pinout ................................................................................................18
Figure 4. STM8S003F3 TSSOP20 pinout ..............................................................................................21
Figure 5. STM8S003F3 UFQFPN20-pin pinout .....................................................................................22
Figure 6. Memory map ...........................................................................................................................25
Figure 7. Pin loading conditions .............................................................................................................46
Figure 8. Pin input voltage .....................................................................................................................47
Figure 9. fCPUmax versus VDD ................................................................................................................50
Figure 10. External capacitor CEXT .......................................................................................................50
Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................58
Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................58
Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................59
Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................59
Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................60
Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................60
Figure 17. HSE external clock source ....................................................................................................61
Figure 18. HSE oscillator circuit diagram ...............................................................................................62
Figure 19. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................63
Figure 20. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................64
Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................67
Figure 22. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................67
Figure 23. Typical pull-up current vs VDD @ 4 temperatures .................................................................68
Figure 24. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................70
Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................70
Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................71
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................71
Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................72
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................72
Figure 30. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................73
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................73
Figure 32. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................74
Figure 33. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................74
Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................76
Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................76
Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................77
Figure 37. Recommended reset pin protection ......................................................................................77
Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................79
Figure 39. SPI timing diagram - slave mode and CPHA = 1 ..................................................................79
Figure 40. SPI timing diagram - master mode(1) ...................................................................................80
Figure 41. Typical application with I2C bus and timing diagram ............................................................84
Figure 42. ADC accuracy characteristics ...............................................................................................84
Figure 43. Typical application with ADC ................................................................................................85
Figure 44. 32-pin low profile quad flat package (7 x 7) ..........................................................................89
Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................90
Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ....................................92
Figure 47. STM8S003x value line ordering information scheme ...........................................................96
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STM8S003K3 STM8S003F3List of figures
Introduction1
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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IntroductionSTM8S003K3 STM8S003F3
Description2
The STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory,
plus integrated true data EEPROM. The STM8S microcontroller family reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
performance, robustness, and reduced system cost.
Device performance and robustness are ensured by integrated true data EEPROM supporting
up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art
technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate
clock source, and a clock security system.
The system cost is reduced thanks to high system integration level with internal clock
oscillators, watchdog and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Table 1: STM8S003xx value line features
STM8S003F3STM8S003K3Device
2032Pin count
1628Maximum number of GPIOs (I/Os)
1627Ext. interrupt pins
77Timer CAPCOM channels
23Timer complementary outputs
54A/D converter channels
1221High sink I/Os
8K8KLow density Flash program memory (bytes)
1K1KRAM (bytes)
128 (1)
128 (1)
True data EEPROM (bytes)
Multipurpose timer (TIM1), SPI, I2C, UART
window WDG,independent WDG, ADC, PWM
timer (TIM2), 8-bit timer (TIM4)
Peripheral set
(1) Without read-while-write capability.
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STM8S003K3 STM8S003F3Description
Block diagram3
Figure 1: Block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
SPI
UART1
16-bit general purpose
AWU timer
Reset block
Reset
POR BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
LIN master
Address and data bus
Window WDG
8-Kbyte
1-Kbyte
ADC1
4 CAPCOM
Reset
400 Kbit/s
Single wire
debug interf.
SPI emul.
channels +3
program
Flash
16-bit advanced
control timer (TIM1)
8-bit basic timer
RAM Up to
Beeper
1/2/4 kHz
beep
Independent WDG
(TIM4)
3 CAPCOM
channels
Up to
complementary
outputs
timer (TIM2)
Up to 5
channels
I2C
128-byte
data EEPROM
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Block diagramSTM8S003K3 STM8S003F3
Product overview4
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM84.1
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Single wire interface module (SWIM) and debug module (DM)4.2
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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STM8S003K3 STM8S003F3Product overview
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
Interrupt controller4.3
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 27 external interrupts on 6 vectors including TLI
Trap and reset interrupts
Flash program memory and data EEPROM4.4
8 Kbytes of Flash program single voltage Flash memory
128 bytes of true data EEPROM
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
the data EEPROM, and the option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to modify the content
of the main program memory and data EEPROM, or to reprogram the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: 8 Kbytes minus UBC
User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
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Product overviewSTM8S003K3 STM8S003F3
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organization
UBC area
Program memory area
Remains write protected during IAP
Write access possible for IAP
Option bytes
Programmable
bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
area from 64
Low density
Flash program
memory
(8 Kbytes)
Data EEPROM (128 bytes)
Read-out protection (ROP)
The read-out protection blocks reading and writing from/to the Flash program memory and
the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program memory. Even if no
protection can be considered as totally unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
Clock controller4.5
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-1-16 MHz high-speed external crystal (HSE)
-Up to 16 MHz high-speed user-external clock (HSE user-ext)
-16 MHz high-speed internal RC oscillator (HSI)
-128 kHz low-speed internal RC (LSI)
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STM8S003K3 STM8S003F3Product overview
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
BitPeripheral
clock
BitPeripheral
clock
BitPeripheral
clock
Bit
ADCPCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17
AWUPCKEN22ReservedPCKEN26ReservedPCKEN12ReservedPCKEN16
ReservedPCKEN21ReservedPCKEN25SPIPCKEN11TIM2PCKEN15
ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM4PCKEN14
Power management4.6
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
Watchdog timers4.7
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
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Product overviewSTM8S003K3 STM8S003F3
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
Auto wakeup counter4.8
Used for auto wakeup from active halt mode
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
Beeper4.9
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
TIM1 - 16-bit advanced control timer4.10
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
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STM8S003K3 STM8S003F3Product overview
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2 - 16-bit general purpose timer4.11
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
3 individually configurable capture/compare channels
PWM mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
TIM4 - 8-bit basic timer4.12
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 3: TIM timer features
Timer
synchronization/
chaining
Ext.
trigger
Complem.
outputs
CAPCOM
channels
Counting
mode
Prescaler
Counter
size (bits)
Timer
No
Yes34Up/down
Any integer
from 1 to
65536
16TIM1
No03Up
Any power of
2 from 1 to
32768
16TIM2
No00Up
Any power of
2 from 1 to
128
8TIM4
Analog-to-digital converter (ADC1)4.13
The STM8S003xx products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 5 external multiplexed inputs channels and the following features:
Input voltage range: 0 to VDD
Conversion time: 14 clock cycles
Single and continuous and buffered continuous conversion modes
Buffer size (n x 10 bits) where n = number of input channels
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
15/100DocID018576 Rev 3
Product overviewSTM8S003K3 STM8S003F3
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Communication interfaces4.14
The following communication interfaces are implemented:
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
SPI : Full and half-duplex, 8 Mbit/s
I²C: Up to 400 Kbit/s
UART14.14.1
Main features
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
-Address bit (MSB)
-Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
DocID018576 Rev 316/100
STM8S003K3 STM8S003F3Product overview
SPI4.14.2
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
I²C4.14.3
I²C master features:
-Clock generation
-Start and stop generation
I²C slave features:
-Programmable I2C address detection
-Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
-Standard speed (up to 100 kHz)
-Fast speed (up to 400 kHz)
17/100DocID018576 Rev 3
Product overviewSTM8S003K3 STM8S003F3
Pinout and pin description5
Table 4: Legend/abbreviations for pinout tables
I= Input, O = Output, S = Power supplyType
CM = CMOS
InputLevel
HS = High sinkOutput
O1 = Slow (up to 2 MHz)
Output speed
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating, wpu = weak pull-upInputPort and control
configuration T = True open drain, OD = Open drain, PP =
Push pull
Output
Bold X(pin state after internal reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
STM8S003K3 LQFP32 pinout and pin description5.1
Figure 3: STM8S003K3 LQFP32 pinout
I2C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH3N/ AIN2/(HS) PB2
TIM1_CH2N/ AIN1/(HS) PB1
TIM1_CH1N/AIN0/(HS) PB0
PB7
PB6
I2C_SDA/ (T) PB5
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
VCAP
VDD
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
NRST
OSCIN/PA1
OSCOUT/PA2
VSS PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS) [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/ TIM1_BKIN [CLK_CCO]
PD7 (HS)/TLI [TIM1_CH4]
PD6 (HS)/UART1_RX
PD5 (HS)/UART1_TX
PD4 (HS)/BEEP/TIM2_CH1
DocID018576 Rev 318/100
STM8S003K3 STM8S003F3Pinout and pin description
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 5: LQFP32 pin description
Alternate
function
after remap
[option bit]
Default
alternate
function
Main
function
(after reset)
OutputInput
Type
Pin
name
Pin
no. PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
ResetXI/ONRST1
Resonator/
crystal in
Port A1XXO1XXXI/O
PA1/ OSCI (2)
2
Resonator/
crystal out
Port A2XXO1XXXI/OPA2/ OSCOUT3
Digital groundSVSS
4
1.8 V regulator capacitorSVCAP5
Digital power supplySVDD
6
SPI master/
slave select
[AFR1]
Timer 2
channel 3
Port A3XXO3HSXXXI/OPA3/
TIM2_CH3
[SPI_NSS]
7
Port F4XXO1XXI/OPF48
Port B7XXO1XXXI/OPB79
Port B6XXO1XXXI/OPB610
I2C dataPort B5
T(3)
O1XXI/OPB5/ I2C_SDA11
I2C clockPort B4
T(3)
O1XXI/OPB4/ I2C_SCL12
Analog input 3/
Timer 1
external trigger
Port B3XXO3HSXXXI/OPB3/AIN3/
TIM1_ETR
13
Analog input 2/
Timer 1 -
Port B2XXO3HSXXXI/OPB2/AIN2/
TIM1_CH3N
14
inverted
channel 3
19/100DocID018576 Rev 3
Pinout and pin descriptionSTM8S003K3 STM8S003F3
Alternate
function
after remap
[option bit]
Default
alternate
function
Main
function
(after reset)
OutputInput
Type
Pin
name
Pin
no. PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
Analog input 1/
Timer 1 -
Port B1XXO3HSXXXI/OPB1/AIN1/
TIM1_CH2N
15
inverted
channel 2
Analog input 0/
Timer 1 -
Port B0XXO3HSXXXI/OPB0/AIN0/
TIM1_CH1N
16
inverted
channel 1
SPI
master/slave
select
Port E5XXO3HSXXXI/OPE5/
SPI_NSS
17
Timer 1 -
channel 1
UART1 clock
Port C1XXO3HSXXXI/OPC1/
TIM1_CH1/
UART1_CK
18
Timer 1 -
channel 2
Port C2XXO3HSXXXI/OPC2/
TIM1_CH2
19
Timer 1 -
channel 3
Port C3XXO3HSXXXI/OPC3/
TIM1_CH3
20
Timer 1 -
channel 4
Port C4XXO3HSXXXI/OPC4/
TIM1_CH4/
CLK_CCO
21
/configurable
clock output
SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_SCK22
SPI master
out/slave in
Port C6XXO3HSXXXI/OPC6/ PI_MOSI23
SPI master in/
slave out
Port C7XXO3HSXXXI/OPC7/ PI_MISO24
Configurable
clock output
[AFR5]
Timer 1 - break
input
Port D0XXO3HSXXXI/OPD0/
TIM1_BKIN
[CLK_CCO]
25
SWIM data
interface
Port D1XXO4HSXXXI/OPD1/ SWIM
(4)
26
Timer 2 -
channel
3[AFR1]
Port D2XXO3HSXXXI/OPD2
[TIM2_CH3]
27
DocID018576 Rev 320/100
STM8S003K3 STM8S003F3Pinout and pin description
Alternate
function
after remap
[option bit]
Default
alternate
function
Main
function
(after reset)
OutputInput
Type
Pin
name
Pin
no. PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
Timer 2 -
channel 2/ADC
external trigger
Port D3XXO3HSXXXI/OPD3/
TIM2_CH2/
ADC_ETR
28
Timer 2 -
channel
1/BEEP output
Port D4XXO3HSXXXI/OPD4/BEEP/
TIM2_CH1
29
UART1 data
transmit
Port D5XXO3HSXXXI/OPD5/
UART1_TX
30
UART1 data
receive
Port D6XXO3HSXXXI/OPD6/
UART1_RX
31
Timer 1 -
channel 4
[AFR6]
Top level
interrupt
Port D7XXO3HSXXXI/OPD7/ TLI
[TIM1_CH4]
32
(1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings (see Electrical characteristics).
(2) When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking
up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt
is used in the application.
(3)In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not
implemented).
(4)The PD1 pin is in input pull-up during the reset phase and after internal reset release.
STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description5.2
STM8S003F3 TSSOP20 pinout and pin description5.2.1
Figure 4: STM8S003F3 TSSOP20 pinout
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
NRST
VDD
VCAP
VSS
OSCOUT/PA2
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD1(HS)/SWIM
PB4 (T)/I2C_SCL [ADC_ETR]
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC5 (HS)/SPI_SCK [TIM2_CH1]
12
11
9
10
[SPI_NSS] TIM2_CH3/(HS) PA3
PD2 (HS)/AIN3/[TIM2_CH3]
OSCIN/PA1
PB5 (T)/I2C_SDA [TIM1_BKIN]
UART1_TX/AIN5/(HS) PD5
UART1_RX/AIN6/(HS) PD6
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC7 (HS)/SPI_MISO [TIM1_CH2]
1. HS high sink capability.
21/100DocID018576 Rev 3
Pinout and pin descriptionSTM8S003K3 STM8S003F3
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
STM8S003F3 UFQFPN20 pinout5.2.2
Figure 5: STM8S003F3 UFQFPN20-pin pinout
2
1
3
4
5
6 7 8 9
11
12
13
14
15
16171819
VCAP
VSS
OSCOUT/PA2
OSCIN/PA1
[SPI_NSS] TIM2_CH3/(HS) PA3
NRST
PD4 (HS)/BEEP / TIM2_CH1/UART1_CK
PD5(HS)/AIN5/UART1_TX
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2(HS)/AIN3/{TIM2_CH3]
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC7(HS)/SPI_MISO[TIM1_CH2]
PD1(HS)/SWIM
[TIM1_BKIN] I2C_SDA/(T)PB5
10
[TIM1_CH1N] [TLI] TIM1_CH3 /(HS)PC3
PD6(HS)/AIN6/UART1_RX
20
VDD
[ADC_ETR] I2C_SCL/(T)PB4
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
STM8S003F3 TSSOP20/UFQFPN20 pin description5.2.3
Table 6: STM8S003F3 pin description
Alternate
function after
remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High
sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP20
Timer 2 -
channel
Port
D4
XXO3HSXXXI/OPD4/ BEEP/
TIM2_ CH1/
UART1 _CK
181
1/BEEP
output/
DocID018576 Rev 322/100
STM8S003K3 STM8S003F3Pinout and pin description
Alternate
function after
remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High
sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP20
UART1
clock
Analog
input 5/
Port
D5
XXO3HSXXXI/OPD5/ AIN5/
UART1 _TX
192
UART1
data
transmit
Analog
input 6/
Port
D6
XXO3HSXXXI/OPD6/ AIN6/
UART1 _RX
203
UART1
data
receive
ResetXI/ONRST14
Resonator/
crystal in
Port
A1
XXO1XXXI/OPA1/ OSCIN
(2)
25
Resonator/
crystal out
Port
A2
XXO1XXXI/OPA2/
OSCOUT
36
Digital groundSVSS
47
1.8 V regulator
capacitor
SVCAP58
Digital power supplySVDD
69
SPI master/
slave select
[AFR1]
Timer 2
channel 3
Port
A3
XXO3HSXXXI/OPA3/ TIM2_
CH3 [SPI_
NSS]
710
Timer 1 -
break input
[AFR4]
I2C dataPort
B5
T
(3)
O1XXI/OPB5/ I2C_
SDA [TIM1_
BKIN]
811
ADC external
trigger [AFR4]
I2C clockPort
B4
T(3)
O1XXI/OPB4/ I2C_
SCL
912
Top level
interrupt
Timer 1 -
channel 3
Port
C3
XXO3HSXXXI/OPC3/
TIM1_CH3
[TLI] [TIM1_
CH1N]
1013
[AFR3] Timer
1 - inverted
channel 1
[AFR7]
Timer 1 -
inverted
Configurable
clock
Port
C4
XXO3HSXXXI/OPC4/
CLK_CCO/
TIM1_
1114
channel 2
[AFR7]
output/Timer
1 - channel
4/Analog
input 2
CH4/AIN2/[TIM1_
CH2N]
Timer 2 -
channel 1
[AFR0]
SPI clockPort
C5
XXO3HSXXXI/OPC5/
SPI_SCK
[TIM2_ CH1]
1215
23/100DocID018576 Rev 3
Pinout and pin descriptionSTM8S003K3 STM8S003F3
Alternate
function after
remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High
sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP20
Timer 1 -
channel 1
[AFR0]
SPI master
out/slave in
Port
C6
XXO3HSXXXI/OPC6/
SPI_MOSI
[TIM1_ CH1]
1316
Timer 1 -
channel 2
[AFR0]
SPI master
in/ slave
out
Port
C7
XXO3HSXXXI/OPC7/
SPI_MISO
[TIM1_ CH2]
1417
SWIM data
interface
Port
D1
XXO4HSXXXI/OPD1/
SWIM(4)
1518
Timer 2 -
channel 3
[AFR1]
Analog
input 3
Port
D2
XXO3HSXXXI/OPD2/AIN3/[TIM2_
CH3]
1619
Analog
input 4/
Port
D3
XXO3HSXXXI/OPD3/ AIN4/
TIM2_ CH2/
ADC_ ETR
1720
Timer 2 -
channel
2/ADC
external
trigger
(1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings.
(2) When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking
up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt
is used in the application.
(3) In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
(4)The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Alternate function remapping5.3
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
DocID018576 Rev 324/100
STM8S003K3 STM8S003F3Pinout and pin description
Memory and register map6
Memory map6.1
Figure 6: Memory map
0x00 9FFF
Flash program memory
(8 Kbytes)
0x00 0000 RAM
0x00 03FF
(1 Kbyte)
513 bytes stack
Reserved
Reserved
0x00 A000
0x02 7FFF
0x00 47FF
0x00 8000 32 interrupt vectors
0x00 807F
GPIO and periph. reg.
0x00 5000
0x00 57FF
0x00 5800
0x00 7FFF
0x00 480B
0x00 4FFF
0x00 7EFF CPU/SWIM/debug/ITC
registers
0x00 7F00
Reserved
Option bytes
0x00 480A
0x00 4800
0x00 0800
0x00 8080
Reserved
0x00 407F Data EEPROM
0x00 4000
Reserved
25/100DocID018576 Rev 3
Memory and register mapSTM8S003K3 STM8S003F3
Register map6.2
I/O port hardware register map6.2.1
Table 7: I/O port hardware register map
Reset
status
Register nameRegister labelBlockAddress
0x00Port A data output latch registerPA_ODR
Port A
0x00 5000
0xXX(1)
Port A input pin value registerPA_IDR0x00 5001
0x00Port A data direction registerPA_DDR0x00 5002
0x00Port A control register 1PA_CR10x00 5003
0x00Port A control register 2PA_CR20x00 5004
0x00Port B data output latch registerPB_ODR
Port B
0x00 5005
0xXX(1)
Port B input pin value registerPB_IDR0x00 5006
0x00Port B data direction registerPB_DDR0x00 5007
0x00Port B control register 1PB_CR10x00 5008
0x00Port B control register 2PB_CR20x00 5009
0x00Port C data output latch registerPC_ODR
Port C
0x00 500A
0xXX(1)
Port C input pin value registerPB_IDR0x00 500B
0x00Port C data direction registerPC_DDR0x00 500C
0x00Port C control register 1PC_CR10x00 500D
0x00Port C control register 2PC_CR20x00 500E
0x00Port D data output latch registerPD_ODR
Port D
0x00 500F
0xXX(1)
Port D input pin value registerPD_IDR0x00 5010
0x00Port D data direction registerPD_DDR0x00 5011
0x02Port D control register 1PD_CR10x00 5012
0x00Port D control register 2PD_CR20x00 5013
0x00Port E data output latch registerPE_ODR
Port E
0x00 5014
0xXX(1)
Port E input pin value registerPE_IDR0x00 5015
0x00Port E data direction registerPE_DDR0x00 5016
0x00Port E control register 1PE_CR10x00 5017
DocID018576 Rev 326/100
STM8S003K3 STM8S003F3Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00Port E control register 2PE_CR2Port E0x00 5018
0x00Port F data output latch registerPF_ODR
Port F
0x00 5019
0xXX(1)
Port F input pin value registerPF_IDR0x00 501A
0x00Port F data direction registerPF_DDR0x00 501B
0x00Port F control register 1PF_CR10x00 501C
0x00Port F control register 2PF_CR20x00 501D
(1)Depends on the external circuitry.
General hardware register map6.2.2
Table 8: General hardware register map
Reset
status
Register nameRegister labelBlockAddress
Reserved area (60 bytes)0x00 501E to
0x00 5059
0x00Flash control register 1FLASH_CR1
Flash0x00 505A
0x00Flash control register 2FLASH_CR20x00 505B
0xFFFlash complementary control register 2FLASH_NCR20x00 505C
0x00Flash protection registerFLASH _FPR0x00 505D
0xFFFlash complementary protection registerFLASH _NFPR0x00 505E
0x00Flash in-application programming status
register
FLASH _IAPSR0x00 505F
Reserved area (2 bytes)0x00 5060 to
0x00 5061
0x00Flash program memory unprotection
register
FLASH _PUKRFlash0x00 5062
27/100DocID018576 Rev 3
Memory and register mapSTM8S003K3 STM8S003F3
Reset
status
Register nameRegister labelBlockAddress
Reserved area (1 byte)0x00 5063
0x00Data EEPROM unprotection registerFLASH_DUKRFlash0x00 5064
Reserved area (59 bytes)0x00 5065 to
0x00 509F
0x00External interrupt control register 1EXTI_CR1ITC0x00 50A0
0x00External interrupt control register 2EXTI_CR20x00 50A1
Reserved area (17 bytes)0x00 50A2 to
0x00 50B2
0xXX(1)
Reset status registerRST_SRRST0x00 50B3
Reserved area (12 bytes)0x00 50B4 to
0x00 50BF
0x01Internal clock control registerCLK_ICKRCLK0x00 50C0
0x00External clock control registerCLK_ECKR0x00 50C1
Reserved area (1 byte)0x00 50C2
0xE1Clock master status registerCLK_CMSRCLK0x00 50C3
0xE1Clock master switch registerCLK_SWR0x00 50C4
0xXXClock switch control registerCLK_SWCR0x00 50C5
0x18Clock divider registerCLK_CKDIVR0x00 50C6
0xFFPeripheral clock gating register 1CLK_PCKENR10x00 50C7
0x00Clock security system registerCLK_CSSR0x00 50C8
0x00Configurable clock control registerCLK_CCOR0x00 50C9
0xFFPeripheral clock gating register 2CLK_PCKENR20x00 50CA
DocID018576 Rev 328/100
STM8S003K3 STM8S003F3Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00HSI clock calibration trimming registerCLK_HSITRIMR0x00 50CC
0bXXXX
XXX0
SWIM clock control registerCLK_SWIMCCR0x00 50CD
ReservLK ed area (3 bytes)0x00 50CE to
0x00 50D0
0x7FWWDG control registerWWDG_CRWWDG0x00 50D1
0x7FWWDR window registerWWDG_WR0x00 50D2
Reserved area (13 bytes)0x00 50D3 to 00
50DF
0xXX(2)
IWDG key registerIWDG_KRIWDG0x00 50E0
0x00IWDG prescaler registerIWDG_PR0x00 50E1
0xFFIWDG reload registerIWDG_RLR0x00 50E2
Reserved area (13 bytes)0x00 50E3 to
0x00 50EF
0x00AWU control/status register 1AWU_CSR1AWU0x00 50F0
0x3FAWU asynchronous prescaler buffer
register
AWU_APR0x00 50F1
0x00AWU timebase selection registerAWU_TBR0x00 50F2
0x1FBEEP control/status registerBEEP_CSRBEEP0x00 50F3
Reserved area (12 bytes)0x00 50F4 to
0x00 50FF
0x00SPI control register 1SPI_CR1SPI0x00 5200
0x00SPI control register 2SPI_CR20x00 5201
29/100DocID018576 Rev 3
Memory and register mapSTM8S003K3 STM8S003F3
Reset
status
Register nameRegister labelBlockAddress
0x00SPI interrupt control registerSPI_ICR0x00 5202
0x02SPI status registerSPI_SR0x00 5203
0x00SPI data registerSPI_DR0x00 5204
0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205
0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206
0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207
Reserved area (8 bytes)0x00 5208 to
0x00 520F
0x00I2C control register 1I2C_CR1I2C0x00 5210
0x00I2C control register 2I2C_CR20x00 5211
0x00I2C frequency registerI2C_FREQR0x00 5212
0x00I2C Own address register lowI2C_OARL0x00 5213
0x00I2C Own address register highI2C_OARH0x00 5214
Reserved0x00 5215
0x00I2C data registerI2C_DR0x00 5216
0x00I2C status register 1I2C_SR10x00 5217
0x00I2C status register 2I2C_SR20x00 5218
0x0XI2C status register 3I2C_SR30x00 5219
0x00I2C interrupt control registerI2C_ITR0x00 521A
0x00I2C Clock control register lowI2C_CCRL0x00 521B
DocID018576 Rev 330/100
STM8S003K3 STM8S003F3Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00I2C Clock control register highI2C_CCRH0x00 521C
0x02I2C TRISE registerI2C_TRISER0x00 521D
0x00I2C packet error checking registerI2C_PECR0x00 521E
Reserved area (17 bytes)0x00 521F to
0x00 522F
0xC0UART1 status registerUART1_SRUART10x00 5230
0xXXUART1 data registerUART1_DR0x00 5231
0x00UART1 baud rate register 1UART1_BRR10x00 5232
0x00UART1 baud rate register 2UART1_BRR20x00 5233
0x00UART1 control register 1UART1_CR10x00 5234
0x00UART1 control register 2UART1_CR20x00 5235
0x00UART1 control register 3UART1_CR30x00 5236
0x00UART1 control register 4UART1_CR40x00 5237
0x00UART1 control register 5UART1_CR50x00 5238
0x00UART1 guard time registerUART1_GTR0x00 5239
0x00UART1 prescaler registerUART1_PSCR0x00 523A
Reserved area (21 bytes)0x00 523B to
0x00 523F
0x00TIM1 control register 1TIM1_CR1TIM10x00 5250
0x00TIM1 control register 2TIM1_CR20x00 5251
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Memory and register mapSTM8S003K3 STM8S003F3
Reset
status
Register nameRegister labelBlockAddress
0x00TIM1 slave mode control registerTIM1_SMCR0x00 5252
0x00TIM1 external trigger registerTIM1_ETR0x00 5253
0x00TIM1 interrupt enable registerTIM1_IER0x00 5254
0x00TIM1 status register 1TIM1_SR10x00 5255
0x00TIM1 status register 2TIM1_SR20x00 5256
0x00TIM1 event generation registerTIM1_EGR0x00 5257
0x00TIM1 capture/compare mode register 1TIM1_CCMR10x00 5258
0x00TIM1 capture/compare mode register 2TIM1_CCMR20x00 5259
0x00TIM1 capture/compare mode register 3TIM1_CCMR30x00 525A
0x00TIM1 capture/compare mode register 4TIM1_CCMR40x00 525B
0x00TIM1 capture/compare enable register 1TIM1_CCER10x00 525C
0x00TIM1 capture/compare enable register 2TIM1_CCER20x00 525D
0x00TIM1 counter highTIM1_CNTRH0x00 525E
0x00TIM1 counter lowTIM1_CNTRL0x00 525F
0x00TIM1 prescaler register highTIM1_PSCRH0x00 5260
0x00TIM1 prescaler register lowTIM1_PSCRL0x00 5261
0xFFTIM1 auto-reload register highTIM1_ARRH0x00 5262
0xFFTIM1 auto-reload register lowTIM1_ARRL0x00 5263
0x00TIM1 repetition counter registerTIM1_RCR0x00 5264
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STM8S003K3 STM8S003F3Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00TIM1 capture/compare register 1 highTIM1_CCR1H0x00 5265
0x00TIM1 capture/compare register 1 lowTIM1_CCR1L0x00 5266
0x00TIM1 capture/compare register 2 highTIM1_CCR2H0x00 5267
0x00TIM1 capture/compare register 2 lowTIM1_CCR2L0x00 5268
0x00TIM1 capture/compare register 3 highTIM1_CCR3H0x00 5269
0x00TIM1 capture/compare register 3 lowTIM1_CCR3L0x00 526A
0x00TIM1 capture/compare register 4 highTIM1_CCR4H0x00 526B
0x00TIM1 capture/compare register 4 lowTIM1_CCR4L0x00 526C
0x00TIM1 break registerTIM1_BKR0x00 526D
0x00TIM1 dead-time registerTIM1_DTR0x00 526E
0x00TIM1 output idle state registerTIM1_OISR0x00 526F
Reserved area (147 bytes)0x00 5270 to
0x00 52FF
0x00TIM2 control register 1TIM2_CR1TIM20x00 5300
Reserved0x00 5301
Reserved0x00 5302
0x00TIM2 Interrupt enable registerTIM2_IER0x00 5303
0x00TIM2 status register 1TIM2_SR10x00 5304
0x00TIM2 status register 2TIM2_SR20x00 5305
0x00TIM2 event generation registerTIM2_EGR0x00 5306
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Memory and register mapSTM8S003K3 STM8S003F3
Reset
status
Register nameRegister labelBlockAddress
0x00TIM2 capture/compare mode register 1TIM2_CCMR10x00 5307
0x00TIM2 capture/compare mode register 2TIM2_CCMR20x00 5308
0x00TIM2 capture/compare mode register 3TIM2_CCMR30x00 5309
0x00TIM2 capture/compare enable register 1TIM2_CCER10x00 530A
0x00TIM2 capture/compare enable register 2TIM2_CCER20x00 530B
0x00TIM2 counter highTIM2_CNTRH0x00 530C
0x00TIM2 counter lowTIM2_CNTRL0x00 530D
0x00TIM2 prescaler registerTIM2_PSCR0x00 530E
0xFFTIM2 auto-reload register highTIM2_ARRH0x00 530F
0xFFTIM2 auto-reload register lowTIM2_ARRL0x00 5310
0x00TIM2 capture/compare register 1 highTIM2_CCR1H0x00 5311
0x00TIM2 capture/compare register 1 lowTIM2_CCR1L0x00 5312
0x00TIM2 capture/compare reg. 2 highTIM2_CCR2H0x00 5313
0x00TIM2 capture/compare register 2 lowTIM2_CCR2L0x00 5314
0x00TIM2 capture/compare register 3 highTIM2_CCR3H0x00 5315
0x00TIM2 capture/compare register 3 lowTIM2_CCR3L0x00 5316
Reserved area (43 bytes)0x00 5317 to
0x00 533F
0x00TIM4 control register 1TIM4_CR1TIM40x00 5340
Reserved0x00 5341
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STM8S003K3 STM8S003F3Memory and register map
Reset
status
Register nameRegister labelBlockAddress
Reserved0x00 5342
0x00TIM4 interrupt enable registerTIM4_IER0x00 5343
0x00TIM4 status registerTIM4_SR0x00 5344
0x00TIM4 event generation registerTIM4_EGR0x00 5345
0x00TIM4 counterTIM4_CNTR0x00 5346
0x00TIM4 prescaler registerTIM4_PSCR0x00 5347
0xFFTIM4 auto-reload registerTIM4_ARR0x00 5348
Reserved area (153 bytes)0x00 5349 to
0x00 53DF
0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to
0x00 53F3
Reserved area (12 bytes)0x00 53F4 to
0x00 53FF
0x00ADC control/status registerADC _CSRADC10x00 5400
0x00ADC configuration register 1ADC_CR10x00 5401
0x00ADC configuration register 2ADC_CR20x00 5402
0x00ADC configuration register 3ADC_CR30x00 5403
0xXXADC data register highADC_DRH0x00 5404
0xXXADC data register lowADC_DRL0x00 5405
0x00ADC Schmitt trigger disable register highADC_TDRH0x00 5406
0x00ADC Schmitt trigger disable register lowADC_TDRL0x00 5407
35/100DocID018576 Rev 3
Memory and register mapSTM8S003K3 STM8S003F3
Reset
status
Register nameRegister labelBlockAddress
0x03ADC high threshold register highADC_HTRH0x00 5408
0xFFADC high threshold register lowADC_HTRL0x00 5409
0x00ADC low threshold register highADC_LTRH0x00 540A
0x00ADC low threshold register lowADC_LTRL0x00 540B
0x00ADC analog watchdog status register
high
ADC_AWSRH0x00 540C
0x00ADC analog watchdog status register lowADC_AWSRL0x00 540D
0x00ADC analog watchdog control register
high
ADC _AWCRH0x00 540E
0x00ADC analog watchdog control register
low
ADC_AWCRL0x00 540F
Reserved area (1008 bytes)0x00 5410 to
0x00 57FF
(1)Depends on the previous reset source.
(2)Write only register.
CPU/SWIM/debug module/interrupt controller registers6.2.3
Table 9: CPU/SWIM/debug module/interrupt controller registers
Reset statusRegister nameRegister labelBlockAddress
0x00AccumulatorA
CPU(1)
0x00 7F00
0x00Program counter extendedPCE0x00 7F01
0x00Program counter highPCH0x00 7F02
0x00Program counter lowPCL0x00 7F03
0x00X index register highXH0x00 7F04
0x00X index register lowXL0x00 7F05
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STM8S003K3 STM8S003F3Memory and register map
Reset statusRegister nameRegister labelBlockAddress
0x00Y index register highYH0x00 7F06
0x00Y index register lowYL0x00 7F07
0x03Stack pointer highSPH0x00 7F08
0xFFStack pointer lowSPL0x00 7F09
0x28Condition code registerCCR0x00 7F0A
Reserved area (85 bytes)
0x00 7F0B to
0x00 7F5F
0x00Global configuration registerCFG_GCRCPU0x00 7F60
0xFFInterrupt software priority register 1ITC_SPR1
ITC
0x00 7F70
0xFFInterrupt software priority register 2ITC_SPR20x00 7F71
0xFFInterrupt software priority register 3ITC_SPR30x00 7F72
0xFFInterrupt software priority register 4ITC_SPR40x00 7F73
0xFFInterrupt software priority register 5ITC_SPR50x00 7F74
0xFFInterrupt software priority register 6ITC_SPR60x00 7F75
0xFFInterrupt software priority register 7ITC_SPR70x00 7F76
0xFFInterrupt software priority register 8ITC_SPR80x00 7F77
Reserved area (2 bytes)
0x00 7F78 to
0x00 7F79
0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80
Reserved area (15 bytes)
0x00 7F81 to
0x00 7F8F
0xFFDM breakpoint 1 register extended
byte
DM_BK1RE
DM
0x00 7F90
0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91
0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92
0xFFDM breakpoint 2 register extended
byte
DM_BK2RE0x00 7F93
0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94
0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95
0x00DM debug module control register 1DM_CR10x00 7F96
0x00DM debug module control register 2DM_CR20x00 7F97
37/100DocID018576 Rev 3
Memory and register mapSTM8S003K3 STM8S003F3
Reset statusRegister nameRegister labelBlockAddress
0x10DM debug module control/status
register 1
DM_CSR10x00 7F98
0x00DM debug module control/status
register 2
DM_CSR20x00 7F99
0xFFDM enable function registerDM_ENFCTR0x00 7F9A
Reserved area (5 bytes)0x00 7F9B to
0x00 7F9F
(1) Accessible by debug module only
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STM8S003K3 STM8S003F3Memory and register map
Interrupt vector mapping7
Table 10: Interrupt mapping
Vector addressWakeup from
active-halt mode
Wakeup from
halt mode
DescriptionSource
block
IRQ
no.
0x00 8000YesYesResetRESET
0x00 8004--Software interruptTRAP
0x00 8008--External top level interruptTLI0
0x00 800CYes-Auto wake up from haltAWU1
0x00 8010--Clock controllerCLK2
0x00 8014Yes(1)
Yes(1)
Port A external interruptsEXTI03
0x00 8018YesYesPort B external interruptsEXTI14
0x00 801CYesYesPort C external interruptsEXTI25
0x00 8020YesYesPort D external interruptsEXTI36
0x00 8024YesYesPort E external interruptsEXTI47
0x00 8028--Reserved8
0x00 802C--Reserved9
0x00 8030YesYesEnd of transferSPI10
0x00 8034--TIM1 update/ overflow/ underflow/
trigger/ break
TIM1
11
0x00 8038--TIM1 capture/ compareTIM112
0x00 803C--TIM2 update/ overflowTIM213
0x00 8040--TIM2 capture/ compareTIM214
0x00 8044--Reserved15
0x00 8048--Reserved16
0x00 804C--Tx completeUART117
0x00 8050--Receive register DATA FULLUART118
0x00 8054YesYesI2C interruptI2C19
0x00 8058--Reserved20
0x00 805C--Reserved21
0x00 8060--ADC1 end of conversion/ analog
watchdog interrupt
ADC1
22
39/100DocID018576 Rev 3
Interrupt vector mappingSTM8S003K3 STM8S003F3
Vector addressWakeup from
active-halt mode
Wakeup from
halt mode
DescriptionSource
block
IRQ
no.
0x00 8064--TIM4 update/ overflowTIM423
0x00 8068--EOP/WR_PG_DISFlash24
0x00 806C to
0x00 807C
Reserved
(1) Except PA1
DocID018576 Rev 340/100
STM8S003K3 STM8S003F3Interrupt vector mapping
Option bytes8
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Factory
default
setting
Option bitsOption
byte no.
Option
name
Addr.
01234567
0x00ROP [7:0]OPT0Read-out
protection
(ROP)
0x4800
0x00UBC [7:0]OPT1User boot
code(UBC)
0x4801
0xFFNUBC [7:0]NOPT10x4802
0x00AFR0AFR1AFR2AFR3AFR4AFR5
AFR6AFR7OPT2Alternate
function
0x4803
0xFFNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804 remapping
(AFR)
0x00WWDG
_HALT
WWDG
_HW
IWDG
_HW
LSI_ ENHSI
TRIM
ReservedOPT3Miscell.
option
0x4805h
0xFFNWW
G_HALT
NWWDG
_HW
NIWDG
_HW
NLSI_
EN
NHSI
TRIM
ReservedNOPT30x4806
0x00PRS C0PRS C1CKAWU
SEL
EXT CLKReservedOPT4Clock
option
0x4807
0xFFNPR
SC0
NPRSC1NCKA
WUSEL
NEXT
CLK
ReservedNOPT40x4808
0x00HSECNT [7:0]OPT5HSE clock
startup
0x4809
0xFFNHSECNT [7:0]NOPT50x480A
Table 12: Option byte description
DescriptionOption byte no.
ROP[7:0] Memory readout protection (ROP)
OPT0
0xAA: Enable readout protection (write access via SWIM protocol)
41/100DocID018576 Rev 3
Option bytesSTM8S003K3 STM8S003F3
DescriptionOption byte no.
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
OPT1
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected.
Page 0 and 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory
write-protected
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
AFR[7:0]
OPT2
Refer to following section for alternate function remapping decriptions
of bits [7:2] and [1:0] respectively.
HSITRIM:High speed internal clock trimming register size
OPT3
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN:Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
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STM8S003K3 STM8S003F3Option bytes
DescriptionOption byte no.
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
OPT4
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]:HSE crystal oscillator stabilization time
OPT5
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
Alternate function remapping bits8.1
Table 13: STM8S003K3 alternate function remapping bits for 32-pin devices
Description(1)
Option byte no.
AFR7 Alternate function remapping option 7
OPT2
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function(2).
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function(2).
43/100DocID018576 Rev 3
Option bytesSTM8S003K3 STM8S003F3
Description(1)
Option byte no.
1: Port D0 alternate function = CLK_CCO.
AFR[4:2] Alternate function remapping options 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2).
1: Port A3 alternate function = SPI_NSS; port D2 alternate function
= TIM2_CH3.
AFR0 Alternate function remapping option 0
Reserved.
(1) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
(2) Refer to pinout description.
Table 14: STM8S003F3 alternate function remapping bits for 20-pin devices
DescriptionOption byte no.
AFR7 Alternate function remapping option 7
OPT2
0: AFR7 remapping option inactive: Default alternate
functions(1).
1: Port C3 alternate function = TIM1_CH1N; port C4
alternate function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate
functions(1).
1: Port B4 alternate function = ADC_ETR; port B5
alternate function = TIM1_BKIN.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate
function(1).
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
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STM8S003K3 STM8S003F3Option bytes
DescriptionOption byte no.
Reserved
AFR1 Alternate function remapping option 1(2)
0: AFR1 remapping option inactive: Default alternate
functions(1).
1: Port A3 alternate function = SPI_NSS; port D2
alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0(2)
0: AFR0 remapping option inactive: Default alternate
functions(1).
1: Port C5 alternate function = TIM2_CH1; port C6
alternate function = TIM1_CH1; port C7 alternate
function = TIM1_CH2.
(1) Refer to pinout description.
(2) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
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Option bytesSTM8S003K3 STM8S003F3
Electrical characteristics9
Parameter conditions9.1
Unless otherwise specified, all voltages are referred to VSS.
Minimum and maximum values9.1.1
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA= 25 °C and TA= TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
Typical values9.1.2
Unless otherwise specified, typical data are based on TA= 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
Typical curves9.1.3
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Loading capacitor9.1.4
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 7: Pin loading conditions
50 pF
STM8 pin
Pin input voltage9.1.5
The input voltage measurement on a pin of the device is described in the following figure.
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STM8S003K3 STM8S003F3Electrical characteristics
Figure 8: Pin input voltage
STM8 pin
VIN
Absolute maximum ratings9.2
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15: Voltage characteristics
UnitMaxMinRatingsSymbol
V
6.5-0.3
Supply voltage(1)
VDDx - VSS
6.5VSS - 0.3
Input voltage on true open drain pins(2)
VIN
VDD + 0.3VSS - 0.3
Input voltage on any other pin(2)
mV
50
Variations between different power pins
|VDDx - VDD|
50
Variations between all the different ground
pins
|VSSx - VSS|
See "Absolute
maximum ratings
(electrical sensitivity)"
Electrostatic discharge voltage
VESD
(1) All power (VDD) and ground (VSS) pins must always be connected to the external power supply
(2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
Table 16: Current characteristics
Unit
Max(1)
RatingsSymbol
mA100
Total current into VDD power lines (source)(2)
IVDD
47/100DocID018576 Rev 3
Electrical characteristicsSTM8S003K3 STM8S003F3
Unit
Max(1)
RatingsSymbol
80
Total current out of VSS ground lines (sink)(2)
IVSS
20
Output current sunk by any I/O and control pin
IIO
- 20
Output current source by any I/Os and control pin
± 4
Injected current on NRST pin
IINJ(PIN)
(3) (4)
± 4
Injected current on OSCIN pin
± 4
Injected current on any other pin(5)
± 20
Total injected current (sum of all I/O and control pins)(5)
ΣI INJ(PIN)
(3)
(1) Data based on characterization results, not tested in production.
(2) All power (VDD) and ground (VSS) pins must always be connected to the external supply.
(3) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
(4) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
(5) When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum
of the positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 17: Thermal characteristics
UnitValueRatingsSymbol
°C
-65 to +150Storage temperature rangeTSTG
150Maximum junction temperatureTJ
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STM8S003K3 STM8S003F3Electrical characteristics
Operating conditions9.3
Table 18: General operating conditions
UnitMaxMinConditionsParameterSymbol
MHz160Internal CPU clock frequencyfCPU
V5.52.95Standard operating voltageVDD
nF3300470
CEXT: capacitance of
external capacitor
VCAP(1)
Ω0.3-
at 1 MHz(2)
ESR of external
capacitor
nH15-
ESL of external
capacitor
mW
238-TSSOP20
Power dissipation at TA= 85 °C
for suffix 6
PD
(3)
220-UFQFPN20
330-LQFP32
°C
85-40
Maximum power dissipationAmbient temperature for 6 suffix
version
TA
105-40
Junction temperature range for
suffix 6
TJ
(1)Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
(2)This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
(3)To calculate PDmax(TA), use the formula PDmax =(TJmax- TA)/ΘJA (see Thermal characteristics ) with the
value for TJmax given in the previous table and the value for ΘJA given in Thermal characteristics.
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Electrical characteristicsSTM8S003K3 STM8S003F3
Figure 9: fCPUmax versus VDD
Table 19: Operating conditions at power-up/power-down
UnitMaxTypMinConditionsParameterSymbol
μs/V
2VDD rise time rate
tVDD 2VDD fall time rate(1)
ms1.7VDD risingReset release delaytTEMP
V
2.852.72.6Power-on reset thresholdVIT+
2.82.652.5Brown-out reset thresholdVIT-
mV70Brown-out reset hysteresisVHYS(BOR)
(1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
VCAP external capacitor9.3.1
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
Figure 10: External capacitor CEXT
C
Rleak
ESR ESL
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
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STM8S003K3 STM8S003F3Electrical characteristics
Supply current characteristics9.3.2
The current consumption is measured as described in Pin input voltage.
Total current consumption in run mode9.3.2.1
The MCU is placed under the following conditions:
All I/O pins in input mode with a static value at VDD or VSS (no load)
All peripherals are disabled (clock stopped by peripheral clock gating registers) except if
explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 20: Total current consumption with code execution in run mode at VDD = 5 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
2.3HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from RAM
IDD(RUN)
2.352HSE user ext. clock (16 MHz)
21.7HSI RC osc. (16 MHz)
0.86HSE user ext. clock (16 MHz)fCPU = fMASTER/128 =
125 kHz 0.870.7HSI RC osc. (16 MHz)
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
0.550.41LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
4.5HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from Flash
4.754.3HSE user ext. clock (16 MHz)
4.53.7HSI RC osc. (16 MHz)
mA
1.050.84HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER =
2 MHz
Supply current
in run mode,
code executed
from Flash
IDD(RUN)
0.90.72HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
125 kHz
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
0.570.42LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 21: Total current consumption with code execution in run mode at VDD = 3.3 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
1.8HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from RAM
IDD(RUN)
2.32HSE user ext. clock (16 MHz)
21.5HSI RC osc. (16 MHz)
0.81HSE user ext. clock (16 MHz)fCPU = fMASTER/
128 = 125 kHz 0.870.7HSI RC osc. (16 MHz)
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/
128 = 15.625 kHz
0.550.41LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
4HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from Flash
4.73.9HSE user ext. clock (16 MHz)
4.53.7HSI RC osc. (16 MHz)
1.050.84HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER =
2 MHz
0.90.72HSI RC osc. (16 MHz)
fCPU = fMASTER/
128 = 125 kHz
0.580.46
HSI RC osc. (16 MHz/8)
fCPU = fMASTER/
128 = 15.625 kHz
0.570.42LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
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STM8S003K3 STM8S003F3Electrical characteristics
Total current consumption in wait mode9.3.2.2
Table 22: Total current consumption in wait mode at VDD = 5 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
1.6HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply
current in
wait mode
IDD(WFI)
1.31.1HSE user ext. clock (16 MHz)
1.10.89HSI RC osc. (16 MHz)
0.880.7HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
125 kHz
0.570.45HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER/128 =
15.625 kHz
0.540.4LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 23: Total current consumption in wait mode at VDD = 3.3 V
Unit
Max (1)
TypConditionsParameterSymbol
mA
1.1
HSE crystal osc.
(16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in wait mode
IDD(WFI)
1.31.1
HSE user ext. clock
(16 MHz)
1.10.89
HSI RC osc.
(16 MHz)
0.880.7
HSI RC osc.
(16 MHz)
fCPU = fMASTER/ 128 =
125 kHz
0.570.45
HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER/ 128 =
15.625 kHz
0.540.4
LSI RC osc.
(128 kHz)
fCPU = fMASTER=
128 kHz
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Total current consumption in active halt mode9.3.2.3
Table 24: Total current consumption in active halt mode at VDD = 5 V
Unit
Max
at 85
°C
(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
μA
1030
HSE crystal osc.
(16 MHz)
Operating modeOn
Supply current in
active halt mode
IDD(AH)
260200
LSI RC osc.
(128 kHz)
Operating modeOn
Supply current in
active halt mode
IDD(AH)
970
HSE crystal osc.
(16 MHz)
Power-down modeOn
Supply current in
active halt mode
IDD(AH)
200150
LSI RC osc.
(128 kHz)
Power-down modeOn
Supply current in
active halt mode
IDD(AH)
8566
LSI RC osc.
(128 kHz)
Operating mode
Off
Supply current in
active halt mode
IDD(AH)
2010
LSI RC osc.
(128 kHz)
Power-down mode
Supply current in
active halt mode
IDD(AH)
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Table 25: Total current consumption in active halt mode at VDD = 3.3 V
Unit
Max at
85 °C(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main voltage
regulator
(MVR)(2)
μA550
HSE crystal osc.
(16 MHz)
Operating modeOn
Supply current in
active halt mode
IDD(AH)
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STM8S003K3 STM8S003F3Electrical characteristics
Unit
Max at
85 °C(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main voltage
regulator
(MVR)(2)
μA
260200
LSI RC osc.
(128 kHz)
Operating mode
On
Supply current in
active halt mode
IDD(AH)
970
HSE crystal osc.
(16 MHz)
Power-down
mode
IDD(AH)
200150
LSI RC osc.
(128 kHz)
Supply current in
active halt mode
IDD(AH)
8066LSI RC osc.
(128 kHz)
Operating mode
Off
IDD(AH)
1810
Power-down
mode
IDD(AH)
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Total current consumption in halt mode9.3.2.4
Table 26: Total current consumption in halt mode at VDD = 5 V
Unit
Max at 85
°C(1)
TypConditionsParameterSymbol
μA
7563
Flash in operating mode, HSI clock
after wakeup
Supply current in halt
mode
IDD(H)
206.0
Flash in power-down mode, HSI
clock after wakeup
(1) Data based on characterization results, not tested in production
Table 27: Total current consumption in halt mode at VDD = 3.3 V
Unit
Max at 85
°C
(1)
TypConditionsParameterSymbol
μA7560
Flash in operating mode, HSI clock
after wakeup
Supply current in halt
mode
IDD(H)
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Electrical characteristicsSTM8S003K3 STM8S003F3
Unit
Max at 85
°C
(1)
TypConditionsParameterSymbol
174.5
Flash in power-down mode, HSI
clock after wakeup
(1) Data based on characterization results, not tested in production
Low power mode wakeup times9.3.2.5
Table 28: Wakeup times
Unit
Max(1)
TypConditionsParameterSymbol
μs
See
note(2)
0 to 16 MHz
Wakeup time from
wait mode to run
tWU(WFI)
0.56fCPU = fMASTER = 16 MHzmode(3)
2(6)
1(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
on(4)
Wakeup time active
halt mode to run
mode(3)
tWU(AH)
wakeup)
3(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
on(4)
mode(3)
48(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
off(4)
Wakeup time active
halt mode to run
mode(3) wakeup)
50(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
off(4)
mode(3)
52Flash in operating mode(5)
Wakeup time from
halt mode to run
tWU(H) 54Flash in power-down mode(5)
mode(3)
(1) Data guaranteed by design, not tested in production.
(2) tWU(WFI) = 2 x 1/fmaster + x 1/fCPU.
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STM8S003K3 STM8S003F3Electrical characteristics
(3) Measured from interrupt event to interrupt vector fetch.
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state9.3.2.6
Table 29: Total current consumption and timing in forced reset state
Unit
Max(1)
TypConditionsParameterSymbol
μA
400VDD = 5 VSupply current in reset
state(2)
IDD(R)
300VDD = 3.3 V
μs150
Reset pin release to
vector fetch
tRESETBL
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals9.3.2.7
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 30: Peripheral current consumption
UnitTyp.ParameterSymbol
μA
210
TIM1 supply current(1)
IDD(TIM1)
130
TIM2 supply current(1)
IDD(TIM2)
50
TIM4 timer supply current(1)
IDD(TIM4)
120
UART1 supply current(2)
IDD(UART1)
45
SPI supply current(2)
IDD(SPI)
65
I2C supply current(2)
IDD(I2C)
1000
ADC1 supply current when converting(3)
IDD(ADC1)
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) Data based on a differential IDD measurement between reset configuration and timer counter running
at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
(2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset
and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.
Not tested in production.
(3) Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
Current consumption curves9.3.2.8
The following figures show typical current consumption measured with code executing in
RAM.
Figure 11: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
Figure 12: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
DocID018576 Rev 358/100
STM8S003K3 STM8S003F3Electrical characteristics
Figure 13: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
Figure 14: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
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Electrical characteristicsSTM8S003K3 STM8S003F3
Figure 15: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
Figure 16: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
External clock sources and timing characteristics9.3.3
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 31: HSE user external clock characteristics
UnitMaxMinConditionsParameterSymbol
MHz160
User external clock source
frequency
fHSE_ext
V
VDD + 0.3 V0.7 x VDD
OSCIN input pin high level voltageVHSEH
(1)
0.3 x VDD
VSS
OSCIN input pin low level voltageVHSEL
(1)
μA+1-1
VSS < VIN <
VDD
OSCIN input leakage currentILEAK_HSE
DocID018576 Rev 360/100
STM8S003K3 STM8S003F3Electrical characteristics
(1) Data based on characterization results, not tested in production.
Figure 17: HSE external clock source
VHSEH
VHSEL
External clock
source OSCIN
fHSE
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 32: HSE oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz161
External high speed
oscillator frequency
fHSE
kΩ220
Feedback resistorRF
pF20
Recommended load
capacitance(2)
C(1)
mA
6 (startup)
C = 20 pF,
HSE oscillator power
consumption
IDD(HSE)
1.6 (stabilized)(3)
fOSC = 16 MHz
6 (startup)
C = 10 pF,
1.2 (stabilized)(3)
fOSC =16 MHz
mA/V5
Oscillator
transconductance
gm
ms1
VDD is stabilizedStartup timetSU(HSE)
(4)
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) C is approximately equivalent to 2 x crystal Cload.
(2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rmvalue. Refer to crystal manufacturer for more details
(3) Data based on characterization results, not tested in production.
(4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 18: HSE oscillator circuit diagram
OSCOUT
OSCIN
fHSE to core
CL1
CL2
RF
STM8
Resonator Consumption
control
gm
Rm
Cm
LmCO
Resonator
HSE oscillator critical g mequation
gmcrit= (2 × Π × fHSE)2× Rm(2Co + C)2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm>> gmcrit
Internal clock sources and timing characteristics9.3.4
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 33: HSI oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz16
FrequencyfHSI
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STM8S003K3 STM8S003F3Electrical characteristics
UnitMaxTypMinConditionsParameterSymbol
%
1.0(3)
User-trimmed with
CLK_HSITRIMR register for
Accuracy of HSI
oscillator
ACCHSI
given VDD and TA
conditions(1)
5-5
VDD = 5 V,
-40 °C TA 85 °C
Accuracy of HSI
oscillator (factory
calibrated)
μs
1.0(3)
HSI oscillator
wakeup time
tsu(HSI)
including
calibration
μA
250(2)
170
HSI oscillator
power
IDD(HSI)
consumption
(1) Refer to application note.
(2) Data based on characterization results, not tested in production.
(3) Guaranteed by design, not tested in production.
Figure 19: Typical HSI frequency variation vs VDD @ 4 temperatures
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Electrical characteristicsSTM8S003K3 STM8S003F3
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 34: LSI oscillator characteristics
UnitMaxTypParameterSymbol
kHz128
FrequencyfLSI
μs7
LSI oscillator wake-up timetsu(LSI)
μA5
LSI oscillator power consumptionIDD(LSI)
Figure 20: Typical LSI frequency variation vs VDD @ 4 temperatures
Memory characteristics9.3.5
RAM and hardware registers
Table 35: RAM and hardware registers
UnitMinConditionsParameterSymbol
V
VIT-max
(2)
Halt mode (or reset)
Data retention mode
(1)
VRM
(1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
(2) Refer to the Operating conditions section for the value of VIT-max
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STM8S003K3 STM8S003F3Electrical characteristics
Flash program memory and data EEPROM
Table 36: Flash program memory and data EEPROM
UnitMaxTyp
Min
(1)
ConditionsParameterSymbol
V5.52.95
fCPU 16 MHz
Operating voltage (all
modes, execution/
write/erase)
VDD
ms
6.66
Standard programming time
(including erase) for
tprog
byte/word/block (1 byte/
4 bytes/64 bytes)
3.333
Fast programming time for
1 block (64 bytes)
3.333
Erase time for 1 block
(64 bytes)
terase
cycles
100
TA= 85 °C
Erase/write cycles(2)
(program memory)
NRW
100 k
Erase/write cycles(2)
(data memory)
years
20
TRET = 55°C
Data retention (program
memory) after 100
erase/write cycles at TA=
85 °C
tRET
20
Data retention (data
memory) after 10 k
erase/write cycles at TA=
85 °C
1
TRET = 85°C
Data retention (data
memory) after 100 k
erase/write cycles at TA=
85 °C
mA2
Supply current (Flash
programming or erasing
IDD
for 1 to 128 bytes)
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) Data based on characterization results, not tested in production.
(2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
I/O port pin characteristics9.3.6
General characteristics
Subject to general operating conditions for VDD and TAunless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 37: I/O static characteristics
UnitMaxTypMinConditionsParameterSymbol
V
0.3 x
VDD
-0.3 V
VDD = 5 V
Input low level voltage
VIL
VDD +
0.3
0.7 x
VDD
Input high level voltage
VIH
mV700
Hysteresis(1)
Vhys
805530
VDD = 5 V, VIN = VSS
Pull-up resistor
Rpu
ns
20 (2)
Fast I/Os
Load = 50 pF
Rise and fall time
(10 % - 90 %)
tR, tF
125 (2)
Standard and high sink
I/Os
Load = 50 pF
μA
±1 (2)
VSS VIN ≤VDD
Digital input leakage current
Ilkg
nA
±250 (2)
VSS VIN VDD
Analog input leakage current
Ilkg ana
μA
±1 (2)
Injection current ±4 mA
Leakage current in adjacent
I/O
Ilkg(inj)
(1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not
tested in production.
(2)Data based on characterisation results, not tested in production.
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Figure 21: Typical VIL and VIH vs VDD @ 4 temperatures
Figure 22: Typical pull-up resistance vs VDD @ 4 temperatures
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Figure 23: Typical pull-up current vs VDD @ 4 temperatures
Table 38: Output driving current (standard ports)
UnitMaxMinConditionsParameterSymbol
V
2.0
IIO= 10 mA,
VDD = 5 V
Output low level with 8 pins sunk
VOL
1.0(1)
IIO = 4 mA,
VDD = 3.3 V
Output low level with 4 pins sunk
2.8
IIO = 10 mA,
VDD = 5 V
Output high level with 8 pins sourced
VOH
2.1(1)
IIO = 4 mA,
VDD = 3.3 V
Output high level with 4 pins sourced
(1) Data based on characterization results, not tested in production
Table 39: Output driving current (true open drain ports)
UnitMaxConditionsParameterSymbol
V
1 .0
IIO = 10
mA, VDD =
5 V
Output low level with 2 pins sunk
VOL
1.5(1)
IIO = 10
mA, VDD =
3.3 V
Output low level with 2 pins sunk
VOL
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STM8S003K3 STM8S003F3Electrical characteristics
UnitMaxConditionsParameterSymbol
2.0(1)
IIO = 20
mA, VDD =
5 V
Output low level with 2 pins sunk
VOL
(1) Data based on characterization results, not tested in production
Table 40: Output driving current (high sink ports)
UnitMaxMinConditionsParameterSymbol
V0.8
IIO = 10 mA,
VDD = 5 V
Output low level with 8 pins sunk
VOL
V
1.0(1)
IIO = 10 mA,
VDD = 3.3 V
Output low level with 4 pins sunk
VOL
1.5(1)
IIO = 20 mA,
VDD = 5 V
Output low level with 4 pins sunk
4.0
IIO = 10 mA,
VDD = 5 V
Output high level with 8 pins sourced
VOH 2.1(1)
IIO = 10 mA,
VDD = 3.3 V
Output high level with 4 pins sourced
3.3(1)
IIO = 20 mA,
VDD = 5 V
Output high level with 4 pins sourced
(1) Data based on characterization results, not tested in production
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Figure 24: Typ. VOL @ VDD = 5 V (standard ports)
Figure 25: Typ. VOL @ VDD = 3.3 V (standard ports)
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STM8S003K3 STM8S003F3Electrical characteristics
Figure 26: Typ. VOL @ VDD = 5 V (true open drain ports)
Figure 27: Typ. VOL @ VDD = 3.3 V (true open drain ports)
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Figure 28: Typ. VOL @ VDD = 5 V (high sink ports)
Figure 29: Typ. VOL @ VDD = 3.3 V (high sink ports)
DocID018576 Rev 372/100
STM8S003K3 STM8S003F3Electrical characteristics
Figure 30: Typ. VDD - VOH@ VDD = 5 V (standard ports)
Figure 31: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
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Electrical characteristicsSTM8S003K3 STM8S003F3
Figure 32: Typ. VDD - VOH@ VDD = 5 V (high sink ports)
Figure 33: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports)
Reset pin characteristics9.3.7
Subject to general operating conditions for VDD and TAunless otherwise specified.
Table 41: NRST pin characteristics
UnitMaxTypMinConditionsParameterSymbol
V0.3 x VDD
-0.3 V
NRST input low
VIL(NRST)
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STM8S003K3 STM8S003F3Electrical characteristics
UnitMaxTypMinConditionsParameterSymbol
level voltage(1)
VDD + 0.30.7 x VDD
IOL=2 mA
NRST input high
VIH(NRST)
level voltage (1)
0.5
NRST output low
VOL(NRST)
level voltage (1)
805530
NRST pull-up
RPU(NRST)
resistor(2)
ns
75
NRST input filtered
tI FP(NRST)
pulse(3)
500
NRST input not
tIN FP(NRST)
filtered pulse(3)
μs
20
NRST output
pulse (3)
tOP(NRST)
(1) Data based on characterization results, not tested in production.
(2) The RPU pull-up equivalent resistor is based on a resistive transistor
(3) Data guaranteed by design, not tested in production.
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Figure 34: Typical NRST VIL and VIH vs VDD @ 4 temperatures
Figure 35: Typical NRST pull-up resistance vs VDD @ 4 temperatures
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STM8S003K3 STM8S003F3Electrical characteristics
Figure 36: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see
#unique_55/CD662 ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 10 nF.
Figure 37: Recommended reset pin protection
0.1 µF
External
reset
circuit
STM8
Filter
RPU
VDD
Internal reset
NRST
(optional)
SPI serial peripheral interface9.3.8
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
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Table 42: SPI characteristics
UnitMaxMin
Conditions(1)
ParameterSymbol
MHz80
Master modeSPI clock
frequency
fSCK1/
tc(SCK)
MHz7(2)
0
SPI clock frequencyfSCK1/ tc(SCK)
fSCK1/
tc(SCK)
ns
25
Capacitive load: C = 30 pFSPI clock rise and
fall time
tr(SCK)
tf(SCK)
4 x
tMASTER
Slave modeNSS setup timetsu(NSS)
(3)
70Slave modeNSS hold timeth(NSS)
(3)
tSCK/
2 +15
tSCK/
2 - 15
Master modeSCK high and low
time
tw(SCKH)
(3)
tw(SCKL)
(3)
5Master modeData input setup
time
tsu(MI)
(3)
tsu(SI)
(3) 5Slave mode
7Master modeData input hold
time
th(MI)
(3)
th(SI)
(3) 10Slave mode
3 x
tMASTER
Slave modeData output
access time
ta(SO)
(3) (4)
25
Slave modeData output
disable time
tdis(SO)
(3) (5)
65(2)
Slave mode
(after enable edge)
Data output valid
time
tv(SO)
(3)
30
Master mode
(after enable edge)
Data output valid
time
tv(MO)
(3)
27(2)
Slave mode
(after enable edge)
Data output hold
time
th(SO)
(3)
11(2)
Master mode
(after enable edge)
Data output hold
time
th(MO)
(3)
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STM8S003K3 STM8S003F3Electrical characteristics
(1) Parameters are given by selecting 10 MHz I/O output frequency.
(2) Data characterization in progress.
(3) Values based on design simulation and/or characterization results, and not tested in
production.
(4) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(5) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
Figure 38: SPI timing diagram - slave mode and CPHA = 0
ai14134
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI)
th(SI)
Figure 39: SPI timing diagram - slave mode and CPHA = 1
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUTPUT
CPHA=1
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI) th(SI)
NSS input
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristicsSTM8S003K3 STM8S003F3
Figure 40: SPI timing diagram - master mode(1)
ai14136b
SCK intput
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
th(MI)
High
SCK output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
I2C interface characteristics9.3.9
Table 43: I2C characteristics
Unit
Fast mode I2C(1)
Standard mode I2C
ParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
μs
1.34.7SCL clock low timetw(SCLL)
0.64.0SCL clock high timetw(SCLH)
ns
100250SDA setup timetsu(SDA)
900(3)
0(4)
0(3)
SDA data hold timeth(SDA)
3001000SDA and SCL rise time
tr(SDA)
tr(SCL)
300300SDA and SCL fall time
tf(SDA)
tf(SCL)
μs
0.64.0START condition hold timeth(STA)
0.64.7Repeated START condition setup timetsu(STA)
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STM8S003K3 STM8S003F3Electrical characteristics
Unit
Fast mode I2C(1)
Standard mode I2C
ParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
0.64.0STOP condition setup timetsu(STO)
μs1.34.7
STOP to START condition time
(bus free)
tw(STO:STA)
pF400400Capacitive load for each bus lineCb
(1) fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
(2) Data based on standard I2C protocol requirement, not tested in production
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 41: Typical application with I2C bus and timing diagram
tf(SDA) tr(SDA) tsu(SDA) th(SDA)
tf(SCL)
tr(SCL)
tw(SCLL)
tw(SCLH)
th(STA) tsu(STO)
tsu(STA) tw(STO:STA)
SDA
SCL
4.7kSDA
SCL
100
100
4.7k
I2C bus
START START
STOP
REPEATED
START
STM8S
VDD VDD
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10-bit ADC characteristics9.3.10
Subject to general operating conditions for VDD, fMASTER, and TAunless otherwise specified.
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Table 44: ADC characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz
41VDD =2.95 to 5.5 VADC clock frequencyfADC
61VDD =4.5 to 5.5 V
VVDD
VSS
Conversion voltage range(1)
VAIN
pF3
Internal sample and hold
capacitor
CADC
μs
0.75fADC = 4 MHzMinimum sampling timetS
(1)
0.5fADC = 6 MHz
μs7Wake-up time from standbytSTAB
μs3.5fADC = 4 MHzMinimum total conversion time
(including sampling time,
10-bit resolution)
tCONV
μs2.33fADC = 6 MHz
1/fADC
14
(1) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tSdepend on programming.
Table 45: ADC accuracy with RAIN < 10 , VDD= 5 V
UnitMax(1)
TypConditionsParameterSymbol
LSB
3.51.6fADC = 2 MHzTotal unadjusted error(2)
|ET|
42.2fADC = 4 MHz
4.52.4fADC = 6 MHz
2.51.1fADC = 2 MHzOffset error(2)
|EO|
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STM8S003K3 STM8S003F3Electrical characteristics
UnitMax(1)
TypConditionsParameterSymbol
31.5fADC = 4 MHz
31.8fADC = 6 MHz
31.5fADC = 2 MHzGain error(2)
|EG|
32.1fADC = 4 MHz
42.2fADC = 6 MHz
1.50.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.50.7fADC = 4 MHz
1.50.7fADC = 6 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
20.8fADC = 4 MHz
20.8fADC = 6 MHz
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 46: ADC accuracy with RAIN < 10 RAIN, VDD = 3.3 V
UnitMax(1)
TypConditionsParameterSymbol
LSB
3.51.6fADC = 2 MHzTotal unadjusted error(2)
|ET|
41.9fADC = 4 MHz
2.51fADC = 2 MHzOffset error(2)
|EO|
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Electrical characteristicsSTM8S003K3 STM8S003F3
UnitMax(1)
TypConditionsParameterSymbol
2.51.5fADC = 4 MHz
31.3fADC = 2 MHzGain error(2)
|EG|
32fADC = 4 MHz
10.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.50.7fADC = 4 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
20.8fADC = 4 MHz
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in I/O port
pin characteristics does not affect the ADC accuracy.
Figure 42: ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
DocID018576 Rev 384/100
STM8S003K3 STM8S003F3Electrical characteristics
3. End point correlation line
ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO= Offset error: deviation between the first actual transition and the first ideal one.
EG= Gain error: deviation between the last ideal transition and the last actual one.
ED= Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL= Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 43: Typical application with ADC
STM8
10-bit A/D
conversion
RAIN
CAIN
VAIN AINx
VDD
VT
0.6 V
VT
0.6 V IL
± 1 µA CADC
EMC characteristics9.3.11
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)9.3.11.1
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
Designing hardened software to avoid noise problems9.3.11.2
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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Electrical characteristicsSTM8S003K3 STM8S003F3
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 47: EMS data
Level/
class
ConditionsParameterSymbol
2/B (1)
VDD = 3.3 V, TA= 25 °C, fMASTER = 16 MHz
(HSI clock), conforming to IEC 61000-4-2
Voltage limits to be
applied on any I/O pin to
induce a functional
disturbance
VFESD
4/A (1)
VDD= 3.3 V, TA= 25 °C ,fMASTER = 16 MHz
(HSI clock),conforming to IEC 61000-4-4
Fast transient voltage
burst limits to be applied
through 100 pF on VDD
VEFTB
and VSS pins to induce a
functional disturbance
(1)Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)9.3.11.3
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This emission test is in line with the norm SAE
IEC 61967-2 which specifies the board and the loading of each pin.
Table 48: EMI data
Unit
Conditions
ParameterSymbol Max fHSE/fCPU
(1)
Monitored
frequency band
General
conditions 16 MHz/
16 MHz
16 MHz/
8 MHz
dBμV
55
0.1 MHz to
VDD = 5 V
TA= 25 °C
Peak level
SEMI 30 MHz
LQFP32
package 54
30 MHz to
DocID018576 Rev 386/100
STM8S003K3 STM8S003F3Electrical characteristics
Unit
Conditions
ParameterSymbol Max fHSE/fCPU
(1)
Monitored
frequency band
General
conditions 16 MHz/
16 MHz
16 MHz/
8 MHz
Conforming to
SAE IEC
61967-2
130 MHz
55
130 MHz to
1 GHz
2.52.5
SAE EMI level
SAE EMI
level
(1) Data based on characterisation results, not tested in production.
Absolute maximum ratings (electrical sensitivity)9.3.11.4
Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)9.3.11.5
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:
Human body model. This test conforms to the JESD22-A114A/A115A standard. For more
details, refer to the application note AN1181.
Table 49: ESD absolute maximum ratings
UnitMaximum
value(1)
ClassConditionsRatingsSymbol
V
4000A
TA= 25°C, conforming toElectrostatic discharge
VESD(HBM)
JESD22-A114voltage
(Human body model)
1000IV
TALQFP32 package =Electrostatic discharge
VESD(CDM)
25°C, conforming tovoltage
SD22-C101(Charge device model)
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Electrical characteristicsSTM8S003K3 STM8S003F3
(1) Data based on characterization results, not tested in production
Static latch-up9.3.11.6
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
A current injection (applied to each input, output and configurable I/O pin) are performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50: Electrical sensitivities
Class(1)
ConditionsParameterSymbol
ATA= 25 °C
Static latch-up classLU
ATA= 85 °C
(1) Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
DocID018576 Rev 388/100
STM8S003K3 STM8S003F3Electrical characteristics
Package information10
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK®
is an ST trademark.
32-pin LQFP package mechanical data10.1
Figure 44: 32-pin low profile quad flat package (7 x 7)
5V_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
16
17
24
25
b
32
1
Pin 1
identification 8
9
Table 51: 32-pin low profile quad flat package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01770.01460.01180.4500.3700.300b
0.00790.00350.2000.090c
0.36220.35430.34659.2009.0008.800D
0.28350.27560.26777.2007.0006.800D1
89/100DocID018576 Rev 3
Package informationSTM8S003K3 STM8S003F3
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.22055.600D3
0.36220.35430.34659.2009.0008.800E
0.28350.27560.26777.2007.0006.800E1
0.22055.600E3
0.03150.800e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
7.0°3.5°0.0°7.0°3.5°0.0°k
0.00390.100ccc
(1) Values in inches are converted from mm and rounded to 4 decimal digits
20-pin TSSOP package mechanical data10.2
Figure 45: 20-pin, 4.40 mm body, 0.65 mm pitch
YA_ME
1
20
CP
c
L
EE1
D
A2
A
k
eb
10
11
A1
L1
aaa
DocID018576 Rev 390/100
STM8S003K3 STM8S003F3Package information
Table 52: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.04721.200A
0.00590.00200.1500.050A1
0.04130.03940.03151.0501.0000.800A2
0.01180.00750.3000.190b
0.00790.00350.2000.090c
0.25980.25590.25206.6006.5006.400D
0.25980.25200.24416.6006.4006.200E
0.17720.17320.16934.5004.4004.300E1
0.02560.650e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
8.0°0.0°8.0°0.0°k
0.00390.100aaa
(1) Values in inches are converted from mm and rounded to 4 decimal digits
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Package informationSTM8S003K3 STM8S003F3
20-lead UFQFPN package mechanical data10.3
Figure 46: 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3)
103_A0A5_ME
11
15
1620
1
5
D
e
be
E
A1 A
ddd
L2
10
L1
A3
L3
L4
D
E
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin 1
1. Drawing is not to scale.
Table 53: 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.11813.000D
0.11813.000E
0.02360.02170.01970.6000.5500.500A
0.00200.00080.00000.0500.0200.000A1
0.00600.152A3
0.01970.500e
0.02360.02170.01970.6000.5500.500L1
0.01570.01380.01180.4000.3500.300L2
0.00590.150L3
0.00790.200L4
0.01180.00980.00710.3000.2500.180b
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STM8S003K3 STM8S003F3Package information
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.00200.050ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
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Package informationSTM8S003K3 STM8S003F3
Thermal characteristics11
The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
TAmax is the maximum ambient temperature in °C
ΘJA is the package junction-to-ambient thermal resistance in °C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD andVDD, expressed in Watts. This is the maximum chip internal
power.
PI/Omax represents the maximum power dissipation on output pins
Where: PI/Omax (VOL*IOL) + Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and
VOH/IOH of the I/Os at low and high level in the application.
Table 54: Thermal characteristics
UnitValueParameter(1)
Symbol
°C/W84Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
ΘJA
90
Thermal resistance junction-ambientΘJA
UFQFPN20 - 3 x 3 mm
60Thermal resistance junction-ambient
LQFP32 - 7 x 7 mm
ΘJA
(1)Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
Reference document11.1
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range11.2
When ordering the microcontroller, the temperature range is specified in the order code.
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STM8S003K3 STM8S003F3Thermal characteristics
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
IDDmax = 8 mA, VDD = 5 V
Maximum 20 I/Os used at the same time in output at low level with
IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V = 400 mW
Amax
PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance ΘJA:
TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C
This is within the range of the suffix 6 version parts (-40 < TJ< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
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Ordering information12
Figure 47: STM8S003x value line ordering information scheme
Pin count
K = 32 pins
F = 20 pins
Example:
Sub-family type
00x = Value line
003 sub-family
Family type
S = Standard
Temperature range
6 = -40 °C to 85 °C
Program memory size
3 = 8 Kbytes
Packing
No character = Tray or tube
TR = Tape and reel
Package pitch
Blank = 0.5 or 0.65 mm(1)
C = 0.8 mm(2)
STM8 S 003 K 3 T 6 TR
Product class
STM8 microcontroller
Package type 1
P = TSSOP
T = LQFP
U = UFQFPN
1. TSSOP and UFQFPN package.
2. LQFP package.
For a list of available options (e.g. package, packing) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales
Office nearest to you.
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STM8 development tools13
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
Emulation and in-circuit debugging tools13.1
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
Occurrence and time profiling and code coverage (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
Software tools13.2
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
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STM8 toolset13.2.1
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop Full-featured integrated development environment from ST, featuring
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
C and assembly toolchains13.2.2
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
Raisonance C compiler for STM8 Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
STM8 assembler linker Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
Programming tools13.3
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history14
Table 55: Document revision history
ChangesRevisionDate
Initial revision.112-Jul-2011
Added NRW and tRET for data EEPROM in Table 36:
Flash program memory and data EEPROM.
209-Jan-2012
Updated RPU in Table 41: NRST pin characteristics and
Table 37: I/O static characteristics.
Updated notes related to VCAP in Table 18: General
operating conditions.
Updated temperature condition for factory calibrated
ACCHSI in Table 33: HSI oscillator characteristics.
Changed SCK input to SCK output in Figure 40: SPI
timing diagram - master mode(1)
312-Jun-2012
Modified Figure 46: 20-lead ultra thin fine pitch quad flat
no-lead package outline (3x3) to add package top view.
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