PalmDSPCore - Atmel Corporation

Features

•16-bit Fixed-point Advanced Digital Signal Processing (DSP) Core

•High Performance:

– 210 MHz (typical) on 0.18-micron CMOS, 1.8V

– 3800 MOPS (3.8 GOPS) - Peak Performance on 0.18-micron CMOS

•Low Current Consumption:

–Active Mode: 0.9 mA/MHz on 0.18-micron CMOS, 1.8V

–Slow Mode: Linearly Reduces Clock Speed by a User-defined Factor

–Stop Mode: less than 200 nA

•Single Clock Edge Triggered Design

•Soft Core Implemented in VHDL (Process- and Library-independent)

•High Level of Modularity:

–Expandable Program RAM and/or ROM

•Memory Organization:

–Advanced Harvard Architecture: Parallel Access to Program and Data Memories

–Program Memory: Linear Space up to 1M Words, Paging Space up to 16M Words

–Three Independent Data Memory Spaces: X-space, Y-space and Z-space for

Peripherals

•Five Parallel Execution Units for Maximum Code and Data Throughput

•Six Data Types Supported, including Single-word and Double-word Size

•Supports SIMD and MIMD Modes

•Wait States are Supported to Link with Slow External Devices

•Fully Scan Testable

•Advanced Windows-based Development Tools: Macro Assembler, Linker, C and C++

Optimizing Compiler, Debugger (emulator, simulator)

•Development Board for Real-time Software Development

•JTAG Serial Interface and On-Chip Emulation Module (OCEM®) for On-chip Debug

Description

Atmel’s embedded 16-bit PalmDSPCore® is based on a dual-MAC and parallel-func-

tioning architecture. The PalmDSPCore is characterized by high performance and

high flexibility, with rapid code and data throughput for complex digital signal process-

ing implementations.

The PalmDSPCore is designed to achieve the best possible performance with the low-

est possible power consumption. It is especially suitable for third-generation mobile

telecommunications, wireless communications, multimedia and hi-fi audio implemen-

tations, advanced consumer electronics as well as general-purpose low-power, high-

speed signal processing applications.

The PalmDSPCore is available as a DSP core in Atmel’s standard cell library, to be uti-

lized as an engine for DSP-based ASICs. It is specified with several levels of

modularity in RAM, ROM and I/O blocks, allowing efficient DSP-based ASIC

development.

The PalmDSPCore consists of five main execution units operating in parallel: the

Computation/Bit Manipulation Unit (CBU), the Data Address Arithmetic Unit (DAAU),

the Program Control Unit (PCU), the Operand Fetch Unit (OFU) and the Instruction

Decode Unit (IDU). The core also contains ROM and RAM addressing units, and Pro-

gram Control Logic (PCL). All other peripheral blocks, which are application-specific,

are defined as a part of the user-specific logic, implemented around the DSP core on

the same silicon die.

The PalmDSPCore has an enhanced set of DSP and general microprocessor func-

tions to meet the application requirements. The PalmDSPCore programming model

and instruction set are aimed at straightforward generation of efficient and compact

code.

Embedded

Digital Signal

Processing

Core

PalmDSPCore®

Rev. 1729A–03/01

2PalmDSPCore

1729A–03/01

Figure 1. PalmDSPCore Symbol

GIEWRP<15:0>

GIOWRP<15:0>

PPAEP<18:0>

PPAOP<18:0>

PPRPAGEP<3:0>

PPREP

PPROP

PPWEP

PPWOP

PPMOVPIP

PTRAPAP

PESFTP

PUSFTP

GIERDP<15:0>

GIORDP<15:0>

Program Address,

Data and Control

DXAEP<14:0>

DXAOP<14:0>

DYAEP<14:0>

DYAOP<14:0>

DZAEP<14:0>

DZAOP<14:0>

DZAEREFLECTP<1:0>

DZAOREFLECTP<1:0>

SXEWRP<15:0>

SXOWRP<15:0>

SYEWRP<15:0>

SYOWRP<15:0>

SZEWRP<15:0>

SZOWRP<15:0>

SE0WDBP<15:0>

SE1WDBP<15:0>

DXERDP

DXORDP

DYERDP

DYORDP

DZERDP

DZORDP

DXEWRP

DXOWRP

DYEWRP

DYOWRP

DZEWRP

DZOWRP

DXNOMEMP

DYNOMEMP

DZNOMEMP

DZLSPB

DZCONSP

GXERDP<15:0>

GXORDP<15:0>

GYERDP<15:0>

GYORDP<15:0>

GZERDP<15:0>

GZORDP<15:0>

OXZADDP<5:0>

OYZADDP<5:0>

Data Address,

Data and Control

DEPMIENP

DEPMJENP

IEPMIP<1:0>

IEPMJP<1:0>

IE0SRCP<3:0>

IE1SRCP<3:0>

IE0DSTP<3:0>

IE1DSTP<3:0>

IE0RDP

IE1RDP

IE0WRP

IE1WRP

IEXTRDWRP

ICPCMDP<3:0>

OEPMADDP<15:0>

BNONOEP

User-defined Register/

Co-processor Support

PIRPCP<19:0>PDUMMYIRN

SDVMP

DXOWBWP

DXEWBWP

DYOWBWP

DYEWBWP

BPABPREQP

OEMULP

BTRAPREQP

Emulation Support

CUO0P

CUO1P

PIACKN

IBUSLOCKP

ISTATUSP<3:0>

LRSTP

NNMIP

NVINTP

NVICNTEXP

NVECTORP<19:0>

NINT0P

NINT1P

NINT2P

NBOOTP

TESTMODEP

OUI0P

OUI1P

Clock

LCLKP

Processor Control Signals

PalmDSPCore

1729A–03/01

Signal Description

Table 1. Pin Configuration List

Pin Name Size Type Description

Program Address, Data and Control

GIERDP 16 I Program data even read bus

GIORDP 16 I Program data odd read bus

GIEWRP 16 O Program data even write bus

GIOWRP 16 O Program data odd write bus

PPAEP 19 O Program address even bus

PPAOP 19 O Program address odd bus

PPRPAGEP 4 O Program page bus (page = 1M words)

PPREP 1 O Program even read enable (over GIERDP)

PPROP 1 O Program read odd enable (over GIORDP)

PPWEP 1 O Program write even enable (over GIEWRP)

PPWOP 1 O Program write odd enable (over GIOWRP)

PMOVPIP 1 O Program protection support

PTRAPAP 1 O BI/TRAPE service routine indication

PESFTP 1 O Software TRAPE service routine indication

PUSFTP 1 O Software user TRAP service routine indication

Data Address, Data and Conrtrol

GXERDP 16 I X space even read data bus

GXORDP 16 I X space odd read data bus

GYERDP 16 I Y space even read data bus

GYORDP 16 I Y space odd read data bus

GZERDP 16 I Z space even read data bus

GZORDP 16 I Z space odd read data bus

OXZADDP 6 I X-Z border address

OYZADDP 6 I Y-Z border address

DXAEP 15 O X even data address bus

DXAOP 15 O X odd data address bus

DYAEP 15 O Y even data address bus

DYAOP 15 O Y odd data address bus

DZAEP 15 O Z even data address bus

DZAOP 15 O Z odd data address bus

DZAEREFLECTP 2 O Z even address reflection bus

DZAOREFLECTP 2 O Z odd address reflection bus

SXEWRP 16 O X space even write data bus

4PalmDSPCore

1729A–03/01

SXOWRP 16 O X space odd write data bus

SYEWRP 16 O Y space even write data bus

SYOWRP 16 O Y space odd write data bus

SZEWRP 16 O Z space even write data bus

SZOWRP 16 O Z space odd write data bus

DXERDP 1 O X even data read enable (over GXERDP)

DXORDP 1 O X odd data read enable (over GXORDP)

DYERDP 1 O Y even data read enable (over GYERDP)

DYORDP 1 O Y odd data read enable (over GYORDP)

DZERDP 1 O Z even data read enable (over GZERDP)

DZORDP 1 O Z odd data read enable (over GZORDP)

DXEWRP 1 O X even data write enable (over SXEWRP)

DXOWRP 1 O X odd data write enable (over SXOWRP)

DYEWRP 1 O Y even data write enable (over SYEWRP)

DYOWRP 1 O Y odd data write enable (over SYOWRP)

DZEWRP 1 O Z even data write enable (over SZEWRP)

DZOWRP 1 O Z odd data write enable (over SZOWRP)

DXNOMEMP 1 O No X space transaction in the next cycle

DYNOMEMP 1 O No Y space transaction in the next cycle

DZNOMEMP 1 O No Z space transaction in the next cycle

DZLSBP 1 O 32-bit Z space registers support

DZCONSP 1 O Consecutive addr generation for Z space indication

BNONOEP 1 I Non odd/even Z space memory structure

User-defined Register/Co-processor Support

OEPMADDP 16 I EPM address bus

DEPMIENP 1 O EPM for R3 is enabled

DEPMJENP 1 O EPM for R7 is enabled

IEPMIP 2 O External post modification type (bank I)

IEPMJP 2 O External post modification type (bank J)

IE0SRCP 4 O External register source bus 0

IE1SRCP 4 O External register source bus 1

IE0DSTP 4 O External register destination bus 0

IE1DSTP 4 O External register destination bus 1

IE0RDP 1 O External read control (code on IE0SRCP)

IE1RDP 1 O External register read control (code on IE1SRCP)

IE0WRP 1 O External register write control (code on IE0DSTP)

Table 1. Pin Configuration List (Continued)

Pin Name Size Type Description

PalmDSPCore

1729A–03/01

IE1WRP 1 O External register write control (code on IE1DSTP)

IEXTRDWRP 1 O OR of the 4 signals above

ICPCMDP 4 O Co-processor command (CPRD/CPWR/CPEX)

SE0WDBP 16 O External 0 write data bus

SE1WDBP 16 O External 1 write data bus

Emulation Support

PIRPCP 20 O IR PC (address of instruction in PID stage)

PDUMMYIRN 1 I Indication for a dummy PC on PIRPCP

BPABPREQP 1 I Request for a program address breakpoint

SDVMP 1 O Data value match

OEMULP 1 I Enable emulation mode

BTRAPREQP 1 I Trap request (break point interrupt)

DXOWBWP 1 O Write to X-odd write buffer indication

DXEWBWP 1 O Write to X-even write buffer indication

DYOWBWP 1 O Write to Y-odd write buffer indication

DYEWBWP 1 O Write to Y-even write buffer indication

Processor Control Signals

LRSTP 1 I Synchronous reset

NNMIP 1 I Non-maskable interrupt request

NVINTP 1 I Vectored interrupt request

NVICNTEXP 1 I Vectored interrupt context switch enable

NVECTORP 20 I Vectored interrupt routine address

NINT0P 1 I Interrupt 0 request

NINT1P 1 I Interrupt 1 request

NINT2P 1 I Interrupt 2 request

NBOOTP 1 I Boot request

CUO0P 1 O User output 0 pin (bit 8 of MOD0 register)

CUO1P 1 O User output 1 pin (bit 9 of MOD0 register)

PIACKN 1 O Interrupt acknowledge

IBUSLOCKP 1 O Bus lock (multi-processor support)

ISTATUSP 4 O ISTATUSP indication from IDU

TESTMODEP 1 I Test mode select

OUI0P 1 I User input #0

OUI1P 1 I User input #1

Clock

LCLKP 1 I Main clock

Table 1. Pin Configuration List (Continued)

Pin Name Size Type Description

6PalmDSPCore

1729A–03/01

Functional Overview As shown in Figure 2, the PalmDSPCore consists of a number of functional units and

memory blocks connected by independent, parallel address and data buses.

Figure 2. PalmDSPCore Block Diagram

Data Address Arithmetic

Unit

The Data Address Arithmetic Unit (DAAU) performs all address storage and effective

address calculations necessary to address data operands in data and program memo-

ries. It includes two built-in Addition/Subtraction Units (ASUs) and has two parallel

address lines to each of the three data memory spaces (X, Y and Z for peripherals). It

also supports the software stack pointer. This unit operates in parallel with other core

resources to minimize address generation overhead.

Six addressing modes are available: direct, indirect, index, circular buffering, immediate,

and bit reversal.

Operand Fetch Unit The Operand Fetch Unit (OFU) can read or write, in parallel, two words to or from each

of the data memory spaces. It can transfer four words in parallel to the CBU. This mini-

mizes the potential bottleneck due to relatively slow memory transfers.

Program Control Unit The Program Control Unit (PCU) fetches instructions from the separate program mem-

ory via the Instruction Fetch Queue (IFQ) and passes them to the autonomous

instruction decode unit (IDU).

The PCU enables parallel processing via SIMD instructions.

Zero overhead looping is implemented, with infinite nesting, including both single-cycle

and block repeat.

Eight interrupts are available: reset, NMI, vector, breakpoint, TRAP (software) and three

maskable interrupts.

Y-space

X-space Z-space

(Peripherals)

Data Memory Space

Operand

Fetch Unit

Data Address

Arithmetic Unit

Co-Processors

User

Defined

Registers Status/Mode

Registers

Computation and Bit

Manipulation Unit

Program

Control Unit

Instruction

Fetch Queue

Address Data

Instruction

Decode

Unit

Program Memory

Reset/Interrupts

Data Address

PalmDSPCore

1729A–03/01

Instruction Decode Unit The instruction decode unit (IDU) decodes the instructions provided by the program

control unit (PCU).

Computation/Bit

Manipulation Unit

The Computation and Bit Manipulation Unit (CBU) (Figure 3) contains seven arithmetic

units operating in parallel. These comprise two 16 x 16-bit parallel 2s complement multi-

pliers, supporting single and double precision multiplication, a three-input, 40-bit

Arithmetical and Logic Unit (ALU), a three-input 40-bit Addition/Subtraction Unit (ASU),

a Barrel Shifter, Exponentiation Unit and an Insert/Extract Unit. These are linked to four

symmetrical 40-bit accumulators considered as a single register file. The PalmDSPCore

can perform a single-cycle dual multiply-accumulate (MAC) instruction, and supports a

single-cycle division step.

The Arithmetic and Logic Unit (ALU) performs all arithmetic and logical operations on

data operands. It is a three-input, 40-bit, single-cycle, non-pipelined unit. A maximum or

minimum operation is available.

Figure 3. PalmDSPCore Computation and Bit Manipulation Unit Block Diagram

Computation and Bit Manipulation Unit

Exponentiation

Unit

Barrel

Shifter Multiplier 0 Multiplier 1

Insert/

Extract

Bit Field

Operator

3-input

Arithmetic

and Logic Unit

3-input

Addition/

Subtraction Unit

Accumulator Register File Saturation

Unit

8PalmDSPCore

1729A–03/01

On-chip Emulation The PalmDSPCore supports on-chip emulation, debugging and testing via a standard

JTAG port or using the On-chip Emulation Module (OCEM).

Development Tools Efficient development tools are a critical element in System-on-Chip (SoC) ASIC design

as they affect the design cycle and the time to market. The PalmDSPCore is supplied

with a comprehensive set of hardware and software development tools that enable the

development and debugging of an application-specific Palm-based integrated circuit

(ASIC). They are composed of:

Software Development

Tools

Advanced Windows, Graphical User Interface (GUI) and Command Line Interpreter

(CLI) based development tools (for SUN WorkStation and PC) include:

•Macro assembler

•Optimizing C, C++ compiler

•Linker

•Loader

•Debugger consisting of:

–integrated simulator

–emulator and simulator interface

–extendable simulator (ASSYST™)

–integrated TCL interpreter

Hardware Development

Tools

The PalmDSPCore is accompanied by development board that features:

•a PalmDSPCore Development Chip Module

•External Data/Program Memories:

–32K x 16 bits of X-data RAM and 32K x 16 bits of Y-data RAM

–64K x 16 bits of program RAM

•Extensions to internal buses

•Peripheral glue logic

•Interfaces for off-chip memories (both fast and slow devices are supported)

•User-assigned area

•Power supply

The PalmDSPCore Development Chip Module contains:

•Internal Data/Program Memories

•Bus and Emulation Interfaces (JTAG, OCEM)

•Interrupt and DMA Controller

•General-purpose I/O (GPIO) Interface.

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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

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by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

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Printed on recycled paper.

1729A–03/01/0M

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

OakDSPCore, TeakDSPCore, PalmDSPCore and OCEM are registered trademarks of DSP Group Inc.

Other terms and product names in this document may be trademarks of others.