MOTOROLA SEMICONDUCTOR TECHNICAL DATA Analog Multiplexers/ Demultiplexers High-Performance SiliconGate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC 4053 ulilize sili- con-gate CMOS technology io achieve fast propagation delays, low ON resistances, and low OFF Jeakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from Voc to VEE). The HC4051, HC4052 and HC4053 are identical in pinout to the metalgate MC14051B, MC14052B and MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Ouiput/Input. When the Enable pin is HIGH, all analog switches are turned off. The ChannelSelect and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs, These devices have been designed so that the ON resistance: (Ron} is more linear over input voltage than Ron of metal-gate CMOS analog switches. For multiplexers/demultiplexers with channel-select latches, see HC4351, HC4352 and HC4353. * Fast Switching and Propagation Speeds e Low Crossialk Between Switches e Diode Protection on All Inputs/Outputs Analog Power Supply Range (VGC VEE) = 2.0 to 12.0 V . Digital (Control) Power Supply Range (Voc GND) = 2.0 t0 6.0 V Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts . Low Noise = e In Compliance With the Requirements of JEDEC Standard No. 7A e Chip Complexity: HC4051 184 FETs or 46 Equivalent Gates HC4052 168 FETs or 42 Equivalent Gates HC4053 156 FETs or 39 Equivalent Gates MC54/74HC4051 MC74HC4052 MC54/74HC4053 J SUFFIX CERAMIC PACKAGE CASE 620-10 1 1 N SUFFIX isk PLASTIC PACKAGE 4 CASE 648-08 ~ LE D SUFFIX SOIC PACKAGE CASE 751B-05 DW SUFFIX SOIC PACKAGE CASE 751G-02 DT SUFFIX TSSOP PACKAGE CASE 948F01 ORDERING INFORMATION 3 MC54HCXXXXJ Ceramic MC74HCXXXXN Plastic MC74HCXXXXD SOIC MC74HCXXXXDW = SOIC Wide MC74HCOXXXXDT TSSOP FUNCTION TABLE MC54/74HC4051 LOGIC DIAGRAM Control Inputs MC54/74HC4051 Select - Single-Pole, 8-Position Plus Common Off Enable | GC B A | ONChannels es _ L Lo oLoL 0 0a oef L LoL oH x1 xj lees L L HOL X2 pga L L oH oH x3 ANALOG 12 L H L L x4 INPUTS) | X8-e-m| _ MULTIPLEXERY 3. COMMON L Ho oL H x5 OUTPUTS | yqeem| DEMULTIPLEXER [* > * ouTPUT/ ~ L H H OL X6 a INPUT L H H H x7 2 H x xX xX NONE Xx6s} - | x7 ne Pinout: MCSA7aHica0st (Top View) | X = Don't Care cuanner [ * r voc * SELECT | 8~- fel [el fal fel [el [rl [ol Ce] INPUTS | _ ENABLE PIN 16= Voc PIN 7 = VEE ) PINS = GND lv] Le] Lat cel lst Led Lz] be ; x4 x6 X Xx? XS Enable Vez GND 10/9 s (M) MOTOROLA Motorola, Inc. 1995 . . 3-615. REV7 < - .MC54/74HC4051 MC74HC4052 MC54/74HC4053 LOGIC DIAGRAM MC74HC4052 DoublePole, 4-Position Plus Common Off x0-ae| xt | xswitch baw! y X2 aap yg ANALOG | SFT | COMMON INPUTS/OUTPUTS 1 OUTPUTS/INPUTS oo 3 Yin" soyswitcH = V2 atdot LY3 em CHANNEL-ELECT [ A-> . INPUTS | gB_____] PIN 16 = Voc 5 PIN 8 = GND ENABLE: LOGIC DIAGRAM MC54/74HC4053 Triple Single-Pole, DoublePosition Plus Common Off Xow] 14 x1 13 X SWITCH YO 15 |. | COMMON INPUTSOUTPUTS | Yicteem] 9 YSWITCH YT Oreitsinpurs Z0Stbe 4 74-3 ZSWITCH = kee 7 A it J CHANNEL-SELECT | p10 PIN 16=Vog INPUTS PIN7 = Veg PIN 8 = GND ENABLE NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch FUNCTION TABLE MC74HC4052 Contro! Inputs Select Enable B A ON Channels _ L L L YO XO L L H Y1 x1 L H L Y2 x2 L H H Y3 X38 H x x NONE X=DontCare _ Pinout: MC74HC4052 (Top View) Veo X2 Xt X x3 A B [re] _fi5] [ia] [is] fre] fr] fro] fe] Lt] Le] [3] [4 YO Ye Y 3 61 17] [3 Enable Veg GND FUNCTION TABLE MC54/74HC4053 Control Inputs Select Enable cl)hUBUA ON Channels L L L L ZO Yo x0 L L L oH ZO Yo Xi L L HOL ZO Yi XO L L HH Zo 1 x1 L H L L Z1 Yo Xo L H L oH Zi Yo xt L H H L Zi Y1 XO L H H H Z1 Y4 x1 H X xX xX NONE X= Don't Care - - Pinout: MC54/74HC4053 (Top View) Veo Y xX. Xt {16) [+5] [v4] [ra] fe] fr] fre] To] A B c 9 ) 11] Le] [a] [4 Yt YO 21 Z Ls] 6} |7] Le} Enable Ver GN MOTOROLA ~ 7 3-616 High-Speed CMOS Logic Data DL129 Rev6 _ ..MC54/74HC4051 MC74HC4052 MC54/74HC4053 MAXIMUM RATINGS* Symbol! Parameter Value Unit This device contains protection Vcc | Positive DC Supply Voltage (Referencedto GND) | 0.5 to + 7.0 Vv circuitry to guard against damage (Referenced to VEE) -~0.5t0+14.0 due to high static voltages or electric tlelds. However, precautions must Vee | Negative DC Supply Voltage (Referenced to GND) -7.0 to + 5.0 Vv be taken to avoid applications of any ~ voltage higher than maximum rated Vis Analog Input Voltage e. 8 < v voltages to this high-impedance cir- : . cuit. For proper operation, Vjp, and Vin Digital Input Voltage (Referenced to GND) -O5toVoo+05] V Vout should be constrained to the range GND s (Vin or Vout) S Voc. | DC Current, Into or Out of Any Pin +25 mA Unused inputs must always be Pp Power Dissipation in Still Air, Plastic or Ceramic DIP} 750 mw tied to an appropriate logic voltage SOIC Packaget 500 level {e.g., either GND or Vcc). TSSOP Packaget 450 Unused outputs must be left open. Tsig | Storage Temperature Range oe ~65 to+ 150 C TL Lead Temprature, 1 mm from Case for 10 Seconds C Plastic DIP, SOIC or TSSOP Package 260 Ceramic DIP 300 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. . {Derating Plastic DIP: 10 mW/C from 65 to 125C _ a. Ceramic DIP: ~ 10 mW/C from 100 to 125C . cee ae SOIC Package: - 7 mW/C from 65 to 125C = oe TSSOP Package: 6.1 mW/C from 65 to 125C se For high frequency or heavy load considerations, see Chapter2. ~ = _ RECOMMENDED OPERATING CONDITIONS Symboi Parameter Min | Max | Unit _ . Voc Positive DO Supply Voltage (Referenced to GND) | 2.0 6.0 Vv (Referenced to Ver) | 2.0 12.0 VEE Negative DC Supply Voltage, Output (Referenced to -6.0 | GND Vv GND) Vis Analog Input Vollage ~~ 7 | Vee [ Voc. Vin Digital Input Voltage (Referenced to GND) GND [| Voc Vio" Static_or Dynamic Voltage Across Switch. 1.2 Vv TA Operating Temperature Range, All Package Types -55 $4125] C ty, tf Input Rise/Fall Time i Voc=2.0V)] 0 1000 | ns (Channel Select or Enable Inputs) . Vog=45V 0 500 Voc =60Vj 0 400 For voltage drops across switch greater than 1.2V (switch on), excessive Vcc current may be drawn; i.e., the current out of the switch may contain both Vcc and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. High-Speed CMOS Logic Data ~ a - 3-617- MOTOROLA DLi29 Rev - a ee - - -MC54/74HC4051 MC74HC4052 MC54/74HC4053 DC CHARACTERISTICS Digital Section (Voltages Referenced to GND) Veg = GND, Except Where Noted Voc Guaranteed Limit Symbol Parameter Condition Vv 55 to 25C | <85C | <125C | Unit VIH Minimum High-Level Input Voltage, | Ron = Per Spec 2.0 1.50 1.50 1.50 Vv Channe!-Select or Enable Inputs 4.5 3.15 | 3.15 3.15 6.0 4.20 4.20 4,20 Vit Maximum Low-Level Input Voltage, | Ron = Per Spec 2.0 0.3 0.3 0.3 v Channe!l-Select or Enable inputs 4.5 0.9 0.9 0.9 6.07 1.2 1.2 1.2 lin Maximum Input Leakage Current, Vin = Voc or GND, 6.0 0.1 +1.0 +1.0 LA Channe|Select or Enable Inputs VEE =-6.0V loc Maximum Quiescent Supply Channel Select, Enable and HA Current (per Package) Vis=VecorGND; Vee=GND] 6.0 2 20 40 VI9 =0V VeEgE=-6.0; 6.0 8 80 160 NOTE: Information on typical parametric values can be found in Chapter 2. , SO DC CHARACTERISTICS Analog Section Guaranteed Limit Symbol! Parameter Condition Voc | VEE | -55to 25C | <e5C | <125C | Unit Ron Maximum ON Resistance Vin=VitorVin: Vig=Vocte | 4.5 0.0 180 240 280 Q Veg lg <2.0mA 45 | -45 120 150 170 (Figures 1, 2) 6.0 | -6.0 100 125 140 Vin=VitorVin: Vis=Vcecor| 4.5 0.0 150 190 230 _ Vee (Endpoints); Is < 2.0 mA 45 | -4.5 100 125 140 (Figures 1, 2) 6.0 -6.0 80 ~ 160 115 ARon Maximum Difference in ON Vin = Vit or Vir 4.5 0.0 30 35 40 Q Resistance Between Any Two Vis = 1/2 (Voc ~ VEE); 45 | -45 12 15 18 Channels in the Same Package fig < 2.0 mA 6.0 -6.0 10 j2 14 lott Maximum OffChannel Leakage =| Vin = VIL or VIH: HA Curreni, Any One Channel Vio = Voo- VEE; 6.0 -6.0 0.1 0.5 1.0 Switch Off (Figure 3) Maximum Off-Channel HC4051 | Vin = VIL or Vip: 6.0 | -6.0 0.2 2.0 4.0 Leakage Current, HC4052 | Vio = Voc - VEE: 6.0 | -6.0 0.1 1.0 2.0 Common Channel HC4053 | Switch Off (Figure 4) 6.0 -6.0 0.1 1.0 2.0 lon Maximum On-Channel HC4051 | Vin = VIL or Vip: 6.0 | -6.0 0.2 2.0 4.0 BA Leakage Current, HC4052 | SwitchtoSwitch = 6.0 -6.0 0.4 1.0 2.0 Channel-to-Channel HC4053 | Voc Veg; (Figure 5) 6.0 | -6.0 0.1 1.0 2.0 MOTOROLA 3-618 High-Speed CMOS Logic Data DLi29 Rev 6MC54/74HC4051 MC74HC4052 MC54/74HC4053 AC CHARACTERISTICS (C_ = 50 pF, Input ty = tt = 6 ns) Voc Guaranteed Limit Symbol Parameter Vv 55 to 25C <85C <125C Unit tPLH Maximum Propagation Delay, Channe!Select to Analog Output 2.0 370 465 550 ns tPHL (Figure 9) 4.5 74 93 110 6.0 63 79 94 tpl, Maximum Propagation Delay, Analog Input to Analog Output 2.0 60 75 90 ns {PHL (Figure 10) 4.5 12 15 18 6.0 10 13 15 tPLz, Maximum Propagation Delay, Enable to Analog Output | 2.0 290 364 430 ns {PHZ (Figure 11) 4.5 58 73 86 6.0 49 62 73 tPZL; Maximum Propagation Delay, Enable to Analog Output 2.0 345 435 515 ns tp7y (Figure 71) : 4.5 69 87 103 6.0 59 74 87 Cin Maximum Input Capacitance, ChannelSelect or Enable Inputs 10 10 10 pF Cvo Maximum Capacitance Analog /O 35 35 35 pF (All Switches Off) Common O/!: HC4051 130 130 130 HC4052 80 80 80 HC4053 50 50 50 Feedthrough 1.0 1.0 1.0 NOTE: For propagation delays with toads other than 50 pF, and information on typical parametric values, se Chapter 2. Typical @ 25C, Voc = 5.0 V, VEE =0V Cpp Power Dissipation Capacitance (Figure 13)* HC4051 45 pF HC4052 80 HC4053 45 * Used to determine the no-load dynamic power consumption: Pp = Cpp Vccf + Ico Vcc. For load considerations, see Chapter 2. High-Speed CMOS Logic Data . 3-619 . - MOTOROLA DLi29 Rev 6 _ :MC54/74HC4051 MC74HC4052 MC54/74HC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) 0.05 Limit* Voc | VEE Symbol Parameter Cendition Vv Vv 25C Unit BW Maximum On-Channel Bandwidth | fi, = 1MHz Sine Wave; Adjust fj, Voltage to 51 | 62 | 53 | MHz or Minimum Frequency Response | Obtain OdBm at Vos; Increase fi, Frequency (Figure 8) Until dB Meter Reads -3qB: - | 225 | 2.25 | 80 | 95 | 120 Ry, = 500, Cy = 10pF 4.50 | -4.50 | 80 | 95 | 120 6.00 | -6.00 | 80 | 95 | i20 _ Off-Channe! Feedthrough Isolation | fin = Sine Wave; Adjust fi, Voltage to Obtain 2.25 | -2.25 50 dB (Figure 7) OdBm at Vis 4.50 | 4.50 50 fin = 10kHz, RL = 600, Cy = 50pF | 6.00 | -6.00 50 2.25 | -2.25 40 4.50 | -4.50 ~40 fin = 1.0MHz, RL = 50Q, Cy = 10pF | 6.00 | -6.00 40 -~ -| Feedthrough Noise. Vin S$ IMHz Square Wave (ty = ts = 6ns); 2.25 | +2.25 25 mVpp Channel-Select Input to Common | Adjust RL at Setup so that ig = 0A; 4.50 | -4.50 105 VO (Figure8) Enable = GND Ry = 600, C_ = 50pF | 6.00 | ~6.00 135 2.25 | -2.25 35 4.50 | -4,50 145 RL = 10kQ, CL = 10pF | 6.00 | -6.00 190 Crosstalk Between Any Two fin = Sine Wave; Adjust fip Voltage to Obtain 2.25 | -2.25 -50 dB Switches (Figure 12) OdBm at Vis 4.50 | -4.50 ~-50 (Test does not apply to HC4051} fin = T0KHz, Ay = 6000, C, = 50pF | 6.00 | -6.00 -50 2.25 | -2.25 -60 4.50 | -4.50 ~60 fin = 1.0MHz, RL = 50, CL = 10pF | 6.00 | -6.00 -60 THD | Total Harmonic Distortion fin = 1KHz, RL = 10kQ, CL = 50pF % (Figure 14) THD = THD measured - THD source Vig = 4.0Vpp sine wave | 2.25 | -2.25 0.10 Vig = 8.0Vpp sine wave | 4.50 | -4.50 0.08 Vig = 11.0Vpp sine wave | 6.00 {| -6.00 Limits not tested. Determined by design and verified by qualification. MOTOROLA 3-620 High-Speed CMOS Logic Data DL129 Rev 6300 g %0 i x 5 N YON ry 200 474 3 wS 125C = 160 Lf \, SS +: a rd A! NON 25C iw | / \ = 100 aA N\ o CT . SJ ee 55C o Leas oot 50 0 0 025 0.50 075 1.0 125 15 175 20 225 Vig, INPUT VOLTAGE (VOLTS), REFERENCED TO Vege Figure 1a. Typical On Resistance, Vcc VEE = 2.0 V 120 105 90 15 60 45 Ron- ON RESISTANCE (OHMS) 30 0 0 05 10 15 20 25 30 35 40 55 6.0 Vig, INPUT VOLTAGE (VOLTS), REFERENCED TO Veg Figure 1c. Typical On Resistance, Vcc VEE = 6.0 V 80 70 60 50 40 30 20 Ron ON RESISTANCE {OHMS) 0 0 10 20 30 40 Vig, INPUT VOLTAGE (VOLTS), REFERENCED TO Veg Figure 1e. Typical On Resistance, Vcc VEE = 12.0 V 6.0 7.0 80 9.0 10.0 11.0 120 MC54/74HC4051 MC74HC4052 MC54/74HC4053 120 100 = | ao a 60 40 | Ron ON RESISTANCE, (OHMS: 20 0 Q 05 = Vig, INPUT VOLTAGE (VOLTS), REFERENCED TO Veg 10 #15 20 25 30 35 40 45 Figure ib. Typical On Resistance, Vcc VEE = 4.5 V Ron ON RESISTANCE (OHMS) | 1.0 Vig, NPUT VOLTAGE (VOLTS), REFERENCED TO Vege 204630 #40 .50 60 70 80 90 Figure 1d. Typical On Resistance, Voc VEE = 9.0 V ~ PLOTTER j } PROGRAMMABLE POWER = ea MINI COMPUTER OC ANALYZER SUPPLY ~ vec DEVICE UNDER TEST ANALOG IN DA COMMON OUT t ~ GND = VY VEE Figure 2, On Resistance Test Set-Up High-Speed CMOS Logic Data DL129 Rev 6 3-621 MOTOROLAMC54/74HC4051 MC74HC4052 MC54/74HC4053 ae 16 Voc OFF OFF COMMON O44 Vi _i 5 ef EE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up vec 4 ce te} Yeo 3 NIC VEE OFF comMonon Vcc ANALOG UO Vit *4 6 7 | 8 VEE Y > Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up Vis Voc 4 Vog O4pF | 16 I dB fino] {oFF | Tt METER gn CL PL i TG 8 7 8 V = . BEY = CHANNEL SELECT Vit or Vint Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set-Up Wate VEE ANALOG VO vect_, te Vcc OFF - OFF EF | common on VIH 5 VEE [x : ~ Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up Voc Vos . : ; a O.1pF 16 a dB i tin oF ON f Tt METER Cc." g RL iu So VEE = "Includes all probe and jig capacitance Figure 6. Maximum On Channel Bandwidth, Test Set-Up Vv st RL . oA] onioF FJ COMMON Oil = ANALOG LO PONT ~~ OFFION RL Cr = Ri -L 8 ? _, 1 Voc Vin <1 MHz 8 1 V ip = tf= 6 ns VEE CC ~ F = GND j ] | CHANNEL SELECT __ "Includes all probe and jig capacitance Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up MOTOROLA 3-622 _ = _ High-Speed GMOS Logic Daia DLi29 Reve ~MC54/74HC4051 MC74HC4052 MC54/74HC4053 Vee _Yec 4 Veo { 16 CHANNEL ON/OFF # } COMMONON seg7 SELECT 50% ne analog 0 | S tt owt oT LOFFION | . GND = cL PLH < 'PHL ZL 6 ANALOG / \ . OUT 7 50% \ _. ae E ? TL = CHANNEL SELECT Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set-Up Channel to Analog Out Select to Analog Out Voc t 16 j | | | ANALOG /0 COMMON OA vee 7 pot POINT ANALOG IN 50% 7 == : wo ae oy GND L 'PLH | PHL 6 ANALOG f ; 6 8 ouT 50% K an _ *includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set-Up to Analog Out Analog In to Analog Out y > tr a POSITION 1 WHEN TESTING tpyjz AND tpz}} _, Veo ad POSITION 2 WHEN TESTING tpy_z AND ipzy, 90% . : : ENABLE \ 50% @) 40% Yoo 4 GND Voc 6 1kQ tpz. (PLZ tae - HIGH O) ANALOG I/O \MPEDANCE ON/OFF o TEST ANALOG Or eT L, POINT Out 10% = Cy" VoL - - | > = tPZH tPHZ ~ mM TL ENABLE . 5 _w ANALOG 90% OH 7 OUT 4 8 HIGH IMPEDANCE = Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set-Up Analog Out Enable to Analog Out High-Speed CMOS Logic Data 3-623 MOTOROLA DLi29 Rev 6MC54/74HC4051 MC74HC4052 MC54/74HC-4053 Vis Vos fir, + 0. tyF VEE AL == qr SRL hg: ior i* Includes ail probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set-Up Vis Voc Vos OApF 16 10 in o DISTORTION * METER T% Ono Vee = Includes all probe and jig capacitance Figure 14a, Total Harmonic Distortion, Test Set-Up Vec A v co 16 ON/OFF COMMON Ovi ANALOG HO }-0 NO = oFFron ] 8 Yoo |, = VEE 8 u = CHANNEL SELECT PLIEL __ CHANNEL SELECT | Figure 13. Power Dissipation Capacitance, Test Set-Up -10 FUNDAMENTAL FREQUENCY dB DEVICE "0 SOURCE ~ 100 1.0 20 3.125 FREQUENCY (kHz) Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at Voc or GND logic levels, Voc being recognized as a logic high and GND being recognized as a logic iow. In this exam- ple: Voc = +5V = logic high GND = OV = logic low The maximum analog voitage swings are determined by the supply voltages Voc and Ver. The positive peak analog voltage should not exceed Voc. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between Voc and Ver is ten volts. Therefore, using the configuration of Figure 15, a maximum analog sig- nal of ten volis peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.., not con- nected). However, tying unused analog inputs and outputs to Vcc or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. . Although used here, balanced supplies are not a require- ment. The only constraints on the power supplies are that: Voc - GND = 2 to 6 volts VEE GND = 0 to -6 volts Voc - VEE = 2 to 12 volts and VEE < GND When voltage transients above Voc and/or below VEE are anticipated on the analog chanriels, external Germanium or Schottky diodes (Dy) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current Surges during clipping. MOTOROLA 3-624 High-Speed CMOS Logic Data DL129 Rev 6*V \ ANALOG 5V at ANALOG /\, MC54/74HC4051 MC74HC4052 MC54/74HC4053 +5V sy UU SIGNAL tree 10 - 9| Vy SIGNAL UU sy TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS Figure 15. Application Example *8V \ ANALOG | +5V 16 ANALOG /*\ +5V Ves SIGNAL co I oD SIGNAL +5V UR VEE 1ife I LSTTL/NMOS 10 CIRCUITRY 9 Vee Y = +L *2K SAS 10K = a. Using Pull-Up Resistors +5V VEE Vj v cc Vec 4 cc Dy 16 Dy ON/OFF Dy Dy VEE VEE a VEEY = Figure 16. External Germanium or Schottky Clipping Diodes f +5V 16 Figure 17. interfacing LSTTL/NMOS to CMOS Inputs att>o LEVEL SHIFTER st >o LEVEL SHIFTER ~ 2D, anatos |p| anatoa fy #Y .. > sienat [=] signa Wye r7 | | +V h sn [> {Lf istmmos 5 3 CIRCUITRY Vi Le oe od cE Hct = BUFFER b. Using HCT Interface 18.4 ae + d J c+_>o LEVEL SHIFTER d_) d ENABLE So LEVEL SHIFTER Figure 18. Function Diagram, HC4051 High-Speed CMOS Logic Data DL129 Rev 6 3-625 MOTOROLAMC54/74HC4051 MC74HC4052 MC54/74HC4053 ae . piso ENABLE {0 A i > s->o_ c+>o_ ENABLE ->o- LEVEL fF 12 SHIFTER xo br st ol FB LEVEL 7 > 15 SHIFTER }d 9=# f>-4+ > ratte 14 4d 3 x3 x _LEVEL 3 SHIFTER q> 8 [|_ {> t [>e EA YO 5 reo! HE 2 y Figure 19. Function Diagram, HC4052 [EVEL _ 3 4 SHIFTER. | 2 ay LEVEL [- #9) ty, SHIFTER LI 2 v9 By LEVEL 3 SHIFTER z\ 45 LEVEL oo . SHIFTER [> Figure 20. Function Diagram, HC4053 MOTOROLA 3-626 - . High-Speed CMOS Logic Data DL129-Rev6 ~