Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - (c) NXP N.V. (year). All rights reserved or (c) Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - (c) Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS 74F74 Dual D-type flip-flop Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 FEATURE PIN CONFIGURATION * Industrial temperature range available (-40C to +85C) DESCRIPTION The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. TYPE 74F74 RD0 1 14 VCC D0 2 13 RD1 CP0 3 12 D1 SD0 4 11 CP1 Q0 5 10 SD1 Q0 6 9 Q1 GND 7 8 Q1 SF00045 TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 125MHz 11.5mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C PKG. DWG. # 14-pin plastic DIP N74F74N I74F74N SOT27-1 14-pin plastic SO N74F74D I74F74D SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION D0, D1 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20A/0.6mA CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20A/0.6mA SD0, SD1 Set inputs (active low) 1.0/3.0 20A/1.8mA RD0, RD1 Reset inputs (active low) 1.0/3.0 20A/1.8mA Q0, Q1, Q0, Q1 Data outputs 50/33 NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. LOGIC SYMBOL IEC/IEEE SYMBOL 2 12 4 D0 D1 3 CP0 4 SD0 5 C1 2 1 1 RD0 11 CP1 10 SD1 13 RD1 10 5 1D 6 R S 9 11 C2 12 13 6 9 2D 8 R 8 SF00047 SF00046 1996 Mar 12 & S 3 Q0 Q0 Q1 Q1 VCC = Pin 14 GND = Pin 7 1.0mA/20mA 2 853 0335 16554 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 LOGIC DIAGRAM FUNCTION TABLE INPUTS SD RD CP D 4, 10 5, 9 1, 13 Q 6, 8 3, 11 Q OUTPUTS OPERATING MODE SD RD CP D Q Q L H X X H L Asynchronous set H L X X L H Asynchronous reset L L X X H H Undetermined* H H h H L Load "1" H H l L H Load "0" H H X NC NC Hold NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level. 2, 12 VCC = Pin 14 GND = Pin 7 SF00048 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage -0.5 to +7.0 V VIN Input voltage -0.5 to +7.0 V IIN Input current -30 to +5 mA VOUT Voltage applied to output in high output state -0.5 to VCC V IOUT Current applied to output in low output state 40 mA Commercial range 0 to +70 Tamb Operating free air temperature range C Industrial range -40 to +85 C Tstg Storage temperature range -65 to +150 C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current -18 mA IOH High-level output current -1 mA IOL Low-level output current Tambb 1996 Mar 12 Operating O erating free air tem temperature erature range V V 20 mA Commercial range 0 +70 C Industrial range -40 +85 C 3 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O High level output voltage High-level VCC = MIN MIN, VIL = MAX, MAX VIH = MIN VOL O Low level output voltage Low-level VCC = MIN MIN, VIL = MAX, MAX VIH = MIN VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current IOH O = MAX IOL O = MAX 10%VCC 2.5 5%VCC 2.7 10%VCC 5%VCC TYP2 MAX UNIT V 3.4 V 0.30 0.50 V 0.30 0.50 V -0.73 -1.2 V 100 A VCC = MAX, VI = 2.7V 20 A VCC = MAX, VI = 0.5V -0.6 mA SDn, RDn VCC = MAX, VI = 0.5V Low-level input current IOS Short-circuit output current3 Supply current (total) MIN Dn, CPn IIL ICC LIMITS TEST CONDITIONS1 PARAMETER 4 VCC = MAX -60 VCC = MAX 11.5 -1.8 mA -150 mA 16 mA NOTES: 1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2 All typical values are at VCC = 5V, Tamb = 25C. 3 Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4 Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn. AC ELECTRICAL CHARACTERISTICS LIMITS VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF, RL = 500 PARAMETER TEST CONDITION MIN TYP fmax Maximum clock frequency Waveform 1 100 125 tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 3.8 4.4 5.3 6.2 6.8 8.0 3.8 4.4 7.8 9.2 3.8 4.4 8.5 9.2 ns tPLH tPHL Propagation delay SDn, RDn to Qn or Qn Waveform 2 3.2 3.5 4.6 7.0 6.1 9.0 3.2 3.5 7.1 10.5 3.2 2.5 7.5 10.5 ns SYMBOL MAX MIN MAX 100 MIN UNIT MAX 90 MHz AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF, RL = 500 MIN UNIT MAX tsu (H) tsu (L) Setup time, high or low Dn to CPn Waveform 1 2.0 3.0 2.0 3.0 2.0 3.0 ns th (H) th (L) Hold time, high or low Dn to CPn Waveform 1 1.0 1.0 1.0 1.0 1.0 1.0 ns tw (H) tw (L) CPn pulse width, high or low Waveform 1 4.0 5.0 4.0 5.0 4.0 5.0 ns tw (L) SDn, RDn pulse width, low Waveform 2 4.0 4.0 4.0 ns trec Recovery time SDn, RDn to CPn Waveform 3 2.0 2.0 2.0 ns 1996 Mar 12 4 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn VM tsu(L) VM VM tsu(H) th(L) VM tw(L) SDn VM VM th(H) 1/fmax CPn VM VM tw(L) RDn tw(L) VM VM tw(H) VM tPHL tPLH tPHL tPLH Qn Qn VM VM VM VM tPLH tPHL tPLH tPHL VM VM Qn VM VM Qn SF00050 Waveform 2. Propagation delay for set and reset to output, set and reset pulse width SF01276 Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency SDn or RDn VM trec CPn VM SF00051 Waveform 3. Recovery time for set or reset to clock TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Mar 12 5 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 DIP14: plastic dual in-line package; 14 leads (300 mil) 1996 Mar 12 6 SOT27-1 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1996 Mar 12 7 SOT108-1 Philips Semiconductors Product specification Dual D-type flip-flop 74F74 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 8 Date of release: 10-98 9397-750-05066