LTC2440
1
2440fd
2440 TA01
2440 TA01
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE 6.9Hz, 200nV NOISE,
50/60Hz REJECTION
880Hz OUTPUT RATE,
2μV NOISE
10-SPEED SERIAL
PROGRAMMABLE
VCC
4.5V TO 5.5V
4
VCC BUSY
fO
REF+
SCK
IN+
IN–
SDO
GND
CS
EXT
SDI
LTC2440
REF–
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
24-Bit High Speed
Differential
Δ∑
ADC with
Selectable Speed/Resolution
The LTC
®
2440 is a high speed 24-bit No Latency Δ∑
TM
ADC with 5ppm INL and 5μV offset. It uses proprietary
delta-sigma architecture enabling variable speed and reso-
lution with no latency. Ten speed/resolution combinations
(6.9Hz/200nVRMS to 3.5kHz/25μVRMS) are programmed
through a simple serial interface. Alternatively, by tying a
single pin HIGH or LOW, a fast (880Hz/2μVRMS) or ultralow
noise (6.9Hz, 200nVRMS, 50/60Hz rejection) speed/reso-
lution combination can be easily selected. The accuracy
(offset, full-scale, linearity, drift) and power dissipation
are independent of the speed selected. Since there is no
latency, a speed/resolution change may be made between
conversions with no degradation in performance.
Following each conversion cycle, the LTC2440 automati-
cally enters a low power sleep state. Power dissipation
may be reduced by increasing the duration of this sleep
state. For example, running at the 3.5kHz conversion speed
but reading data at a 100Hz rate draws 240μA average
current (1.1mW) while reading data at a 7Hz output rate
draws only 25μA (125μW).The LTC2440 communicates
through a fl exible 3-wire or 4-wire digital interface that is
compatible with the LTC2410 and is available in a narrow
16-lead SSOP package.
Simple 24-Bit 2-Speed Acquisition System
n Up to 3.5kHz Output Rate
n Selectable Speed/Resolution
n 2μVRMS Noise at 880Hz Output Rate
n 200nVRMS Noise at 6.9Hz Output Rate with
Simultaneous 50/60Hz Rejection
n 0.0005% INL, No Missing Codes
n Autosleep Enables 20μA Operation at 6.9Hz
n <5μV Offset (4.5V < VCC < 5.5V, –40°C to 85°C)
n Differential Input and Differential Reference with
GND to VCC Common Mode Range
n No Latency, Each Conversion is Accurate Even After
an Input Step
n Internal Oscillator—No External Components
n Pin Compatible with the LTC2410
n 24-Bit ADC in Narrow 16-Lead SSOP Package
n High Speed Multiplexing
n Weight Scales
n Auto Ranging 6-Digit DVMs
n Direct Temperature Measurement
n High Speed Data Acquisition
Speed vs RMS Noise
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency Δ∑ is a trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
CONVERSION RATE (Hz)
1
0.1
RMS NOISE (μV)
1
10
100
10 100
2440 TA02
1000 10000
VCC = 5V
VREF = 5V
VIN+ = VIN– = 0V
2μV AT 880Hz
200nV AT 6.9Hz
(50/60Hz REJECTION)
LTC2440
2
2440fd
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) to GND ....................... –0.3V to 6V
Analog Input Pins Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND .......–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2440C ............................................... 0°C to 70°C
LTC2440I .............................................–40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Notes 1,2)
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VCC
REF+
REF–
IN+
IN–
SDI
GND
GND
BUSY
fO
SCK
SDO
CS
EXT
GND
TJMAX = 125°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2440CGN#PBF LTC2440CGN#TRPBF 2440 Narrow 16-Lead SSOP 0°C to 70°C
LTC2440IGN#PBF LTC2440IGN#TRPBF 2440I Narrow 16-Lead SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) l24 Bits
Integral Nonlinearity VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
l5
315 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC (Note 12) l2.5 5 μV
Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC 20 nV/°C
Positive Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25V
REF+ = 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V
l
l
10
10 30
50 ppm of VREF
ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+0.2 ppm of VREF/°C
Negative Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75V
REF+ = 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V
l
l
10
10 30
50 ppm of VREF
ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+0.2 ppm of VREF/°C
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN– = IN+ ≤ VCC 120 dB
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Notes 3, 4)
LTC2440
3
2440fd
ANALOG INPUT AND REFERENCE
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage lGND – 0.3V VCC + 0.3V V
IN–Absolute/Common Mode IN– Voltage lGND – 0.3V VCC + 0.3V V
VIN Input Differential Voltage Range (IN+ – IN–)l–VREF/2 VREF/2 V
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND VCC – 0.1V V
VREF Reference Differential Voltage Range (REF+
– REF–)
l0.1 VCC V
CS(IN+)IN+ Sampling Capacitance 3.5 pF
CS(IN–)IN– Sampling Capacitance 3.5 pF
CS(REF+)REF+ Sampling Capacitance 3.5 pF
CS(REF–)REF– Sampling Capacitance 3.5 pF
IDC_LEAK(IN+, IN–,
REF+, REF–)
Leakage Current, Inputs and Reference CS = VCC, IN+ = GND, IN– = GND,
REF+ = 5V, REF– = GND
l–100 10 100 nA
ISAMPLE(IN+, IN–,
REF+, REF–)
Average Input/Reference Current During
Sampling Varies, See Applications Section
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN High Level Input Voltage
CS, fO, SDI 4.5V ≤ VCC ≤ 5.5V l2.5 V
VIL Low Level Input Voltage
CS, fO, SDI 4.5V ≤ VCC ≤ 5.5V l0.8 V
VIN High Level Input Voltage
SCK 4.5V ≤ VCC ≤ 5.5V (Note 8) l2.5 V
VIL Low Level Input Voltage
SCK 4.5V ≤ VCC ≤ 5.5V (Note 8) l0.8 V
IIN Digital Input Current
CS, fO
0V ≤ VIN ≤ VCC l–10 10 μA
IIN Digital Input Current
SCK 0V ≤ VIN ≤ VCC (Note 8) l–10 10 μA
CIN Digital Input Capacitance
CS, fO
10 pF
CIN Digital Input Capacitance
SCK (Note 8) 10 pF
VOH High Level Output Voltage
SDO, BUSY IO = –800μA lVCC – 0.5V V
VOL Low Level Output Voltage
SDO, BUSY IO = 1.6mA l0.4V V
VOH High Level Output Voltage
SCK IO = –800μA (Note 9) lVCC – 0.5V V
VOL Low Level Output Voltage
SCK IO = 1.6mA (Note 9) l0.4V V
IOZ Hi-Z Output Leakage
SDO
l–10 10 μA
The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
LTC2440
4
2440fd
↑
↑
↑
↑
↑
↑
POWER REQUIREMENTS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5 to 5.5V unless otherwise specifi ed.
VREF = REF+ – REF–
, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–
, VINCM = (IN+ + IN–)/2.
Note 4: fO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specifi ed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l4.5 5.5 V
ICC Supply Current
Conversion Mode
Sleep Mode
CS = 0V (Note 7)
CS = VCC (Note 7)
l
l
8
811
30 mA
μA
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 3)
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 3)
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator. fO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1μs (typical) to
the conversion time.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range l0.1 20 MHz
tHEO External Oscillator High Period l25 10000 ns
tLEO External Oscillator Low Period l25 10000 ns
tCONV Conversion Time OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
External Oscillator (Note 10, 13)
l
l
l
0.99
126 1.13
145
40 • OSR + 170
fEOSC(kHz)
1.33
170 ms
ms
ms
fISCK Internal SCK Frequency Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
l0.8 0.9
fEOSC /10 1
DISCK Internal SCK Duty Cycle (Note 9) l45 55 %
fESCK External SCK Frequency Range (Note 8) l20 MHz
tLESCK External SCK Low Period (Note 8) l25 ns
tHESCK External SCK High Period (Note 8) l25 ns
tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l30.9 35.3
320/fEOSC
41.6 μs
s
tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 8) l32/fESCK s
t1CS to SDO Low Z (Note 12) l025ns
t2CS ↑ to SDO High Z (Note 12) l025ns
t3CS to SCK (Note 9) l5μs
t4CS to SCK ↑(Notes 8, 12) l25 ns
tKQMAX SCK to SDO Valid l25 ns
tKQMIN SDO Hold After SCK (Note 5) l15 ns
t5SCK Set-Up Before CS l50 ns
t7SDI Setup Before SCK ↑(Note 5) l10 ns
t8SDI Hold After SCK ↑(Note 5) l10 ns
↑
LTC2440
5
2440fd
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity fOUT = 3.5kHz
Integral Nonlinearity
fOUT = 1.76kHz Integral Nonlinearity fOUT = 880Hz
Integral Nonlinearity fOUT = 440Hz Integral Nonlinearity fOUT = 220Hz Integral Nonlinearity fOUT = 110Hz
Integral Nonlinearity fOUT = 55Hz Integral Nonlinearity fOUT = 27.5Hz
Integral Nonlinearity
fOUT = 13.75Hz
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G01
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G02
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G03
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G04
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G05
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G06
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G07
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G08
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G09
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
LTC2440
6
2440fd
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
fOUT = 6.875Hz
Integral Nonlinearity
vs Conversion Rate Integral Nonlinearity vs VINCM
Integral Nonlinearity
vs Temperature
Integral Nonlinearity
vs Temperature –Full-Scale Error vs VREF
+Full-Scale Error vs VREF –Full-Scale Error vs VCC +Full-Scale Error vs VCC
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G10
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
fO = GND
TA = 25°C
CONVERSION RATE (Hz)
0
0
INL ERROR (ppm OF VREF)
2.5
5.0
7.5
10.0
500 1000 1500 2000
2440 G11
2500 3000 3500
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
–2.5V ≤ VIN ≤ 2.5V
VINCM = 2.5V
fO = GND
TA = 25°C
VIN (V)
–1.25
INL ERROR (ppm OF VREF)
0
5
0.75
2440 G12
–5
–10 –0.75 –0.25 1.25
10
0.25
VCC = 5V
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
OSR = 32768
fO = GND
TA = 25°C
VINCM = 1.25V
VINCM = 3.75V
VINCM = 2.5V
VIN (V)
–1.25
INL ERROR (ppm OF VREF)
0
5
0.75
2440 G13
–5
–10 –0.75 –0.25 1.25
10
0.25
VCC = 5V
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VINCM = 1.25V
OSR = 32768
fO = GND
TA = 25°C
TA = –55°C TA = 125°C
VIN (V)
–2.5
INL ERROR (ppm OF VREF)
0
5
1.5
2440 G14
–5
–10 –1.5 –0.5 02.5
10
0.5
–2 –1 2
1
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
OSR = 32768
fO = GND
TA = –25°C
TA = 125°C
TA = 25°C
VREF (V)
0
–FULL-SCALE ERROR (ppm OF VREF)
0
10
4
2440 G15
–10
–20 1235
20
VREF (V)
0
+FULL-SCALE ERROR (ppm OF VREF)
0
10
4
2440 G16
–10
–20 1235
20
VCC (V)
4.5
FULL-SCALE ERROR (ppm OF VREF)
6
8
10
5.3
2440 G17
4
2
5
7
9
3
1
04.7 4.9 5.1 5.5
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VINCM = 1.25V
OSR = 32768
fO = GND
TA = 25°C
VCC (V)
4.5
FULL-SCALE ERROR (ppm OF VREF)
–4
–2
0
5.3
2440 G18
–6
–8
–5
–3
–1
–7
–9
–10 4.7 4.9 5.1 5.5
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VINCM = 1.25V
OSR = 32768
fO = GND
TA = 25°C
LTC2440
7
2440fd
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Full-Scale Error
vs Temperature
Positive Full-Scale Error
vs Temperature Offset Error vs VCC
Offset Error vs Conversion Rate Offset Error vs VINCM RMS Noise vs Temperature
Offset Error vs Temperature
INL vs Output Rate
(OSR = 128) External Clock Sweep
10MHz to 20MHz
RMS Noise vs Output Rate
(OSR = 128) External Clock
Sweep 10MHz to 20MHz
TEMPERATURE (°C)
–55
FULL-SCALE ERROR (ppm OF VREF)
5
10
15
125
2440 G19
–5
–20 –25 5 35 65 95
20
0
–10
–15
4.5V
5V
5.5V
VCC = 4.5V
VREF = 4.5V
VREF+ = 4.5V
VREF– = GND
VINCM = 2.25V
OSR = 32768
fO = GND
VCC = 5.5V, 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
OSR = 32768
fO = GND
TEMPERATURE (°C)
–55
FULL-SCALE ERROR (ppm OF VREF)
5
10
15
125
2440 G20
–5
–20 –25 5 35 65 95
20
0
–10
–15
4.5V
5V
5.5V
VCC = 4.5V
VREF = 4.5V
VREF+ = 4.5V
VREF– = GND
VINCM = 2.25V
OSR = 32768
fO = GND
VCC = 5.5V, 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VINCM = 2.5V
OSR = 32768
fO = GND
VCC (V)
4.5
OFFSET ERROR (ppm OF VREF)
0
2.5
5.3
2440 G21
–2.5
–5.0 4.7 4.9 5.1 5.5
5.0 VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VIN+ = VIN– = GND
OSR = 32768
fO = GND
TA = 25°C
CONVERSION RATE (Hz)
0
–5.0
OFFSET ERROR (ppm OF VREF)
–2.5
0
2.5
5.0
500 1000 1500 2000
2440 G22
2500 3000 3500
VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VIN+ = VIN– = GND
fO = GND
TA = 25°C
VINCM (V)
0
OFFSET ERROR (ppm OF VREF)
0
2.5
4
2440 G23
–2.5
–5.0 1235
5.0 VCC = 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VIN+ = VIN– = VINCM
OSR = 32768
fO = GND
TA = 25°C
TEMPERATURE (°C)
–55
0.5
RMS NOISE (μV)
1.0
1.5
2.0
2.5
3.5
–25 53565
2440 G24
95 125
3.0
VCC = 4.5V
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VIN+ = VIN– = GND
OSR = 256
fO = GND
VCC = 5.5V, 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VIN+ = VIN– = GND
OSR = 256
fO = GND
VCC = 5V
VCC = 5.5V
VCC = 4.5V
TEMPERATURE (°C)
–55
–5.0
OFFSET ERROR (μV)
–2.5
0
2.5
5.0
–25 53565
2440 G25
95 125
VCC = 4.5V
VREF = 2.5V
VREF+ = 2.5V
VREF– = GND
VIN+ = VIN– = GND
OSR = 256
fO = GND
VCC = 5.5V, 5V
VREF = 5V
VREF+ = 5V
VREF– = GND
VIN+ = VIN– = GND
OSR = 256
fO = GND
VCC = 5V VCC = 5.5V VCC = 4.5V
OUTPUT RATE (Hz)
2000 2500 3000 3500 4000
LINEARITY (BITS)
2440 G26
20
18
16
14
12
10
8
6
4
2
0
EXTERNAL CLOCK 10MHz
(OR INTERNAL OSCILLATOR)
VREF = VCC = 5V
TEMP = 25°C
SWEEP (VIN – VREF/2) TO VREF/2
EXTERNAL
CLOCK 20MHz
OUTPUT RATE (Hz)
2000 2500 3000 3500 4000
RMS NOISE (μV)
2440 G27
5
4
3
2
1
0
VREF = VCC = 5V
TEMP = 25°C
VIN ±VREF/2
LTC2440
8
2440fd
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins
internally connected for optimum ground current fl ow and
VCC decoupling. Connect each one of these pins to a ground
plane through a low impedance connection. All four pins
must be connected to ground for proper operation.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF–, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between GND
– 0.3V and VCC + 0.3V. Within these limits the converter
bipolar input range (VIN = IN+ – IN–) extends from –0.5
• (VREF) to 0.5 • (VREF). Outside this input range the
converter produces unique overrange and underrange
output codes.
SDI (Pin 7): Serial Data Input. This pin is used to select
the speed/resolution of the converter. If SDI is grounded
(pin compatible with LTC2410) the device outputs data at
880Hz with 21 bits effective resolution. By tying SDI HIGH,
the converter enters the ultralow noise mode (200nVRMS)
with simultaneous 50/60Hz rejection at 6.9Hz output
rate. SDI may be driven logic HIGH or LOW anytime dur-
ing the conversion or sleep state in order to change the
speed/resolution. The conversion immediately following
the data output cycle will be valid and performed at the
newly selected output rate/resolution. SDI may also be
programmed by a serial input data stream under control of
SCK during the data output cycle. One of ten speed/resolu-
tion ranges (from 6.9Hz/200nVRMS to 3.5kHz/21μVRMS)
may be selected. The fi rst conversion following a new
selection is valid and performed at the newly selected
speed/resolution.
EXT (Pin 10): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting
data. If EXT is tied low (pin compatible with the LTC2410),
the device is in the external SCK mode and data is shifted
out the device under the control of a user applied serial
clock. If EXT is tied high, the internal serial clock mode
is selected. The device generates its own SCK signal and
outputs this on the SCK pin. A framing signal BUSY (Pin 15)
goes low indicating data is being output.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output. The
conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is used
as digital input for the external serial interface clock during
the Data Output period. The Serial Clock Operation mode is
determined by the logic level applied to the EXT pin.
fO (Pin 14): Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When fO is connected to
VCC or GND, the converter uses its internal oscillator running
at 9MHz. The conversion rate is determined by the selected
OSR such that tCONV (in ms) = (40 • OSR + 170)/9000
(tCONV = 1.137ms at OSR = 256, tCONV = 146ms at OSR =
32768). The fi rst null is located at 8/tCONV, 7kHz at OSR =
256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768.
When fO is driven by an oscillator with frequency fEOSC (in
kHz), the conversion time becomes tCONV = (40 • OSR +
170)/fEOSC (in ms) and the fi rst null remains 8/tCONV.
BUSY (Pin 15): Conversion in Progress Indicator. For
compatibility with the LTC2410, this pin should not be
tied to ground. This pin is HIGH while the conversion
is in progress and goes LOW indicating the conversion
is complete and data is ready. It remains low during the
sleep and data output states. At the conclusion of the data
output state, it goes HIGH indicating a new conversion
has begun.
LTC2440
9
2440fd
FUNCTIONAL BLOCK DIAGRAM
TEST CIRCUITS
APPLICATIONS INFORMATION
Figure 1. Functional Block Diagram
Figure 2. LTC2440 State Transition Diagram
CONVERTER OPERATION
Converter Operation Cycle
The LTC2440 is a high speed, delta-sigma analog-to-digital
converter with an easy to use 4-wire serial interface (see
Figure 1). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 4-wire interface consists
of serial data input (SDI), serial data output (SDO), serial
clock (SCK) and chip select (CS). The interface, timing,
operation cycle and data out format is compatible with
the LTC2410.
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
GND
VCC
IN+
IN–
SDO
SCK
REF+
REF–
CS
SDI
BUSY
EXT
fO
(INT/EXT)
2440 F01
–+
+
–
1.69k
SDO
2440 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
1.69k
SDO
2440 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
CONVERT
SLEEP
DATA OUTPUT
2440 F02
TRUE
FALSE CS = LOW
AND
SCK
LTC2440
10
2440fd
APPLICATIONS INFORMATION
Initially, the LTC2440 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
below 10μA. The part remains in the sleep state as long
as CS is HIGH. The conversion result is held indefi nitely
in a static shift register while the converter is in the sleep
state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion
just performed. This result is shifted out on the serial data
out pin (SDO) under the control of the serial clock (SCK).
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32-bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
Through timing control of the CS, SCK and EXT pins,
the LTC2440 offers several fl exible modes of operation
(internal or external SCK). These various modes do not
require programming confi guration registers; moreover,
they do not disturb the cyclic operation described above.
These modes of operation are described in detail in the
Serial Interface Timing Modes section.
Ease of Use
The LTC2440 data output has no latency, fi lter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy. Speed/resolution adjust-
ments may be made seamlessly between two conversions
without settling errors.
The LTC2440 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2440 automatically enters an internal reset state
when the power supply voltage VCC drops below ap-
proximately 2.2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection.
When the VCC voltage rises above this critical threshold, the
converter creates an internal power-on-reset (POR) signal
with a duration of approximately 0.5ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2440 starts a normal conversion cycle and follows the
succession of states described above. The fi rst conversion
result following POR is accurate within the specifi cations
of the device if the power supply voltage is restored within
the operating range (4.5V to 5.5V) before the end of the
POR time interval.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage specifi cation
for the REF+ and REF– pins covers the entire range from
GND to VCC. For correct converter operation, the REF+ pin
must always be more positive than the REF– pin.
The LTC2440 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi -
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute/com-
mon mode range for the IN+ and IN– input pins extending
from GND – 0.3V to VCC + 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2440 converts the bipolar differential input
signal, VIN = IN+ – IN–, from –FS = –0.5 • VREF to +FS =
LTC2440
11
2440fd
APPLICATIONS INFORMATION
Figure 3. Output Data Timing
0.5 • VREF where VREF = REF+ – REF–. Outside this range,
the converter indicates the overrange or the underrange
condition using distinct output codes.
Output Data Format
The LTC2440 serial output data stream is 32-bits long.
The fi rst 3-bits represent status information indicating
the sign and conversion state. The next 24-bits are the
conversion result, MSB fi rst. The remaining 5-bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effec-
tive bits of performance are possible (see Table 3). Under
these conditions, sub LSBs are included in the conversion
result and represent useful information beyond the 24-bit
level. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the dif-
ferential input voltage is above +FS). For input conditions
in excess of twice full scale (|VIN| ≥ VREF), the converter
may indicate either overrange or underrange. Once the
input returns to the normal operating range, the conversion
result is immediately accurate within the specifi cations of
the device.
Bit 31 (fi rst output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most signifi cant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 • VREF 0011
0V ≤ VIN < 0.5 • VREF 0010
–0.5 • VREF ≤ VIN < 0V 0001
VIN < –0.5 • VREF 0000
Bits ranging from 28 to 5 are the 24-bit conversion result
MSB fi rst.
Bit 5 is the Least Signifi cant Bit (LSB).
Bits ranging from 4 to 0 are sub LSBs below the 24-bit
level. Bits 4 to bit 0 may be included in averaging or dis-
carded without loss of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance.
In order to shift the conversion result out of the device,
CS must fi rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
MSBSIG“0”
1 2 3 4 5 262732
BIT 0BIT 27 BIT 5
LSB24
BIT 28BIT 29BIT 30
SDO
SCK
BUSY
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2440 F03
Hi-Z
LTC2440
12
2440fd
APPLICATIONS INFORMATION
microcontroller. Bit 31 (EOC) can be captured on the fi rst
rising edge of SCK. Bit 30 is shifted out of the device on
the fi rst falling edge of SCK. The fi nal data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins is main-
tained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
SERIAL INTERFACE PINS
The LTC2440 transmits the conversion results and receives
the start of conversion command through a synchronous
2-wire, 3-wire or 4-wire interface. During the conversion
and sleep states, this interface can be used to assess
the converter status and during the data output state it
is used to read the conversion result and program the
speed/resolution.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2440 creates its own serial clock. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected
by tying EXT (Pin 10) LOW for external SCK and HIGH
for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
fi rst) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH
on the SDO pin. Once the conversion is complete, EOC
goes LOW. The device remains in the sleep state until the
fi rst rising edge of SCK occurs while CS = LOW.
Table 2. LTC2440 Output Data Format
Differential Input Voltage
VIN*
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB Bit 27 Bit 26 Bit 25 … Bit 0
VIN* ≥ 0.5 • VREF** 0011000…0
0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1
0.25 • VREF** 0010100…0
0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1
0 0010000…0
–1LSB 0001111…1
–0.25 • VREF** 0001100…0
–0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1
–0.5 • VREF** 0001000…0
VIN* < –0.5 • VREF** 0000111…1
*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.
LTC2440
13
2440fd
APPLICATIONS INFORMATION
Chip Select Input (CS)
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
In addition, the CS signal can be used to trigger a new con-
version cycle before the entire serial data transfer has been
completed. The LTC2440 will abort any serial data transfer
in progress and start a new conversion cycle anytime a
LOW-to-HIGH transition is detected at the CS pin after the
converter has entered the data output state (i.e., after the
fi fth falling edge of SCK occurs with CS = LOW).
Serial Data Input (SDI)—Logic Level Speed Selection
The serial data input (SDI, Pin 7) is used to select the
speed/resolution of the LTC2440. A simple 2-speed control
is selectable by either driving SDI HIGH or LOW. If SDI
is grounded (pin compatible with LTC2410) the device
outputs data at 880Hz with 21 bits effective resolution. By
tying SDI HIGH, the converter enters the ultralow noise
mode (200nVRMS) with simultaneous 50/60Hz rejection at
6.9Hz output rate. SDI may be driven logic HIGH or LOW
anytime during the conversion or sleep state in order to
change the speed/resolution. The conversion immediately
following the data output cycle will be valid and performed
at the newly selected output rate/resolution.
Changing SDI logic state during the data output cycle
should be avoided as speed resolution other than 6.9Hz
or 880Hz may be selected. For example, if SDI is changed
from logic 0 to logic 1 after the second rising edge of SCK,
the conversion rate will change from 880Hz to 55Hz (the
following values are listed in Table 3: OSR4 = 0, OSR3 = 0,
OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH,
the conversion rate will switch to the desired 6.9Hz speed
immediately following the conversion at 55Hz. The 55Hz
rate conversion cycle will be a valid result as well as the
fi rst 6.9Hz result. On the other hand, if SDI is changed to a
1 anytime before the fi rst rising edge of SCK, the following
conversion rate will become 6.9Hz. If SDI is changed to
a 1 after the 5th rising edge of SCK, the next conversion
will remain 880Hz while all subsequent conversions will
be at 6.9Hz.
Serial Data Input (SDI)—Serial Input Speed Selection
SDI may also be programmed by a serial input data
stream under control of SCK during the data output cycle,
see Figure 4. One of ten speed/resolution ranges (from
6.9Hz/200nVRMS to 3.5kHz/21μVRMS) may be selected, see
Table 3. The conversion following a new selection is valid
and performed at the newly selected speed/resolution.
BUSY
The BUSY output (Pin 15) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device. It goes HIGH at the conclusion
of the data output cycle indicating a new conversion has
begun. This rising edge may be used to fl ag the comple-
tion of the data read cycle.
SERIAL INTERFACE TIMING MODES
The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI
and MICROWIRE compatible. This interface offers several
fl exible modes of operation. These include internal/external
serial clock, 2-wire or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (fO =
LOW) or an external oscillator connected to the fO pin.
See Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
LTC2440
14
2440fd
APPLICATIONS INFORMATION
Figure 4. SDI Speed/Resolution Programming
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 1 BIT 0
LSB
Hi-Z
2440 F04
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
*OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE
OSR4* OSR3 OSR2 OSR1 OSR0
Table 3. SDI Speed/Resolution Programming
OSR4 OSR3 OSR2 OSR1 OSR0
CONVERSION RATE
RMS
NOISE ENOB OSR
INTERNAL
9MHz CLOCK
EXTERNAL
10.24MHz CLOCK
X 0 0 0 1 3.52kHz 4kHz 23μV 17 64
X 0 0 1 0 1.76kHz 2kHz 3.5μV 20 128
0 0 0 0 0 880Hz 1kHz 2μV 21.3 256*
X 0 0 1 1 880Hz 1kHz 2μV 21.3 256
X 0 1 0 0 440Hz 500Hz 1.4μV 21.8 512
X 0 1 0 1 220Hz 250Hz 1μV 22.4 1024
X 0 1 1 0 110Hz 125Hz 750nV 22.9 2048
X 0 1 1 1 55Hz 62.5Hz 510nV 23.4 4096
X 1 0 0 0 27.5Hz 31.25Hz 375nV 24 8192
X 1 0 0 1 13.75Hz 15.625Hz 250nV 24.4 16384
X 1 1 1 1 6.875Hz 7.8125Hz 200nV 24.6 32768**
**Address allows tying SDI HIGH *Additional address to allow tying SDI LOW
↑
↑
Table 4. LTC2440 Interface Timing Modes
Confi guration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal CS CS Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
LTC2440
15
2440fd
APPLICATIONS INFORMATION
Figure 5. External Serial Clock, Single Cycle Operation
EOC = 1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the low
power sleep state once the conversion is complete.
When the device is in the sleep state (EOC = 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the fi rst rising
edge of SCK is seen. Data is shifted out the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fi fth falling edge (SDI must
be properly loaded each cycle) and the 32nd falling edge
of SCK, see Figure 6. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
7. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. Conversely, BUSY (Pin 15) may
be used to monitor the status of the conversion cycle.
EOC or BUSY may be used as an interrupt to an external
EOC
BIT 31
SDO
BUSY
SCK
(EXTERNAL)
CS
TEST EOC
SUB LSBMSBSIG
BIT 0
LSB
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
2440 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOCTEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
BUSY
REF+
REF–SCK
IN+
IN–
SDO
GND
CS
EXT
2
14
15
3
413
5
6
12
1, 8, 9, 16
11
10
SDI 7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
LTC2440
16
2440fd
APPLICATIONS INFORMATION
Figure 6. External Serial Clock, Reduced Data Output Length
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
SDO
15
BUSY
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSIONSLEEP SLEEP
TEST EOC TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2410 F06
MSBSIG
BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30
EOC
BIT 31BIT 0
EOC
Hi-Z
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–SCK
IN+
IN–
SDO
GND
CS
EXT
2
14
BUSY 15
3
413
5
6
12
1, 8, 9, 16
11
10
SDI 7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
EOC
BIT 31
SDO
BUSY
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB24
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
2440 F07
CONVERSION
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–SCK
IN+
IN–
SDO
GND
CS
EXT
2
14
BUSY 15
3
413
5
6
12
1, 8, 9, 16
11
10
SDI 7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
LTC2440
17
2440fd
APPLICATIONS INFORMATION
Figure 8. Internal Serial Clock, Single Cycle Operation
controller indicating the conversion result is ready. EOC
= 1 (BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
fi rst rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the fi rst rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna-
tively, BUSY (Pin 15) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the low power sleep state, CS must
be pulled HIGH before the fi rst rising edge of SCK. In the
internal SCK timing mode, SCK goes HIGH and the device
begins outputting data at time tEOCtest after the falling edge
of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is
LOW during the falling edge of EOC). The value of tEOCtest
is 500ns. If CS is pulled HIGH before time tEOCtest, the
device remains in the sleep state. The conversion result
is held in the internal static shift register.
If CS remains LOW longer than tEOCtest, the fi rst rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
SDO
BUSY
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB24
BIT 5 TEST EOC
BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSIONCONVERSION
2440 F08
<tEOCtest
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
413
5
6
12
1, 8, 9, 16
11
10 VCC
15
SDI 7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
LTC2440
18
2440fd
APPLICATIONS INFORMATION
on this fi rst rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the fi rst and 32nd rising
edge of SCK, see Figure 9. In order to properly select the
OSR for the conversion following a data abort, fi ve SCK
rising edges must be seen prior to performing a data out
abort (pulling CS HIGH). If CS is pulled high prior to the
fi fth SCK falling edge, the OSR selected depends on the
number of SCK signals seen prior to data abort, where
subsequent nonaborted conversion cycles return to the
programmed OSR. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
Figure 9. Internal Serial Clock, Reduced Data Output Length
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW (EOC
= 0) indicating the conversion has fi nished and the device
has entered the low power sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the fi rst rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
SDO
BUSY
SCK
(INTERNAL)
CS
>tEOCtest
MSBSIG
BIT 8
TEST EOCTEST EOC BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP DATA OUTPUT
Hi-Z Hi-Z
51
Hi-Z Hi-Z Hi-Z
DATA OUTPUT
CONVERSIONCONVERSIONSLEEP
2440 F09
<tEOCtest
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
413
5
6
12
1, 8, 9, 16
11
10
15
SDI
VCC
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
LTC2440
19
2440fd
APPLICATIONS INFORMATION
Figure 10. Internal Serial Clock, Continuous Operation
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital fi ltering. Combined
with a large oversampling ratio, the LTC2440 signifi cantly
simplifi es antialiasing fi lter requirements.
The LTC2440’s speed/resolution is determined by the
over sample ratio (OSR) of the on-chip digital fi lter. The
OSR ranges from 64 for 3.5kHz output rate to 32,768
for 6.9Hz output rate. The value of OSR and the sample
rate fS determine the fi lter characteristics of the device.
The fi rst NULL of the digital fi lter is at fN and multiples
of fN where fN = fS/OSR, see Figure 11 and Table 5. The
rejection at the frequency fN ±14% is better than 80dB,
see Figure 12.
If fO is grounded, fS is set by the on-chip oscillator at
1.8MHz ±5% (over supply and temperature variations). At
an OSR of 32,768, the fi rst NULL is at fN = 55Hz and the
no latency output rate is fN/8 = 6.9Hz. At the maximum
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
SDO
BUSY
SCK
(INTERNAL)
CS
LSB24
MSBSIG
BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2410 F10
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
413
5
6
12
1, 8, 9, 16
11
10
15
SDI
VCC
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
2-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
2440 F11
–80
–100
60 120 240
–120
–140
–20
NORMAL MODE REJECTION (dB)
LTC2440
20
2440fd
APPLICATIONS INFORMATION
OSR, the noise performance of the device is 200nVRMS with
better than 80dB rejection of 50Hz ±2% and 60Hz ±2%.
Since the OSR is large (32,768) the wide band rejection
is extremely large and the antialiasing requirements are
simple. The fi rst multiple of fS occurs at 55Hz • 32,768 =
1.8MHz, see Figure 13.
The fi rst NULL becomes fN = 7.04kHz with an OSR of 256
(an output rate of 880Hz) and fO grounded. While the NULL
has shifted, the sample rate remains constant. As a result
of constant modulator sampling rate, the linearity, offset
and full-scale performance remains unchanged as does
the fi rst multiple of fS.
Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator) Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
47
–140
NORMAL MODE REJECTION (dB)
–130
–120
–110
–100
51 55 59 63
2440 F12
–90
–80
49 53 57 61
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
1440 F13
–80
–100
1000000 2000000
–120
1.8MHz
–140
–20
NORMAL MODE REJECTION (dB)
REJECTION > 120dB
Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator
Running at 9MHz
OSR NOTCH (fN)
64 28.16kHz
128 14.08kHz
256 7.04kHz
512 3.52kHz
1024 1.76kHz
2048 880Hz
4096 440Hz
8192 220Hz
16384 110Hz
32768* 55Hz
*Simultaneous 50/60 rejection
LTC2440
21
2440fd
APPLICATIONS INFORMATION
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
The sample rate fS and NULL fN, my also be adjusted by
driving the fO pin with an external oscillator. The sample
rate is fS = fEOSC /5, where fEOSC is the frequency of the
clock applied to fO. Combining a large OSR with a reduced
sample rate leads to notch frequencies fN near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to fO results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz fi lter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz can
be implemented using the LTC1799 (resistor set SOT-23
oscillator), see Figure 22. By fl oating pin 4 (DIV) of the
LTC1799, the output oscillator frequency is:
f MHz k
R
OSC SET
=⎛
⎝
⎜⎞
⎠
⎟
10 10
10
••
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with RSET = 100k) to the fO pin on the LTC2440 with SDI
tied HIGH (OSR = 32768).
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8μA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
For example, if the OSR is programmed at the fastest rate
(OSR = 64, tCONV = 0.285ms) and the sleep state is 10ms,
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240μA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30μA. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/Speed)
and sleep mode duration (Power).
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
246 10
–100
–120
–140
NORMAL MODE REJECTION (dB)
LTC2440
22
2440fd
APPLICATIONS INFORMATION
LTC2440 Input Structure
Modern delta sigma converters have switched capacitor
front ends that repeatedly sample the input voltage over
some time period. The sampling process produces a small
current pulse at the input and reference terminals as the
capacitors are charged. The LTC2440 switches the input
and reference to a 5pF sample capacitor at a frequency
of 1.8MHz. A simplifi ed equivalent circuit is shown in
Figure 16.
The average input and reference currents can be expressed
in terms of the equivalent input resistance of the sample
capacitor, where:
Req = 1/(fSW • Ceq)
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
Driving the Input and Reference
Because of the small current pulses, excessive lead length
at the analog or reference input may allow refl ections or
ringing to occur, affecting the conversion accuracy. The
key to preserving the accuracy of the LTC2440 is complete
settling of these sampling glitches at both the input and
reference terminals. There are several recommended
methods of doing this.
Figure 15. Reduced Power Timing Mode
Figure 16. LTC2440 Input Structure
SLEEP CONVERT SLEEP CONVERT SLEEP
8mA
2440 F15
8μA8μA8mA8μA
DATA
OUT
DATA
OUT
CONVERTER
STATE
SUPPLY
CURRENT
CS
VREF+
VIN+
VCC
RSW (TYP)
500Ω
ILEAK
ILEAK
VCC
ILEAK
ILEAK
VCC
RSW (TYP)
500Ω
CEQ
5pF
(TYP)
(CEQ = 3.5pF SAMPLE CAP + PARASITICS)
RSW (TYP)
500Ω
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2440 F16
ILEAK
VCC
ILEAK
ILEAK
SWITCHING FREQUENCY
fSW = 1.8MHz INTERNAL OSCILLATOR
fSW = fEOSC/5 EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
500Ω
LTC2440
23
2440fd
APPLICATIONS INFORMATION
Figure 18. Input Capacitors Allow Longer Connection
Between the Low Impedance Source and the ADC.
Direct Connection to Low Impedance Sources
If the ADC can be located physically close to the sensor,
it can be directly connected to sensors or other sources
with impedances up to 350Ω with no other components
required (see Figure 17).
Longer Connections to Low Impedance Sources
If longer lead lengths are unavoidable, adding an input
capacitor close to the ADC input pins will average the
charging pulses and prevent refl ections or ringing (see
Figure 18). Averaging the current pulses results in a DC
input current that should be taken into account. The re-
sulting 110kΩ input impedance will result in a gain error
of 0.44% for a 350Ω bridge (within the full scale specs
of many bridges) and a very low 12.6ppm error for a 2Ω
thermocouple connection.
Buffering the LTC2440
Many applications will require buffering, particularly
where high impedance sources are involved or where the
device being measured is located some distance from the
LTC2440. When buffering the LTC2440 a few simple steps
should be followed.
Figure 19 shows a network suitable for coupling the inputs
of a LTC2440 to a LTC2051 chopper-stabilized op amp. The
3μV offset and low noise of the LTC2051 make it a good
choice for buffering the LTC2440. Many other op amps
will work, with varying performance characteristics.
The LTC2051 is confi gured to be able to drive the 1μF ca-
pacitors at the inputs of the LTC2440. The 1μF capacitors
should be located close to the ADC input pins.
The measured total unadjusted error of Figure 19 is well
within the specifi cations of the LTC2440 by itself. Most
autozero amplifi ers will degrade the overall resolution to
some degree because of the extremely low input noise
of the LTC2440, however the LTC2051 is a good general
purpose buffer. The measured input referred noise of two
LTC2051s buffering both LTC2440 inputs is approximately
double that of the LTC2440 by itself, which reduces the ef-
fective resolution by 1-bit for all oversample ratios. Adding
gain to the LTC2051 will increase gain and offset errors
and will not appreciably increase the overall resolution,
so it has limited benefi t.
Procedure For Coupling Any Amplifi er to the LTC2440
The LTC2051 is suitable for a wide range of DC and low
frequency measurement applications. If another ampli-
fi er is to be selected, a general procedure for evaluating
the suitability of an amplifi er for use with the LTC2440 is
suggested here:
1. Perform a thorough error and noise analysis on the
amplifi er and gain setting components to verify that the
amplifi er will perform as intended.
2. Measure the large signal response of the overall circuit.
The capacitive load may affect the maximum slew rate of
the amplifi er. Verify that the slew rate is adequate for the
Figure 17. Direct Connection to Low Impedance (<350Ω) Source
is Possible if the Sensor is Located Close to the ADC.
2440 F17
REF+
REF–
IN+
IN–
LTC2440
1μF
4.5V to 5.5V
2440 F18
1μF
4.5V to 5.5V
REMOTE
THERMOCOUPLE
VREF+VCC
GND
IN+
IN–
LTC2440
1μF
1μF
LTC2440
24
2440fd
APPLICATIONS INFORMATION
fastest expected input signal. Figure 20 shows the large
signal response of the circuit in Figure 19.
3. Measure noise performance of the complete circuit. A
good technique is to build one amplifi er for each input,
even if only one will be used in the end application. Bias
both amplifi er outputs to midscale, with the inputs tied
together. Verify that the noise is as expected, taking into
account the bandwidth of the LTC2440 inputs for the OSR
being used, the amplifi er’s broadband voltage noise and
1/f corner (if any) and any additional noise due to the
amplifi er’s current noise and source resistance.
For more information on testing high linearity ADCs, refer
to Linear Technology Design Solutions 11.
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC4 digital fi lter and
the digital and analog autocalibration circuits determines
the LTC2440 input bandwidth and rejection characteristics.
The digital fi lter’s response can be adjusted by setting the
oversample ratio (OSR) through the SPI interface or by
supplying an external conversion clock to the fO pin.
Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Amplifi er
Figure 20. Large Signal Input Settling Time Indicates
Completed Settling with Selected Load Capacitance.
Figure 21. Dynamic Input Current is Attenuated by Load
Capacitance and Completely Settled Before the Next Conversion
Sample Resulting in No Reduction in Performance.
VCC
fO
REF+
REF–SCK
BUSY
IN+
IN–
SDO
CS
EXT
0.1μF413
5
6
12
1, 8, 9, 16
11
10
15
SDI 7
5V
10μF0.01μF
LTC2440
2440 F19
14
10Ω
IN+
5k
C2
C2, C5 TAIYO YUDEN JMK107BJ105MA
4.7μF
8-12V
LT1236-5
1μF
C1 R1
R2
R4
R5
0.01μF
1/2 LTC2051HV
C5
1μF
10Ω
IN–
5k
C4
0.01μF
1/2 LTC2051HV
+
–
+
–
2440 F20
100μs/DIV
100mV/DIV
2440 F21
5ns/DIV
2mV/DIV
LTC2440
25
2440fd
APPLICATIONS INFORMATION
Table 6 lists the properties of the LTC2440 with various
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fi ne tuning
the characteristics of the LTC2440 to the application.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
This is the fi rst notch in the SINC4 portion of the digital fi lter
and depends on the fo clock frequency and the oversample
ratio. Rejection at this frequency and its multiples (up to
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Effective Noise Bandwidth
The LTC2440 has extremely good input noise rejection from
the fi rst notch frequency all the way out to the modulator
sample rate (typically 1.8MHz). Effective noise bandwidth
is a measure of how the ADC will reject wideband input
noise up to the modulator sample rate. The example on
the following page shows how the noise rejection of the
LTC2440 reduces the effective noise of an amplifi er driv-
ing its input.
Table 6
Oversample
Ratio
(OSR)
ADC
Noise*
ENOB
(VREF = 5V)*
Maximum Conversion Rate First Notch Frequency Effective Noise BW –3dB Point (Hz)
Internal
9MHz clock
External
fO
Internal
9MHz clock
External
fO
Internal
9MHz clock
External
fO
Internal
9MHz clock
External
fO
64 23μV 17 3515.6 fO/2560 28125 fO/320 3148 fO/2850 1696 fO/5310
128 3.5μV 20 1757.8 fO/5120 14062.5 fO/640 1574 fO/5700 848 fO/10600
256 2μV 21.3 878.9 fO/10240 7031.3 fO/1280 787 fO/11400 424 fO/21200
512 1.4μV 21.8 439.5 fO/20480 3515.6 fO/2560 394 fO/22800 212 fO/42500
1024 1μV 22.4 219.7 fO/40960 1757.8 fO/5120 197 fO/45700 106 fO/84900
2048 750nV 22.9 109.9 fO/81920 878.9 fO/1020 98.4 fO/91400 53 fO/170000
4096 510nV 23.4 54.9 fO/163840 439.5 fO/2050 49.2 fO/183000 26.5 fO/340000
8192 375nV 24 27.5 fO/327680 219.7 fO/4100 24.6 fO/366000 13.2 fO/679000
16384 250nV 24.4 13.7 fO/655360 109.9 fO/8190 12.4 fO/731000 6.6 fO/1358000
32768 200nV 24.6 6.9 fO/1310720 54.9 fO/16380 6.2 fO/1463000 3.3 fO/2717000
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64
include effects from internal modulator quantization noise.
LTC2440
26
2440fd
Example:
If an amplifi er (e.g. LT1219) driving the input of an LTC2440
has wideband noise of 33nV/√Hz, band-limited to 1.8MHz,
the total noise entering the ADC input is:
33nV/√Hz • √1.8MHz = 44.3μV.
When the ADC digitizes the input, its digital fi lter fi lters
out the wideband noise from the input signal. The noise
reduction depends on the oversample ratio which defi nes
the effective bandwidth of the digital fi lter.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifi er noise to:
33nV/√Hz • √787Hz = 0.93μV.
The total noise is the RMS sum of this noise with the 2μV
noise of the ADC at OSR=256.
√0.93μ/V2 + 2μV2 = 2.2μV.
Increasing the oversampling ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifi er noise to:
33nV/√Hz • √6.2Hz = 82nV.
The total noise is the RMS sum of this noise with the
200nV noise of the ADC at OSR = 32768.
√82nV2 + 2μV2 = 216nV.
In this way, the digital fi lter with its variable oversampling
ratio can greatly reduce the effects of external noise
sources.
Using Non-Autozeroed Amplifi ers for Lowest Noise
Applications
Ultralow noise applications may require the use of low
noise bipolar amplifi ers that are not autozeroed. Because
the LTC2440 has such exceptionally low offset, offset drift
and 1/f noise, the offset drift and 1/f noise in the ampli-
fi ers may need to be compensated for to retain the system
performance of which the ADC is capable.
The circuit of Figure 23 uses low noise bipolar amplifi ers
and correlated double sampling to achieve a resolution of
14nV, or 19 effective bits over a 10mV span. Each measure-
ment is the difference between two ADC readings taken
with opposite polarity bridge excitation. This cancels 1/f
noise below 3.4Hz and eliminates errors due to parasitic
thermocouples. Allow 750μs settling time after switching
excitation polarity.
APPLICATIONS INFORMATION
LTC2440
27
2440fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
TYPICAL APPLICATIONS
Figure 22. Simple External Clock Source
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
VCC
fO
REF+
REF–SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
4
51
2
3
0.1μF
RSET
4
NC
50Ω
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
7
VCC
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
V+
GND
OUT
DIV SET 2440 TA05
LTC1799
3-WIRE
SPI INTERFACE
LTC2440
28
2440fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
LT 1008 REV D • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1025 Micropower Thermocouple Cold Junction Compensator 80μA Supply Current, 0.5°C Initial Accuracy
LTC1043 Dual Precision Instrumentation Switched Capacitor
Building Block Precise Charge, Balanced Switching, Low Power
LTC1050 Precision Chopper Stabilized Op Amp No External Components 5μV Offset, 1.6μVP-P Noise
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift
LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/°C Max Drift
LTC1592 Ultraprecise 16-Bit SoftSpanTM DAC Six Programmable Output Ranges
LTC1655 16-Bit Rail-to-Rail Micropower DAC ±1LSB DNL, 600μA, Internal Reference, SO-8
LTC1799 Resistor Set SOT-23 Oscillator Single Resistor Frequency Set
LTC2053 Rail-to-Rail Instrumentation Amplifi er 10μV Offset with 50nV/°C Drift, 2.5μVP-P Noise 0.01Hz to 10Hz
LTC2400 24-Bit, No Latency Δ∑ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency Δ∑ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency Δ∑ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410/LTC2413 24-Bit, No Latency Δ∑ ADC 800nVRMS Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection
LTC2411 24-Bit, No Latency Δ∑ ADC in MSOP 1.45μVRMS Noise, 6ppm INL
LTC2420LTC2424/
LTC2428 1-/4-/8-Channel, 20-Bit, No Latency Δ∑ ADCs 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/
LTC2404/LTC2408
SoftSpan is a trademark of Linear Technology Corporation.
Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-Autozeroed,
Bipolar Amplifi er. Circuit Gives 14nV Noise Level or 19 Effective Bits over a 10mV Span
REF+
REF–
IN+
IN–
VREF
0.1μF10μF
4
LTC2440
2440 F22
+7V
LT1461-5
1k 0.1%
10Ω
100Ω 0.1%
0.047μF
1μF
1k 0.1%
10Ω
0.047μF
1μF
+
–
–
+
2X LT1677
2X SILICONIX SI9801
5,6,7,8
100k
100k
TOP_N
TOP_P
VREF
1
3
2
5,6,7,8
4
100k
100k
BOTTOM_N
BOTTOM_P
VREF
1
3
2
4
