PD - 97047B IRFB3077PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Worldwide Best RDS(on) in TO-220 l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability HEXFET(R) Power MOSFET D G S VDSS RDS(on) typ. max. ID (Silicon Limited) 75V 2.8m: 3.3m: 210A c ID (Package Limited) 120A D G D S TO-220AB IRFB3077PbF G D S G ate Drain Source Absolute Maximum Ratings Max. Units ID @ TC = 25C Symbol Continuous Drain Current, VGS @ 10V (Silicon Limited) Parameter 210c A ID @ TC = 100C Continuous Drain Current, VGS @ 10V (Silicon Limited) 150c ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 120 IDM Pulsed Drain Current d 850 PD @TC = 25C Maximum Power Dissipation 370 W W/C V Linear Derating Factor 2.5 VGS Gate-to-Source Voltage 20 dV/dt TJ Peak Diode Recovery f 2.5 Operating Junction and -55 to + 175 TSTG Storage Temperature Range V/ns C 300 Soldering Temperature, for 10 seconds (1.6mm from case) 10lbxin (1.1Nxm) Mounting torque, 6-32 or M3 screw Avalanche Characteristics EAS (Thermally limited) Single Pulse Avalanche Energy e IAR Avalanche Current d EAR Repetitive Avalanche Energy g 200 mJ See Fig. 14, 15, 22a, 22b, A mJ Thermal Resistance Typ. Max. RJC Symbol Junction-to-Case k --- 0.402 RCS Case-to-Sink, Flat Greased Surface 0.50 --- RJA Junction-to-Ambient jk --- 62 www.irf.com Parameter Units C/W 1 5/2/11 IRFB3077PbF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance Min. Typ. Max. Units V Conditions 75 --- --- --- 0.091 --- V/C Reference to 25C, ID = 5mAd VGS = 0V, ID = 250A --- 2.8 3.3 m VGS = 10V, ID = 75A g VGS(th) Gate Threshold Voltage 2.0 --- 4.0 V VDS = VGS, ID = 250A IDSS Drain-to-Source Leakage Current --- --- 20 A VDS = 75V, VGS = 0V --- --- 250 IGSS Gate-to-Source Forward Leakage --- --- 100 Gate-to-Source Reverse Leakage --- --- -100 Gate Input Resistance --- 1.2 --- RG VDS = 75V, VGS = 0V, TJ = 125C nA VGS = 20V f = 1MHz, open drain VGS = -20V Dynamic @ TJ = 25C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Qg Forward Transconductance 160 --- --- S Total Gate Charge --- 160 220 nC Qgs Gate-to-Source Charge --- 37 --- VDS = 38V Qgd Gate-to-Drain ("Miller") Charge --- 42 --- VGS = 10V g td(on) Turn-On Delay Time --- 25 --- tr Rise Time --- 87 --- td(off) Turn-Off Delay Time --- 69 --- RG = 2.1 tf Fall Time --- 95 --- VGS = 10V g Ciss Input Capacitance --- 9400 --- Coss Output Capacitance --- 820 --- VDS = 50V Crss Reverse Transfer Capacitance --- 350 --- = 1.0MHz Coss eff. (ER) Effective Output Capacitance (Energy Related)i --- Coss eff. (TR) Effective Output Capacitance (Time Related)h --- 1090 --- VGS = 0V, VDS = 0V to 60V j, See Fig.11 1260 --- VGS = 0V, VDS = 0V to 60V h, See Fig. 5 ns VDS = 50V, ID = 75A ID = 75A VDD = 38V ID = 75A pF VGS = 0V Diode Characteristics Symbol Parameter Min. Typ. Max. Units IS Continuous Source Current --- --- 210c ISM (Body Diode) Pulsed Source Current --- --- VSD (Body Diode)di Diode Forward Voltage --- --- 1.3 V trr Reverse Recovery Time --- 42 63 ns --- 50 75 Qrr Reverse Recovery Charge --- 59 89 --- 86 130 IRRM Reverse Recovery Current --- 2.5 --- ton Forward Turn-On Time Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.028mH RG = 25, IAS = 120A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 400A/s, VDD V(BR)DSS, TJ 175C. 2 A Conditions MOSFET symbol showing the integral reverse 850 G p-n junction diode. TJ = 25C, IS = 75A, VGS = 0V g VR = 64V, TJ = 25C TJ = 125C nC D TJ = 25C S IF = 75A di/dt = 100A/s g TJ = 125C A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ approximately 90C www.irf.com IRFB3077PbF 1000 1000 BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 4.5V BOTTOM 4.5V 100 60s PULSE WIDTH Tj = 175C 60s PULSE WIDTH Tj = 25C 10 10 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 100 Fig 2. Typical Output Characteristics 1000 2.5 100 TJ = 25C VDS = 25V 60s PULSE WIDTH 1 2.0 3.0 4.0 5.0 VGS = 10V 2.0 (Normalized) TJ = 175C 10 ID = 75A RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current() 10 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 6.0 7.0 1.5 1.0 0.5 8.0 -60 -40 -20 VGS, Gate-to-Source Voltage (V) 16000 VGS, Gate-to-Source Voltage (V) Coss = Cds + Cgd Ciss 8000 4000 Coss Crss 10 100 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com ID= 75A VDS = 60V 16 VDS= 38V VDS= 17V 12 8 4 0 0 1 20 40 60 80 100 120 140 160 180 Fig 4. Normalized On-Resistance vs. Temperature 20 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 12000 0 TJ , Junction Temperature (C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) 1 0 40 80 120 160 200 240 280 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFB3077PbF 10000 ID, Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 1000.0 TJ = 175C 100.0 10.0 TJ = 25C 1.0 OPERATION IN THIS AREA LIMITED BY R DS (on) 1000 1msec 10msec LIMITED BY PACKAGE 10 1 0.1 0.0 0.4 0.8 1.2 1.6 0.1 2.0 LIMITED BY PACKAGE ID, Drain Current (A) 200 160 120 80 40 0 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage 240 50 10 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 1 VDS , Drain-toSource Voltage (V) VSD , Source-to-Drain Voltage (V) 100 90 80 70 -60 -40 -20 TC, Case Temperature (C) 0 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage 3.0 EAS, Single Pulse Avalanche Energy (mJ) 1000 2.5 2.0 Energy (J) DC Tc = 25C Tj = 175C Single Pulse VGS = 0V 0.1 1.5 1.0 0.5 0.0 ID 22A 40A BOTTOM 120A TOP 800 600 400 200 0 0 20 40 60 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 100sec 100 80 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (C) Fig 12. Maximum Avalanche Energy Vs. DrainCurrent www.irf.com IRFB3077PbF 1 Thermal Response ( Z thJC ) D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 J J 1 R2 R2 2 1 2 R3 R3 3 C 3 Ci= i/Ri Ci i/Ri SINGLE PULSE ( THERMAL RESPONSE ) 0.001 R1 R1 Ri (C/W) i (sec) 0.0766 0.000083 0.1743 0.000995 0.1513 0.007038 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 100 0.01 0.05 0.10 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 240 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 120A 200 160 120 80 40 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFB3077PbF 24 ID = 1.0A ID = 1.0mA ID = 250A 20 3.0 16 IRRM - (A) VGS(th) Gate threshold Voltage (V) 4.0 2.0 12 8 IF = 30A VR = 64V 4 1.0 -75 -50 -25 0 25 50 75 TJ = 125C TJ = 25C 0 100 125 150 175 100 200 300 400 500 600 700 800 900 1000 TJ , Temperature ( C ) dif / dt - (A / s) Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt 24 400 20 300 QRR - (nC) IRRM - (A) 16 12 8 4 IF = 45A VR = 64V 200 IF = 30A VR = 64V 100 TJ = 125C TJ = 25C TJ = 125C TJ = 25C 0 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / s) dif / dt - (A / s) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt 400 QRR - (nC) 300 200 100 0 IF = 45A VR = 64V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFB3077PbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG + V - DD IAS VGS 20V tp A 0.01 I AS Fig 22a. Unclamped Inductive Test Circuit LD Fig 22b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1s Duty Factor < 0.1% td(on) Fig 23a. Switching Time Test Circuit tr td(off) tf Fig 23b. Switching Time Waveforms Id Vds Vgs L DUT 0 VCC Vgs(th) 1K Qgs1 Qgs2 Fig 24a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRFB3077PbF TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB Part Marking Information E XAMPL E : T HIS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" Note: "P" in assembly line position indicates "Lead-Free" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. 8 IR WORLD HEADQUARTERS: 101N. Sepulveda, El Segundo, California 90245, USA Tel: (310) 2527105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 05/2011 www.irf.com