IRFB3077PBF - INTERNATIONAL RECTIFIER

5/2/11

Benefits

lWorldwide Best RDS(on) in TO-220

lImproved Gate, Avalanche and Dynamic dV/dt

Ruggedness

lFully Characterized Capacitance and Avalanche

SOA

lEnhanced body diode dV/dt and dI/dt Capability

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IRFB3077PbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS

l Uninterruptible Power Supply

l High Speed Power Switching

l Hard Switched and High Frequency Circuits

TO-220AB

IRFB3077PbF

GDS

Gate Drain Source

VDSS 75V

RDS

(

)

typ. 2.8m:

max. 3.3m:

ID (Silicon Limited) 210A c

ID (Package Limited) 120A

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited

)

IDM Pulsed Drain Current d

PD @TC = 25°C Maximum Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

dV/dt Peak Diode Recovery fV/ns

TJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

Avalanche Characteristics

EAS (Thermally limited) Single Pulse Avalanche Energy emJ

IAR Avalanche Current dA

EAR Repetitive Avalanche Energy gmJ

Thermal Resistance

Symbol Parameter Typ. Max. Units

RθJC Junction-to-Case k––– 0.402

RθCS Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W

RθJA Junction-to-Ambient jk ––– 62

200

See Fig. 14, 15, 22a, 22b,

370

2.5

-55 to + 175

± 20

2.5

10lbxin (1.1Nxm)

300

Max.

210c

120

850

150c

PD - 97047B

IRFB3077PbF

2www.irf.com

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 120A. Note that current

limitations arising from heating of the device leads may occur with

some lead mounting arrangements.

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by TJmax, starting TJ = 25°C, L = 0.028mH

RG = 25Ω, IAS = 120A, VGS =10V. Part not recommended for use

above this value.

ISD ≤ 75A, di/dt ≤ 400A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

 Coss eff. (TR) is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS.

 Coss eff. (ER) is a fixed capacitance that gives the same energy as

Coss while VDS is rising from 0 to 80% VDSS.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 Rθ is measured at TJ approximately 90°C

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V

ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.091 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 2.8 3.3 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

IDSS Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

RGGate Input Resistance ––– 1.2 ––– Ωf = 1MHz, open drain

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 160 ––– ––– S

QgTotal Gate Charge ––– 160 220 nC

Qgs Gate-to-Source Charge ––– 37 –––

Qgd Gate-to-Drain ("Miller") Charge ––– 42 –––

td(on) Turn-On Delay Time ––– 25 ––– ns

trRise Time ––– 87 –––

td(off) Turn-Off Delay Time ––– 69 –––

tfFall Time ––– 95 –––

Ciss Input Capacitance ––– 9400 ––– pF

Coss Output Capacitance ––– 820 –––

Crss Reverse Transfer Capacitance ––– 350 –––

Coss eff. (ER) Effective Output Capacitance (Energy Related)

––– 1090 –––

Coss eff. (TR) Effective Output Capacitance (Time Related)h––– 1260 –––

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 210cA

(Body Diode)

ISM Pulsed Source Current ––– ––– 850

(Body Diode)di

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time ––– 42 63 ns TJ = 25°C VR = 64V,

––– 50 75 TJ = 125°C IF = 75A

Qrr Reverse Recovery Charge ––– 59 89 nC TJ = 25°C di/dt = 100A/μs g

––– 86 130 TJ = 125°C

IRRM Reverse Recovery Current ––– 2.5 ––– A TJ = 25°C

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

ID = 75A

RG = 2.1Ω

VGS = 10V g

VDD = 38V

TJ = 25°C, IS = 75A, VGS = 0V g

integral reverse

p-n junction diode.

Conditions

VGS = 0V, ID = 250μA

Reference to 25°C, ID = 5mAd

VGS = 10V, ID = 75A g

VDS = VGS, ID = 250μA

VDS = 75V, VGS = 0V

VDS = 75V, VGS = 0V, TJ = 125°C

MOSFET symbol

showing the

VDS = 38V

Conditions

VGS = 10V g

VGS = 0V

VDS = 50V

ƒ = 1.0MHz

VGS = 0V, VDS = 0V to 60V j, See Fig.11

VGS = 0V, VDS = 0V to 60V h, See Fig. 5

Conditions

VDS = 50V, ID = 75A

ID = 75A

VGS = 20V

VGS = -20V

IRFB3077PbF

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Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

Fig 2. Typical Output Characteristics

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60μs PULSE WIDTH

Tj = 25°C

4.5V

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60μs PULSE WIDTH

Tj = 175°C

4.5V

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current

(Α)

VDS = 25V

≤ 60μs PULSE WIDTH

TJ = 25°C

TJ = 175°C

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 75A

VGS = 10V

110 100

VDS, Drain-to-Source Voltage (V)

4000

8000

12000

16000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 40 80 120 160 200 240 280

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 60V

VDS= 38V

VDS= 17V

ID= 75A

IRFB3077PbF

4www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 10. Drain-to-Source Breakdown Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

Fig 11. Typical COSS Stored Energy

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

0.0 0.4 0.8 1.2 1.6 2.0

VSD, Source-to-Drain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

100

V(BR)DSS , Drain-to-Source Breakdown Voltage

020 40 60 80

VDS, Drain-to-Source Voltage (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Energy (μJ)

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

200

400

600

800

1000

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 22A

40A

BOTTOM 120A

25 50 75 100 125 150 175

TC, Case Temperature (°C)

120

160

200

240

ID, Drain Current (A)

LIMITED BY PACKAGE

0.1 1 10 100

VDS, Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100μsec

LIMITED BY PACKAGE

IRFB3077PbF

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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 14. Typical Avalanche Current vs.Pulsewidth

Fig 15. Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. PD (ave) = Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. Iav = Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as

25°C in Figure 14, 15).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

Thermal Response ( Z

thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.0766 0.000083

0.1743 0.000995

0.1513 0.007038

τJ

τ1

τ2

τ2τ3

τ3

R1R2

R2R3

τC

Ci τi/Ri

Ci= τi/Ri

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

120

160

200

240

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 120A

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔΤ j = 25°C and

Tstart = 150°C.

0.01

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

IRFB3077PbF

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Fig. 17 - Typical Recovery Current vs. dif/dt

Fig 16. Threshold Voltage Vs. Temperature

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

Fig. 20 - Typical Stored Charge vs. dif/dt

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

2.0

3.0

4.0

VGS(th) Gate threshold Voltage (V)

ID = 1.0A

ID = 1.0mA

ID = 250μA

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IRRM - (A)

IF = 45A

VR = 64V

TJ = 125°C

TJ = 25°C

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IRRM - (A)

IF = 30A

VR = 64V

TJ = 125°C

TJ = 25°C

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

100

200

300

400

QRR - (nC)

IF = 30A

VR = 64V

TJ = 125°C

TJ = 25°C

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

100

200

300

400

QRR - (nC)

IF = 45A

VR = 64V

TJ = 125°C

TJ = 25°C

IRFB3077PbF

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Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms

VGS

VDS

90%

10%

td(on) td(off)

trtf

VGS

Pulse Width < 1μs

Duty Factor < 0.1%

VDD

VDS

D.U.T

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

(BR)DSS

0.01

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

VCC

DUT

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



Inductor Current

IRFB3077PbF

8www.irf.com

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 101N. Sepulveda, El Segundo, California 90245, USA Tel: (310) 252-

7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 05/2011

TO-220AB packages are not recommended for Surface Mount Application.

TO-220AB Package Outline (Dimensions are shown in millimeters (inches))

TO-220AB Part Marking Information

EXAMPLE:

IN THE ASS EMBLY LINE "C"

T HIS IS AN IRF 1010

LOT CODE 1789

AS S E MB LE D ON WW 19, 1997 PART NUMBER

ASSEMBLY

LOT CODE

DAT E CODE

YEAR 7 = 1997

LINE C

WE E K 19

LOGO

R E CT IF IE R

INT E R NAT IONAL

Note: "P" in assembly line

position indicates "Lead-Free"

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/