7-203
7
VN2222
VN2224
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FET s are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
N-Channel Enhancement-Mode
Vertical DMOS FETs
Package Options
Ordering Information
Absolute Maximum Ratings
Drain-to-Source Voltage BVDSS
Drain-to-Gate Voltage BVDGS
Gate-to-Source Voltage ± 20V
Operating and Storage Temperature -55°C to +150°C
Soldering Temperature* 300°C
* Distance of 1.6 mm from case for 10 seconds.
Order Number / Package
BVDSS /R
DS(ON) ID(ON)
BVDGS (max) (min) TO-92 20-Pin C-Dip
220V 1.25Ω5.0A – VN2222NC
240V 1.25Ω5.0A VN2224N3 –
Applications
■■Motor controls
■■Converters
■■Amplifiers
■■Switches
■■Power supply circuits
■■Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Features
■■Free from secondary breakdown
■■Low power drive requirement
■■Ease of paralleling
■■Low CISS and fast switching speeds
■■Excellent thermal stability
■■Integral Source-Drain diode
■■High input impedance and high gain
High Reliability Devices
See pages 5-4 and 5-5 for MILITARY STANDARD Process
Flows and Ordering Information.
Note: See Package Outline section for dimensions.
1
10
2
3
4
5
6
7
8
9
20
11
19
18
17
16
15
14
13
12
top view
SS
SS
SNC
G1 D1
G2 D2
G3 D3
G4 D4
SNC
SS
SS
S G D
20-pin Ceramic DIP