Si840x
Rev. 1.6 19
Not Recommended
for New Designs
4.3. I2C Isolator Design Constraints
Table 13 lists the design constraints.
4.4. I2C Isolator Design Considerations
The first step in applying an I2C isolator is to choose which side of the bus will be connected to the isolator A side.
Ideally, it should be the side which:
1. Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8400/01/02/05
isolators are normally used with a pull up of 0.5 mA to 3 mA.
2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and
other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
3. Have devices on the bus that can pull down below the isolator input low level. For example, the Si840x input
level is 0.45 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
The Si840x isolators are not compatible with devices that have a logic low of 0.8 V. For this situation, a discrete
circuit can be used. See “AN352: Low-Cost, High-Speed I2C Isolation with Digital Isolators” for additional
information.
Table 13. Design Constraints
Design Cons tra int Data Sheet Value s Effect of Bus Pu ll-up Strength
and Temperature
To prevent the latch condition, the
isolator output low level must be
greater than the isolator input low
level.
Isolator VOL 0.8 V typical
Isolator VIL 0.6 V typical
Input/Output Logic Low Level
Difference
∆VSDA1, ∆VSCL1 = 50 mV minimum
This is normally guaranteed by the
isolator data sheet. However, if the
pull up strength is too weak, the out-
put low voltage will fall and can get
too close to the input low logic level.
These track over temperature.
The bus output low must be less
than the isolator input low logic
level.
Bus VOL =0.4V maximum
Isolator VIL = 0.45 V minimum
If the pull up strength is too large,
the devices on the bus might not pull
the voltage below the input low
range. These have opposite tem-
perature coefficients. Worst case is
hot temperature.
The isolator output low must be
less than the bus input low.
Bus VIL 0.3 x VDD = 1.0 V minimum for
VDD =3.3V
Isolator VOL = 0.825 V maximum,
(0.5 mA pullup, –10 to 125 °C)
If the pull up strength is too large,
the isolator might not pull below the
bus input low voltage.
Si8400/01/05 Vol: –1.8 mV/C
CMOS buffer: –0.6 mV/C
This provides some temperature
tracking, but worst case is cold tem-
perature.