Rev: 1.01 11/2000 1/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS815218/36/72B-225/200/180/166/150/133
1M x 18, 512K x 36, 256K x 72
16Mb S/DCD Sync Burst SRAMs
200 MHz–133MHz
3.3 V VDD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• On-chip parity encoding and error detection
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
Functional Description
Applications
The GS815218/36/72B is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS815218/36/72B is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
ByteSafe™ Parity Functions
The GS815218/36/72B features ByteSafe data security functions.
See the detailed discussion following.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS815218/36/72B operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V- and 2.5 V-compatible.
-225 -200 -180 -166 -150 -133 Unit
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
7.0
8.5
205
240
325
7.5
10.0
185
210
285
8.0
10.0
185
210
285
8.5
10.0
185
210
285
10.0
10.0
185
210
285
11.0
15.0
140
160
205
ns
ns
mA
mA
mA
Pipeline
3-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
2.5
4.4
350
410
570
3.0
5.0
315
370
515
3.2
5.5
290
340
470
3.5
6.0
270
315
435
3.8
6.7
250
290
400
4.0
7.5
230
260
360
ns
ns
mA
mA
mA
Rev: 1.01 11/2000 2/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815272 Pad Out
209 Bump BGA—Top View
12345678910 11
A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3A17 DQB1 DQB5
B DQG6 DQG2 BCBGNC BWA16 BB BFDQB2 DQB6
C DQG7 DQG3 BHBDNC E1NC BE BA DQB3 DQB7
D DQG8 DQG4 VSS NC NC GGW NC VSS DQB4 DQB8
E DQG9 DQC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQF9 DQB9
FDQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS DQF8 DQF4
G DQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF7 DQF3
H DQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS DQF6 DQF2
J DQC1 DQC5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF5 DQF1
K NC NC CK NC VSS MCL VSS NC DP NC QE
L DQH1 DQH5 VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1
M DQH2 DQH6 VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2
N DQH3 DQH7 VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA7 DQA3
P DQH4 DQH8 VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4
R DQD9 DQH9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQA9 DQE9
T DQD8 DQD4 VSS NC NC LBO PE NC VSS DQE4 DQE8
U DQD7 DQD3 NC A14 A13 A12 A11 A10 NC DQE3 DQE7
VDQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6
WDQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5
Rev 9.7 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.01 11/2000 3/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815272 BGA Pin Description
Pin Location Symbol Type Description
W6, V6 A0, A1IAddress field LSBs and Address Counter Preset Inputs.
W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,
U5, U4, A3, B7, A9 An IAddress Inputs
L11, M11, N11, P11, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, VV2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9
I/O Data Input and Output pins (x36 Version)
C9, B8, B3, C4, C8, B9, B4, C3 BA, BB, BC,BD,
BE, BF, BG,BHIByte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K10,
T4, T5, T8, U3, U9 NC -No Connect
K3 CK IClock Input Signal; active high
D7 GW IGlobal Write Enable—Writes all bytes; active low
C6, A8 E1, E3IChip Enable; active low
A4 E2IChip Enable; active high
D6 GIOutput Enable; active low
A7 ADV IBurst address counter advance enable; active low
A5, A6 ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low
P6 ZZ ISleep Mode control; active high
L6 FT IFlow Through or Pipeline mode; active low
T6 LBO ILinear Burst Order mode; active low
N6 SCD ISingle Cycle Deselect/Dual Cycle Deselect Mode Control
G6 MCH IMust Connect High
H6, J6, K6, M6 MCL Must Connect Low
T7 PE IParity Bit Enable; active low (High = x16/32 Mode, Low = x18/36
Mode)
Rev: 1.01 11/2000 4/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
K9 DP IData Parity Mode Input; 1 = Even, 0 = Odd
K11 QE OParity Error Out; Open Drain Output
F6 ZQ I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
W2 TMS IScan Test Mode Select
W4 TDI IScan Test Data In
W8 TDO OScan Test Data Out
W9 TCK IScan Test Clock
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7 VDD ICore power supply
C3, C9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
VSS II/O and Core Ground
E3, E4, E8, E0, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ IOutput driver power supply
GS815272 BGA Pin Description
Pin Location Symbol Type Description
Rev: 1.01 11/2000 5/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815236 Pad Out
119 Bump BGA—Top View
1234567
AVDDQ A6A7ADSP A8A9VDDQ
BNC A18 A4ADSC A15 A17 NC
CNC A5A3VDD A14 A16 NC
DDQC4 DQC9 VSS ZQ VSS DQB9 DQB4
EDQC3 DQC8 VSS E1VSS DQB8 DQB3
FVDDQ DQC7 VSS GVSS DQB7 VDDQ
GDQC2 DQC6 BCADV BBDQB6 DQB2
HDQC1 DQC5 VSS GW VSS DQB5 DQB1
JVDDQ VDD DP VDD QE VDD VDDQ
KDQD1 DQD5 VSS CK VSS DQA5 DQA1
LDQD2 DQD6 BDSCD BADQA6 DQA2
MVDDQ DQD7 VSS BW VSS DQA7 VDDQ
NDQD3 DQD8 VSS A1VSS DQA8 DQA3
PDQD4 DQD9 VSS A0VSS DQA9 DQA4
RNC A2LBO VDD FT A13 PE
TNC NC A10 A11 A12 NC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Rev: 1.01 11/2000 6/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815218 Pad Out
BPR1999.05.18
119 Bump BGA—Top View
1234567
AVDDQ A6A7ADSP A8A9VDDQ
BNC A18 A4ADSC A15 A17 NC
CNC A5A3VDD A14 A16 NC
DDQB1 NC VSS ZQ VSS DQA9 NC
ENC DQB2 VSS E1VSS NC DQA8
FVDDQ NC VSS GVSS DQA7 VDDQ
GNC DQB3 BBADV NC NC DQA6
HDQB4 NCVSS GW VSS DQA5 NC
JVDDQ VDD DP VDD QE VDD VDDQ
KNC DQB5 VSS CK VSS NC DQA4
LDQB6 NC NC SCD BADQA3 NC
MVDDQ DQB7 VSS BW VSS NC VDDQ
NDQB8 NC VSS A1VSS DQA2 NC
PNC DQB9 VSS A0VSS NC DQA1
RNC A2LBO VDD FT A13 PE
TNC A10 A11 NC A12 A19 ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Rev: 1.01 11/2000 7/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815218/36 (PE = 0) Block Diagram
A1
A0 A0
A1 D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E1
FT
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
DQx0–DQx9 DP
Parity
QE
Parity
Encode
Compare
36
4
36
36
4
32
Note: Only x36 version shown for simplicity.
SCD
36
36
D Q
Register
4
BA
BB
BC
BD
Rev: 1.01 11/2000 8/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815218/36 (PE = 1) x32 Mode Block Diagram
A1
A0 A0
A1 D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
E1
FT
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
DQx0–DQx8 DP
Parity
QE
Parity
Encode
Compare
32
4
32
36
4
32
Note: Only x36 version shown for simplicity.
SCD
DQ
Register
DQ
Register
Parity
Encode
32
4
32
36
Rev: 1.01 11/2000 9/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO LLinear Burst
HInterleaved Burst
Output Register Control FT LFlow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Single / Dual Cycle Deselect Control SCD LDual Cycle Deselect
H or NC Single Cycle Deselect
ByteSafe Data Parity Control DP LCheck for Odd Parity
H or NC Check for Even Parity
Parity Enable PE L or NC Activate 9th I/O’s (x18/36 Mode)
HDeactivate 9th I/O’s (x16/32 Mode)
FLXDrive Output Impedance Control ZQ LHigh Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.01 11/2000 10/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Function GW BW BABBBCBDNotes
Read H H XXXX1
Read HLHHHH1
Write byte a HL L HHH2, 3
Write byte b HLHLH H 2, 3
Write byte c HLH H LH2, 3, 4
Write byte d HLHHHL2, 3, 4
Write all bytes HLLLLL2, 3, 4
Write all bytes LXXXXX
Rev: 1.01 11/2000 11/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Synchronous Truth Table
Operation Address Used
State
Diagram
Key5
E1ADSP ADSC ADV W3DQ4
Deselect Cycle, Power Down None XHXLX X High-Z
Deselect Cycle, Power Down None XL L X X X High-Z
Deselect Cycle, Power Down None XLHLX X High-Z
Read Cycle, Begin Burst External RL L X X X Q
Read Cycle, Begin Burst External RLHLXFQ
Write Cycle, Begin Burst External WLHLXTD
Read Cycle, Continue Burst Next CR XH H LFQ
Read Cycle, Continue Burst Next CR HXHLFQ
Write Cycle, Continue Burst Next CW XH H LTD
Write Cycle, Continue Burst Next CW HXHLTD
Read Cycle, Suspend Burst Current XHHHFQ
Read Cycle, Suspend Burst Current HXH H FQ
Write Cycle, Suspend Burst Current XHHHTD
Write Cycle, Suspend Burst Current HXH H TD
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 11/2000 12/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.01 11/2000 13/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.01 11/2000 14/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VCK Voltage on Clock Input Pin –0.5 to 6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Notes
Supply Voltage VDD 3.135 3.3 3.6 V
I/O Supply Voltage VDDQ 2.375 2.5 VDD V1
Input High Voltage VIH 1.7 —VDD +0.3 V2
Input Low Voltage VIL –0.3 —0.8 V2
Ambient Temperature (Commercial Range Versions) TA0 25 70 °C3
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C3
Rev: 1.01 11/2000 15/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Input/Output Capacitance CI/O VOUT = 0 V 6 (x36)
12 (x18)
7 (x36)
12 (x18) pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2
Junction to Case (TOP) —RΘJC 9°C/W 3
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Rev: 1.01 11/2000 16/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
AC Test Conditions
Parameter Conditions
Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
Output load Fig. 1& 2
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
Mode Pin Input Current IINMVDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–300 uA
–1 uA
1 uA
1 uA
Output Leakage Current IOL
Output Disable,
VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 4 mA —0.4 V
DQ
VT = 1.25 V
50Ω30pF*DQ
2.5 V
Output Load 1 Output Load 2
225Ω
225Ω
5pF*
* Distributed Test Jig Capacitance
Rev: 1.01 11/2000 17/38 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
Operating Currents
Parameter Test Conditions Mode Symbol
-225 -200 -180 -166 -150 -133
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x72)
Pipeline IDD
IDDQ
421
149
431
159
380
132
390
142
347
119
357
129
324
110
334
120
298
99
308
109
269
88
279
98 mA
Flow
Through
IDD
IDDQ
244
78
254
88
215
66
225
76
215
66
225
76
215
66
225
76
215
66
225
76
160
44
170
54 mA
(x36)
Pipeline IDD
IDDQ
335
74
345
84
303
66
313
76
278
59
288
69
260
55
270
65
240
50
250
60
218
44
228
54 mA
Flow
Through
IDD
IDDQ
199
39
209
49
177
33
187
43
177
33
187
43
177
33
187
43
177
33
187
43
134
22
144
32 mA
(x18)
Pipeline IDD
IDDQ
310
37
320
47
281
33
291
43
258
30
268
40
242
27
252
37
223
25
233
35
204
22
214
32 mA
Flow
Through
IDD
IDDQ
186
19
196
29
166
17
176
27
166
17
176
27
166
17
176
27
166
17
176
27
127
11
137
21 mA
Standby
Current ZZ ≥ VDD – 0.2 V —Pipeline ISB 10 20 10 20 10 20 10 20 10 20 10 20 mA
Flow
Through ISB 10 20 10 20 10 20 10 20 10 20 10 20 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—Pipeline IDD 80 85 75 80 70 75 64 70 60 65 50 55 mA
Flow
Through IDD 60 65 50 55 50 55 50 55 50 55 45 50 mA
