GS815236B-150IT - Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Preliminary

GS815218/36/72B-225/200/180/166/150/133

1M x 18, 512K x 36, 256K x 72

16Mb S/DCD Sync Burst SRAMs

200 MHz–133MHz

3.3 V VDD

2.5 V or 3.3 V I/O

119- and 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• On-chip parity encoding and error detection

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Functional Description

Applications

The GS815218/36/72B is a 18,874,368-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS815218/36/72B is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

ByteSafe™ Parity Functions

The GS815218/36/72B features ByteSafe data security functions.

See the detailed discussion following.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS815218/36/72B operates on a 3.3 V power supply. All

input are 3.3 V- and 2.5 V-compatible. Separate output power

(VDDQ) pins are used to decouple output noise from the internal

circuits and are 3.3 V- and 2.5 V-compatible.

-225 -200 -180 -166 -150 -133 Unit

Flow

Through

2-1-1-1

tKQ

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

7.0

8.5

205

240

325

7.5

10.0

185

210

285

8.0

10.0

185

210

285

8.5

10.0

185

210

285

10.0

185

210

285

11.0

15.0

140

160

205

Pipeline

3-1-1-1

tKQ

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

2.5

4.4

350

410

570

3.0

5.0

315

370

515

3.2

5.5

290

340

470

3.5

6.0

270

315

435

3.8

6.7

250

290

400

4.0

7.5

230

260

360

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815272 Pad Out

209 Bump BGA—Top View

12345678910 11

A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3A17 DQB1 DQB5

B DQG6 DQG2 BCBGNC BWA16 BB BFDQB2 DQB6

C DQG7 DQG3 BHBDNC E1NC BE BA DQB3 DQB7

D DQG8 DQG4 VSS NC NC GGW NC VSS DQB4 DQB8

E DQG9 DQC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQF9 DQB9

FDQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS DQF8 DQF4

G DQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF7 DQF3

H DQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS DQF6 DQF2

J DQC1 DQC5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF5 DQF1

K NC NC CK NC VSS MCL VSS NC DP NC QE

L DQH1 DQH5 VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1

M DQH2 DQH6 VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2

N DQH3 DQH7 VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA7 DQA3

P DQH4 DQH8 VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4

R DQD9 DQH9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQA9 DQE9

T DQD8 DQD4 VSS NC NC LBO PE NC VSS DQE4 DQE8

U DQD7 DQD3 NC A14 A13 A12 A11 A10 NC DQE3 DQE7

VDQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6

WDQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5

Rev 9.7 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815272 BGA Pin Description

Pin Location Symbol Type Description

W6, V6 A0, A1IAddress field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,

U5, U4, A3, B7, A9 An IAddress Inputs

L11, M11, N11, P11, M10, N10, P10, R10

A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, VV2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

DQE1–DQE9

DQF1–DQF9

DQG1–DQG9

DQH1–DQH9

I/O Data Input and Output pins (x36 Version)

C9, B8, B3, C4, C8, B9, B4, C3 BA, BB, BC,BD,

BE, BF, BG,BHIByte Write Enable for DQA, DQB, DQC, DQD, DQE,

DQF, DQG, DQH I/Os; active low

B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K10,

T4, T5, T8, U3, U9 NC -No Connect

K3 CK IClock Input Signal; active high

D7 GW IGlobal Write Enable—Writes all bytes; active low

C6, A8 E1, E3IChip Enable; active low

A4 E2IChip Enable; active high

D6 GIOutput Enable; active low

A7 ADV IBurst address counter advance enable; active low

A5, A6 ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low

P6 ZZ ISleep Mode control; active high

L6 FT IFlow Through or Pipeline mode; active low

T6 LBO ILinear Burst Order mode; active low

N6 SCD ISingle Cycle Deselect/Dual Cycle Deselect Mode Control

G6 MCH IMust Connect High

H6, J6, K6, M6 MCL Must Connect Low

T7 PE IParity Bit Enable; active low (High = x16/32 Mode, Low = x18/36

Mode)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

K9 DP IData Parity Mode Input; 1 = Even, 0 = Odd

K11 QE OParity Error Out; Open Drain Output

F6 ZQ I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

W2 TMS IScan Test Mode Select

W4 TDI IScan Test Data In

W8 TDO OScan Test Data Out

W9 TCK IScan Test Clock

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7 VDD ICore power supply

C3, C9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9

VSS II/O and Core Ground

E3, E4, E8, E0, G3, G4, G8, G9, J3, J4, J8, J9,

L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ IOutput driver power supply

GS815272 BGA Pin Description

Pin Location Symbol Type Description

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815236 Pad Out

119 Bump BGA—Top View

1234567

AVDDQ A6A7ADSP A8A9VDDQ

BNC A18 A4ADSC A15 A17 NC

CNC A5A3VDD A14 A16 NC

DDQC4 DQC9 VSS ZQ VSS DQB9 DQB4

EDQC3 DQC8 VSS E1VSS DQB8 DQB3

FVDDQ DQC7 VSS GVSS DQB7 VDDQ

GDQC2 DQC6 BCADV BBDQB6 DQB2

HDQC1 DQC5 VSS GW VSS DQB5 DQB1

JVDDQ VDD DP VDD QE VDD VDDQ

KDQD1 DQD5 VSS CK VSS DQA5 DQA1

LDQD2 DQD6 BDSCD BADQA6 DQA2

MVDDQ DQD7 VSS BW VSS DQA7 VDDQ

NDQD3 DQD8 VSS A1VSS DQA8 DQA3

PDQD4 DQD9 VSS A0VSS DQA9 DQA4

RNC A2LBO VDD FT A13 PE

TNC NC A10 A11 A12 NC ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815218 Pad Out

BPR1999.05.18

119 Bump BGA—Top View

1234567

AVDDQ A6A7ADSP A8A9VDDQ

BNC A18 A4ADSC A15 A17 NC

CNC A5A3VDD A14 A16 NC

DDQB1 NC VSS ZQ VSS DQA9 NC

ENC DQB2 VSS E1VSS NC DQA8

FVDDQ NC VSS GVSS DQA7 VDDQ

GNC DQB3 BBADV NC NC DQA6

HDQB4 NCVSS GW VSS DQA5 NC

JVDDQ VDD DP VDD QE VDD VDDQ

KNC DQB5 VSS CK VSS NC DQA4

LDQB6 NC NC SCD BADQA3 NC

MVDDQ DQB7 VSS BW VSS NC VDDQ

NDQB8 NC VSS A1VSS DQA2 NC

PNC DQB9 VSS A0VSS NC DQA1

RNC A2LBO VDD FT A13 PE

TNC A10 A11 NC A12 A19 ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815218/36 (PE = 0) Block Diagram

A0 A0

A1 D0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx0–DQx9 DP

Parity

Encode

Compare

Note: Only x36 version shown for simplicity.

SCD

D Q

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

GS815218/36 (PE = 1) x32 Mode Block Diagram

A0 A0

A1 D0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx0–DQx8 DP

Parity

Encode

Compare

Note: Only x36 version shown for simplicity.

SCD

Parity

Encode

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Note:

There are pull-up devices on the ZQ, SCD DP, and FT pins and pull-down devices on the PE and ZZ pins, so those input pins can

be unconnected and the chip will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,

x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE

deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits

generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name Pin

Name State Function

Burst Order Control LBO LLinear Burst

HInterleaved Burst

Output Register Control FT LFlow Through

H or NC Pipeline

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

Single / Dual Cycle Deselect Control SCD LDual Cycle Deselect

H or NC Single Cycle Deselect

ByteSafe Data Parity Control DP LCheck for Odd Parity

H or NC Check for Even Parity

Parity Enable PE L or NC Activate 9th I/O’s (x18/36 Mode)

HDeactivate 9th I/O’s (x16/32 Mode)

FLXDrive Output Impedance Control ZQ LHigh Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BABBBCBDNotes

Read H H XXXX1

Read HLHHHH1

Write byte a HL L HHH2, 3

Write byte b HLHLH H 2, 3

Write byte c HLH H LH2, 3, 4

Write byte d HLHHHL2, 3, 4

Write all bytes HLLLLL2, 3, 4

Write all bytes LXXXXX

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Synchronous Truth Table

Operation Address Used

State

Diagram

Key5

E1ADSP ADSC ADV W3DQ4

Deselect Cycle, Power Down None XHXLX X High-Z

Deselect Cycle, Power Down None XL L X X X High-Z

Deselect Cycle, Power Down None XLHLX X High-Z

Read Cycle, Begin Burst External RL L X X X Q

Read Cycle, Begin Burst External RLHLXFQ

Write Cycle, Begin Burst External WLHLXTD

Read Cycle, Continue Burst Next CR XH H LFQ

Read Cycle, Continue Burst Next CR HXHLFQ

Write Cycle, Continue Burst Next CW XH H LTD

Write Cycle, Continue Burst Next CW HXHLTD

Read Cycle, Suspend Burst Current XHHHFQ

Read Cycle, Suspend Burst Current HXH H FQ

Write Cycle, Suspend Burst Current XHHHTD

Write Cycle, Suspend Burst Current HXH H TD

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

First Write First Read

Burst Write Burst Read

Deselect

CRCW

Simple Synchronous OperationSimple Burst Synchronous Operation

CW CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

First Write First Read

Burst Write Burst Read

Deselect

CRCW

CW CR

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V

(i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated

for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 4.6 V

VDDQ Voltage in VDDQ Pins –0.5 to VDD V

VCK Voltage on Clock Input Pin –0.5 to 6 V

VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage VDD 3.135 3.3 3.6 V

I/O Supply Voltage VDDQ 2.375 2.5 VDD V1

Input High Voltage VIH 1.7 —VDD +0.3 V2

Input Low Voltage VIL –0.3 —0.8 V2

Ambient Temperature (Commercial Range Versions) TA0 25 70 °C3

Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C3

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Note: These parameters are sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Capacitance

(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 4 5 pF

Input/Output Capacitance CI/O VOUT = 0 V 6 (x36)

12 (x18)

7 (x36)

12 (x18) pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2

Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2

Junction to Case (TOP) —RΘJC 9°C/W 3

20% tKC

VSS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA

ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

–1 uA

1 uA

300 uA

Mode Pin Input Current IINMVDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

–300 uA

–1 uA

1 uA

Output Leakage Current IOL

Output Disable,

VOUT = 0 to VDD –1 uA 1 uA

Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7 V —

Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V —

Output Low Voltage VOL IOL = 4 mA —0.4 V

VT = 1.25 V

50Ω30pF*DQ

2.5 V

Output Load 1 Output Load 2

225Ω

5pF*

* Distributed Test Jig Capacitance

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Operating Currents

Parameter Test Conditions Mode Symbol

-225 -200 -180 -166 -150 -133

Unit

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Operating

Current

Device Selected;

All other inputs

≥VIH or ≤ VIL

Output open

(x72)

Pipeline IDD

IDDQ

421

149

431

159

380

132

390

142

347

119

357

129

324

110

334

120

298

308

109

269

279

98 mA

Flow

Through

IDD

IDDQ

244

254

215

225

215

225

215

225

215

225

160

170

54 mA

(x36)

Pipeline IDD

IDDQ

335

345

303

313

278

288

260

270

240

250

218

228

54 mA

Flow

Through

IDD

IDDQ

199

209

177

187

177

187

177

187

177

187

134

144

32 mA

(x18)

Pipeline IDD

IDDQ

310

320

281

291

258

268

242

252

223

233

204

214

32 mA

Flow

Through

IDD

IDDQ

186

196

166

176

166

176

166

176

166

176

127

137

21 mA

Standby

Current ZZ ≥ VDD – 0.2 V —Pipeline ISB 10 20 10 20 10 20 10 20 10 20 10 20 mA

Flow

Through ISB 10 20 10 20 10 20 10 20 10 20 10 20 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

—Pipeline IDD 80 85 75 80 70 75 64 70 60 65 50 55 mA

Flow

Through IDD 60 65 50 55 50 55 50 55 50 55 45 50 mA

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter Symbol -225 -200 -180 -166 -150 -133 Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 4.4 —5.0 —5.5 —6.0 —6.7 —7.5 —ns

Clock to Output Valid tKQ —2.5 —3.0 —3.2 —3.5 —3.8 —4.0 ns

Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Flow

Through

Clock Cycle Time tKC 8.5 —10.0 —10.0 —10.0 —10.0 —15.0 —ns

Clock to Output Valid tKQ —7.0 —7.5 —8.0 —8.5 —10.0 —11.0 ns

Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns

Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns

Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.3 —1.5 —1.7 —ns

Clock LOW Time tKL 1.5 —1.5 —1.5 —1.5 —1.7 —2—ns

Clock to Output in High-Z tHZ11.5 2.5 1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE —2.5 —3.2 —3.2 —3.5 —3.8 —4.0 ns

G to output in Low-Z tOLZ10—0—0—0—0—0—ns

G to output in High-Z tOHZ1—2.5 —3.0 —3.2 —3.5 —3.8 —4.0 ns

Setup time tS 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Hold time tH 0.5 —0.5 —0.5 —0.5 —0.5 —0.5 —ns

ZZ setup time tZZS25—5—5—5—5—5—ns

ZZ hold time tZZH21—1—1—1—1—1—ns

ZZ recovery tZZR 100 —100 —100 —100 —100 —100 —ns

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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ADSP

ADSC

ADV

WR2 WR3

WR1

WR1 WR2 WR3

tKC

Single Write Burst Write

tKL

tKH

tS tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E inactive

A0–An

BA–BD

DQA–DQD

Write Deselected

WR1 WR2 WR3

Write Cycle Timing

tS tH

E1 only sampled with ADSP or ADSC

E1 masks ADSP

D2AD2BD2CD2DD3A

D1A

Hi-Z tS tH

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Q1AQ3A

Q2D

Q2cQ2B

Q2A

tKQ

tLZ

tOE tOHZ

tOLZ tKQX

tHZ

tKQX

ADSP

ADSC

ADV

Burst Read

RD2 RD3

tKL

tS tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BA–BD

tKH tKC

tS tH

DQA–DQD

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

tH E1 masks ADSP

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Flow Through Read-Write Cycle Timing

ADSP

ADV

Q1AD1AQ2AQ2BQ2c Q2D

Single Read Burst Read

tOE tOHZ

tS tH

tKH

DQA–DQD

BA–BD

tKL tKC

Single Write

ADSP is blocked by E inactive

tKQ tS tH

Hi-Z Q2A

Burst wrap around to it’s initial state

WR1

tS E1 masks ADSP

RD1 WR1 RD2

tS tH

A0–An

ADSC

tS tH ADSC initiated read

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Pipelined SCD Read Cycle Timing

Q1AQ3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ tKQX

tHZ

tKQX

ADSP

ADSC

ADV

Burst Read

RD2 RD3

tKL

tS tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BWA–BWD

tKH tKC

tS tH

DQA–DQD

RD1

Hi-Z

tH E1 masks ADSP

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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ADSP

ADV

Q1AD1AQ2AQ2BQ2c Q2D

Single Read Burst Read

tOE tOHZ

tS tH

tKH

DQA–DQD

BWA– BWD

tKL

tKC

Single Write

ADSP is blocked by E inactive

tKQ tS tH

Hi-Z

Pipelined SCD Read-Write Cycle Timing

WR1

tS E1 masks ADSP

RD1 WR1 RD2

tS tH

A0–An

ADSC

tS tH ADSC initiated read

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Pipelined DCD Read Cycle Timing

Q1AQ3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ tKQX

tHZ

tKQX

ADSP

ADV

Burst Read

RD2 RD3

tKL

tS tH

Suspend Burst

E1 masks ADSP

Single Read

ADSP is blocked by E1 inactive

A0–An

BA–BD

tKH tKC

DQA–DQD

RD1

Hi-Z

ADSC

tS tH ADSC initiated read

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Pipelined DCD Read-Write Cycle Timing

ADSP

ADSC

ADV

WR1

Q1AD1AQ2AQ2BQ2c Q2D

Single Read Burst Read

tOE tOHZ

tS tH

tKH

ADSC initiated read

E1 masks ADSP

DQA–DQD

tKL

tKC

Single Write

ADSP is blocked by E1 inactive

tKQ tS tH

Hi-Z

BA–BD

RD1 RD2

tS tH

A0–An WR1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output

drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there

will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on

dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address

boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface

standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Unlike

JTAG implementations that have been common among SRAM vendors for the last several years, this implementation does offer a

form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the “hand coding” that has been required to

overcome the test program compiler errors caused by previous non-compliant implementations. The JTAG Port interfaces with

conventional 2.5 V CMOS logic level signaling.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

ADSP

ADSC

tH tKH tKL

tKC

ZZ tZZR

tZZH

tZZS

Snooze

Sleep Mode Timing Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TMS Test Mode Select In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

TDO Test Data Out Out

Output that is active depending on the state of the TAP state machine. Output changes in

response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1

compliant because some of the mandatory instructions are uniquely implemented. The TAP on this device may be used to monitor

all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This

ID Register Contents

Die

Revision

Code

Not Used I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1

110 9 8 7 6 5 4 3 2 1 0

x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1

x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Instruction Register

ID Code Register

Boundary Scan Register

012

· · · ·

31 30 29

012

· · ·

· · ·· · ·

Bypass Register

TDI TDO

TMS

TCK Test Access Port (TAP) Controller

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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device will not perform INTEST or the preload portion of the SAMPLE / PRELOAD command.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-

tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm

the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-

ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0 0

11 0

1 1 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the

TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-

DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This

functionality is not Standard 1149.1 compliant.

EXTEST (EXTEST-A)

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in

the device, is loaded with all logic 0s. The EXTEST implementation in this device does not, without further user intervention, actually move

the contents of the scan chain onto the RAM’s output pins. Therefore, this device is not strictly 1149.1-compliant. Nevertheless, this RAM’s

TAP does respond to an all 0s instruction, EXTEST (000), by overriding the RAM’s control inputs and activating the Data I/O output drivers.

The RAM’s main clock (CK) may then be used to transfer Boundary Scan Register contents associated with each I/O from the scan register

to the RAM’s output drivers and onto the I/O pins. A single CK transition is sufficient to transfer the data, but more transitions will do no

harm.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-

ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST-A 000 Places the Boundary Scan Register between TDI and TDO.

This RAM implements an Clock Assisted EXTEST function. *Not 1149.1

Compliant * 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

Forces all RAM output drivers to High-Z. 1

RFU 011 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

SAMPLE/

PRELOAD 100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1

Compliant *

GSI 101 GSI private instruction. 1

RFU 110 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

Test Port Input High Voltage VIHT 0.7 * VDD VDD +0.3 V1, 2

Test Port Input Low Voltage VILT –0.3 0.3 * VDD V1, 2

TMS, TCK and TDI Input Leakage Current IINTH –300 1 uA 3

TMS, TCK and TDI Input Leakage Current IINTL –1 1 uA 4

TDO Output Leakage Current IOLT –1 1 uA 5

Test Port Output High Voltage VOHT 1.7 —V6, 7

Test Port Output Low Voltage VOLT —0.4 V6, 8

Note:

1. This device features input buffers compatible with 2.5 V I/O drivers.

2. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tTKC.

3. VDD ≥ VIN ≥ VIL

4. 0 V ≤ VIN ≤ VIL

5. Output Disable, VOUT = 0 to VDD

6. The TDO output driver is served by the VDD supply.

7. IOH = –4 mA

8. IOL = + 4 mA

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

VT = 1.25 V

50Ω30pF*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 20 —ns

TCK Low to TDO Valid tTKQ —10 ns

TCK High Pulse Width tTKH 10 —ns

TCK Low Pulse Width tTKL 10 —ns

TDI & TMS Set Up Time tTS 5—ns

TDI & TMS Hold Time tTH 5—ns

tTKQ

tTS tTH

tTKH tTKL

TCK

TMS

TDI

TDO

tTKC

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS815218/36B BGA Boundary Scan Register

Note:

1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.

2. Registers are listed in exit order (i.e. Location 1 is the first out of the TDO pin.

3. NC = No Connect, NA = Not Active

Order

x36 x18 Bump

x36 x18

1PE 7R

2PH = 0 n/a

3A10 3T 3T

4A11 4T 2T

5A12 5T

6A13 6R

7A14 5C

8A15 5B

9A16 6C

10 x36 = DQA9

x32 = NA = 0 NC = 1 6P

11 DQA8 NC = 1 7N

12 DQA7 NC = 1 6M

13 DQA6 NC = 1 7L

14 DQA5 NC = 1 6K

15 DQA4 DQA1 7P

16 DQA3 DQA2 6N

17 DQA2 DQA3 6L

18 DQA1 DQA4 7K

19 ZZ 7T

20 QE 5J

21 DQB1 DQA5 6H

22 DQB2 DQA6 7G

23 DQB3 DQA7 6F

24 DQB4 DQA8 7E

25 DQB5 x18 =DQA9

x16 = NA = 0 7H 6D

26 DQB6 NC = 1 6G

27 DQB7 NC = 1 6E

28 DQB8 NC = 1 7D

29 x36 = DQB9

x32 = NA = 0

A19 6D 6T

30 A96A

31 A85A

32 ADV 4G

33 ADSP 4A

34 ADSC 4B

35 G4F

36 BW 4M

37 GW 4H

38 CK 4K

39 PH = 1 n/a

40 PH = 0 n/a

41 A17 6B

42 BABA5L

43 BBBB5G 3G

44 BCNC = 1 3G 5G

45 BDNC = 1 3L

46 A18 2B

47 E14E

48 A73A

49 A62A

50 x36 =DQC9

x32 = NA = 0 NC = 1 2D

51 DQC8 NC = 1 1E

52 DQC7 NC = 1 2F

53 DQC6 NC = 1 1G

54 DQC5 NC = 1 2H

55 DQC4 DQB1 1D

56 DQC3 DQB2 2E

57 DQC2 DQB3 2G

Order

x36 x18 Bump

x36 x18

58 DQC1 DQB4 1H

59 FT 5R

60 DP 3J

61 SCD 4L

62 DQD1 DQB5 2K

63 DQD2 DQB6 1L

64 DQD3 DQB7 2M

65 DQD4 DQB8 1N

66 DQD5 x18 = DQB9

x16 = NA = 0 1K 2P

67 DQD6 NC = 1 2L

68 DQD7 NC = 1 2N

69 DQD8 NC = 1 1P

70 x36 = DQD9

x32 = NA = 0 NC = 1 2P 1K

71 LBO 3R

72 A52C

73 A43B

74 A33C

75 A22R

76 A14N

77 A04P

78 ZQ 4D

BPR 1999.12.10

Order

x36 x18 Bump

x36 x18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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209 BGA Package Drawing

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

Symbol Min Typ Max Units

A1.70 mm

A1 0.40 0.50 0.60 mm

∅b0.50 0.60 0.70 mm

c0.31 0.36 0.38 mm

D21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E13.9 14.0 14.1 mm

E1 10.0 (BSC) mm

e1.00 (BSC) mm

aaa 0.15 mm

Rev 1.0

∅be

aaa

Bottom View

Side View

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Package Dimensions—119-Pin PBGA

Pin 1

Corner

C T

1234567

Package Dimensions—119-Pin PBGA

Unit: mm

Symbol Description Min. Nom. Max

AWidth 13.8 14.0 14.2

BLength 21.8 22.0 22.2

CPackage Height (including ball) — — 2.40

DBall Size 0.60 0.75 0.90

EBall Height 0.50 0.60 0.70

FPackage Height (excluding balls) —1.46 1.70

GWidth between Balls —1.27 —

KPackage Height above board 0.80 0.90 1.00

NCut-out Package Width —12.00 —

PFoot Length —19.50 —

RWidth of package between balls —7.62 —

SLength of package between balls —20.32 —

TVariance of Ball Height —0.15 —

Bottom View

Top View

Side View

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Package Speed2

(MHz/ns) TA3Status

1M x 18 GS815218B-225 ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 C

1M x 18 GS815218B-200 ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 C

1M x 18 GS815218B-180 ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 C

1M x 18 GS815218B-166 ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 C

1M x 18 GS815218B-150 ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 C

1M x 18 GS815218B-133 ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 C

512K x 36 GS815236B-225 ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 C

512K x 36 GS815236B-200 ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 C

512K x 36 GS815236B-180 ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 C

512K x 36 GS815236B-166 ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 C

512K x 36 GS815236B-150 ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 C

512K x 36 GS815236B-133 ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 C

256k x 72 GS815272B-225 ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 C

256k x 72 GS815272B-200 ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 C

256k x 72 GS815272B-180 ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 C

256k x 72 GS815272B-166 ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 C

256k x 72 GS815272B-150 ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 C

256k x 72 GS815272B-133 ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 C

1M x 18 GS815218B-225I ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 INot Available

1M x 18 GS815218B-200I ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 INot Available

1M x 18 GS815218B-180I ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 I

1M x 18 GS815218B-166I ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 I

1M x 18 GS815218B-150I ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 I

1M x 18 GS815218B-133I ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 I

512K x 36 GS815236B-225I ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 INot Available

512K x 36 GS815236B-200I ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 INot Available

512K x 36 GS815236B-180I ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 I

512K x 36 GS815236B-166I ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 I

512K x 36 GS815236B-150I ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 I

512K x 36 GS815236B-133I ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS815218B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

256k x 72 GS815272B-225I ByteSafe S/DCD Pipeline/Flow Through BGA 225/7 INot Available

256k x 72 GS815272B-200I ByteSafe S/DCD Pipeline/Flow Through BGA 200/7.5 INot Available

256k x 72 GS815272B-180I ByteSafe S/DCD Pipeline/Flow Through BGA 180/8 I

256k x 72 GS815272B-166I ByteSafe S/DCD Pipeline/Flow Through BGA 166/8.5 I

256k x 72 GS815272B-150I ByteSafe S/DCD Pipeline/Flow Through BGA 150/10 I

256k x 72 GS815272B-133I ByteSafe S/DCD Pipeline/Flow Through BGA 133/11 I

Org Part Number1Type Package Speed2

(MHz/ns) TA3Status

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS815218B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS815218/36/72B-225/200/180/166/150/133

0.18u 16M Sync SRAM Data Sheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content Page;Revisions;Reason

815218_r1 • Creation of new datasheet

815218_r1; 815218_r1_01 Content • Update Features list on page 1

• Completely change table on page 1

• Update Mode Pin Functions table on page 9