Semiconductor Components Industries, LLC, 2001
July, 2001 – Rev. 2 1Publication Order Number:
MMBT2222AWT1/D
MMBT2222AWT1
Preferred Device
General Purpose Transistor
NPN Silicon
These transistors are designed for general purpose amplifier
applications. They are housed in the SOT–323/SC–70 package which
is designed for low power surface mount applications.
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO 40 Vdc
Collector–Base Voltage VCBO 75 Vdc
Emitter–Base V oltage VEBO 6.0 Vdc
Collector Current – Continuous IC600 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board
TA = 25°CPD150 mW
Thermal Resistance
Junction to Ambient RJA 833 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
Device Package Shipping
ORDERING INFORMATION
MMBT2222AWT1 SC–70
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SC–70
CASE 419
STYLE 3
3000/Tape & Reel
2
3
1
Preferred devices are recommended choices for future use
and best overall value.
MARKING DIAGRAM
P1 M
P1 = Specific Device Code
M = Date Code
COLLECTOR
3
1
BASE
2
EMITTER
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage (Note 1.)
(IC = 1.0 mAdc, IB = 0) V(BR)CEO 40 Vdc
Collector–Base Breakdown Voltage
(IC = 10 Adc, IE = 0) V(BR)CBO 75 Vdc
Emitter–Base Breakdown Voltage
(IE = 10 Adc, IC = 0) V(BR)EBO 6.0 Vdc
Base Cutoff Current
(VCE = 60 Vdc, VEB = 3.0 Vdc) IBL 20 nAdc
Collector Cutoff Current
(VCE = 60 Vdc, VEB = 3.0 Vdc) ICEX 10 nAdc
ON CHARACTERISTICS (Note 1.)
DC Current Gain (Note 1.)
(IC = 0.1 mAdc, VCE = 10 Vdc)
(IC = 1.0 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc)
(IC = 150 mAdc, VCE = 10 Vdc)
(IC = 500 mAdc, VCE = 10 Vdc)
HFE 35
50
75
100
40
300
Collector–Emitter Saturation Voltage (Note 1.)
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
VCE(sat)
0.3
1.0
Vdc
Base–Emitter Saturation Voltage (Note 1.)
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
VBE(sat) 0.6
1.2
2.0
Vdc
SMALL–SIGNAL CHARACTERISTICS
Current–Gain – Bandwidth Product
(IC = 20 mAdc, VCE = 20 Vdc, f = 100 MHz) fT300 MHz
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cobo 8.0 pF
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo 30 pF
Input Impedance
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz) hie 0.25 1.25 k ohms
Voltage Feedback Ratio
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz) hre 4.0 X 10–4
Small–Signal Current Gain
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz) hfe 75 375
Output Admittance
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz) hoe 25 200 mhos
Noise Figure
(VCE = 10 Vdc, IC = 100 Adc, RS = 1.0 k, f = 1.0 kHz) NF 4.0 dB
SWITCHING CHARACTERISTICS
Delay Time (VCC = 3.0 Vdc, VBE = –0.5 Vdc, td 10
ns
Rise Time
(VCC
3
.
0
Vdc
,
VBE
0
.
5
Vdc
,
IC = 150 mAdc, IB1 = 15 mAdc) tr 25 ns
Storage Time (VCC = 30 Vdc, IC = 150 mAdc, ts 225
ns
Fall Time
(VCC
30
Vdc
,
IC
150
mAdc
,
IB1 = IB2 = 15 mAdc) tf 60 ns
1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
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Figure 1. Turn–On Time Figure 2. Turn–Off Time
SWITCHING TIME EQUIVALENT TEST CIRCUITS
Scope rise time < 4 ns
*Total shunt capacitance of test jig, connectors, and oscilloscope.
+16 V
-2 V < 2 ns
0
1.0 to 100 µs,
DUTY CYCLE 2.0%
1 k
+30 V
200
CS* < 10 pF
+16 V
-14 V
0
< 20 ns
1.0 to 100 µs,
DUTY CYCLE 2.0%
1 k
+30 V
200
CS* < 10 pF
-4 V
1N914
1000
10
20
30
50
70
100
200
300
500
700
1.0 k0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500 700
IC, COLLECTOR CURRENT (mA)
Figure 3. DC Current Gain
hFE, DC CURRENT GAINVCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
1.0
0.8
0.6
0.4
0.2
0
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50
IB, BASE CURRENT (mA)
Figure 4. Collector Saturation Region
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Figure 5. TurnOn Time
IC, COLLECTOR CURRENT (mA)
70
100
200
50
t, TIME (ns)
10 20 70
5.0
100
5.0 7.0 30 50 200
10
30
7.0
20
IC/IB = 10
TJ = 25°C
tr @ VCC = 30 V
td @ VEB(off) = 2.0 V
td @ VEB(off) = 0
3.0
2.0
300 500
500
t, TIME (ns)
5.0
7.0
10
20
30
50
70
100
200
300
Figure 6. TurnOff Time
IC, COLLECTOR CURRENT (mA)
10 20 70 1005.0 7.0 30 50 200 300 500
VCC = 30 V
IC/IB = 10
IB1 = IB2
TJ = 25°C
ts = ts - 1/8 tf
tf
Figure 7. Frequency Effects
f, FREQUENCY (kHz)
4.0
6.0
8.0
10
2.0
0.1
Figure 8. Source Resistance Effects
RS, SOURCE RESISTANCE (OHMS)
NF, NOISE FIGURE (dB)
1.0 2.0 5.0 10 20 50
0.2 0.5
0
100
NF, NOISE FIGURE (dB)
0.01 0.02 0.05
RS = OPTIMUM
RS = SOURCE
RS = RESISTANCE
IC = 1.0 mA, RS = 150
500 µA, RS = 200
100 µA, RS = 2.0 k
50 µA, RS = 4.0 k
f = 1.0 kHz
IC = 50 µA
100 µA
500 µA
1.0 mA
4.0
6.0
8.0
10
2.0
0
50 100 200 500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k
Figure 9. Capacitances
REVERSE VOLTAGE (VOLTS)
3.0
5.0
7.0
10
2.0
0.1
CAPACITANCE (pF)
1.0 2.0 3.0 5.0 7.0 10 20 30 50
0.2 0.3 0.5 0.7
Ccb
20
30
Ceb
Figure 10. Current–Gain Bandwidth Product
IC, COLLECTOR CURRENT (mA)
70
100
200
300
50
500
fT, CURRENT-GAIN BANDWIDTH PRODUCT (MHz)
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
VCE = 20 V
TJ = 25°C
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Figure 11. “On” Voltages
IC, COLLECTOR CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
V, VOLTAGE (VOLTS)
0
TJ = 25°C
VBE(sat) @ IC/IB = 10
VCE(sat) @ IC/IB = 10
VBE(on) @ VCE = 10 V
Figure 12. Temperature Coefficients
IC, COLLECTOR CURRENT (mA)
-0.5
0
+0.5
COEFFICIENT (mV/ C)
-1.0
-1.5
-2.5
°
RVC for VCE(sat)
RVB for VBE
0.1 1.0 2.0 5.0 10 20 50
0.2 0.5 100 200 500 1.0 k
1.0 V
-2.0
0.1 1.0 2.0 5.0 10 20 500.2 0.5 100 200 500
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PD = TJ(max) – TA
RθJA
PD = 150°C – 25°C
0.625°C/W = 200 milliwatts
The soldering temperature and time should not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied dur-
ing cooling
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
INFORMATION FOR USING THE SC–70/SOT–323 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
SC–70/SOT–323 POWER DISSIPATION
The power dissipation of the SC–70/SOT–323 is a func-
tion of the pad size. This can vary from the minimum pad
size for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device
is determined by TJ(max), the maximum rated junction tem-
perature of the die, RθJA, the thermal resistance from the
device junction to ambient; and the operating temperature,
TA. Using the values provided on the data sheet, PD can be
calculated as follows.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one
can calculate the power dissipation of the device which in
this case is 200 milliwatts.
The 0.625°C/W assumes the use of the recommended
footprint on a glass epoxy printed circuit board to achieve
a power dissipation of 200 milliwatts. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, a higher power dissipation of 300 milli-
watts can be achieved using the same footprint.
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference should be a maximum of 10°C.
mm
inches
0.035
0.9
0.075
0.7
1.9
0.028
0.65
0.025
0.65
0.025
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STEP 1
PREHEAT
ZONE 1
RAMP"
STEP 2
VENT
SOAK"
STEP 3
HEATING
ZONES 2 & 5
RAMP"
STEP 4
HEATING
ZONES 3 & 6
SOAK"
STEP 5
HEATING
ZONES 4 & 7
SPIKE"
STEP 6
VENT
STEP 7
COOLING
200°C
150°C
100°C
50°C
TIME (3 TO 7 MINUTES TOTAL) TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205° TO 219°C
PEAK AT
SOLDER JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
100°C
150°C
160°C
140°C
Figure 13. Typical Solder Heating Profile
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
170°C
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session t o the next. Figure 7 shows a typical heating profile
for use when soldering a surface mount device to a printed
circuit board. This profile will vary among soldering
systems but it is a good starting point. Factors that can
affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the surface mounted package
should be the same as the pad size on the printed circuit
board, i.e., a 1:1 registration.
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because i t has a lar ge surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
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PACKAGE DIMENSIONS
CN
AL
D
G
SB
H
J
K
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.071 0.087 1.80 2.20
B0.045 0.053 1.15 1.35
C0.032 0.040 0.80 1.00
D0.012 0.016 0.30 0.40
G0.047 0.055 1.20 1.40
H0.000 0.004 0.00 0.10
J0.004 0.010 0.10 0.25
K0.017 REF 0.425 REF
L0.026 BSC 0.650 BSC
N0.028 REF 0.700 REF
S0.079 0.095 2.00 2.40
0.05 (0.002) STYLE 3:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
SC–70/SOT–323
CASE 419–04
ISSUE L
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