2.5 V to 5.5 V Octal Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308/AD5318/AD5328
Rev. F
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FEATURES
AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL, B version: ±0.75 LSB INL
AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL, B version: ±3 LSB INL
AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL, B version: ±12 LSB INL
Low power operation: 0.7 mA @ 3 V
Guaranteed monotonic by design over all codes
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Double-buffered input logic
Buffered/unbuffered/VDD reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
Programmability
Individual channel power-down
Simultaneous update of outputs (LDAC)
Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-
compatible 3-wire serial interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +125°C
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/s. The AD5308/
AD5318/AD5328 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards.
The references for the eight DACs are derived from two
reference pins (one per DAC quad). These reference inputs can
be configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 400 nA at 5 V (120 nA at 3 V).
The eight channels of the DAC may be powered down individually.
All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.
AD5308/AD5318/AD5328
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
Digital-to-Analog Converter .................................................... 15
Resistor String............................................................................. 15
Output Amplifier........................................................................ 15
Power-On Reset .......................................................................... 16
Power-Down Mode .................................................................... 16
Serial Interface ............................................................................ 16
Low Power Serial Interface ....................................................... 18
Load DAC Input (LDAC) Function......................................... 18
Double-Buffered Interface ........................................................ 18
Microprocessor Interface............................................................... 19
ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328
Interface ....................................................................................... 19
68HC11/68L11-to-AD5308/AD5318/AD5328 Interface ..... 19
80C51/80L51-to-AD5308/AD5318/AD5328 Interface......... 19
Microwire-to-AD5308/AD5318/AD5328 Interface.............. 20
Applications Information.............................................................. 21
Typical Application Circuit....................................................... 21
Driving VDD from the Reference Voltage ................................ 21
Bipolar Operation Using the AD5308/AD5318/AD5328..... 21
Opto-Isolated Interface for Process Control Applications ... 21
Decoding Multiple AD5308/AD5318/AD5328s.................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
4/11—Rev. E to Rev. F
Added Automotive Products Information ................. Throughout
2/11—Rev. D to Rev. E
Change to Temperature Range .................................... Throughout
Changes to Table 3, t4 Timing Characteristics .............................. 6
3/07—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings Section......................... 7
9/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Change to Equation........................................................................ 21
11/03—Rev. A to Rev. B
Changes to Ordering Guide ............................................................ 4
Changes to Y axis on TPCs 12, 13, and 15 .................................... 9
8/03—Rev. 0 to Rev. A
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Edits to Absolute Maximum Ratings ............................................. 4
Edits to Ordering Guide .................................................................. 4
Updated Outline Dimensions....................................................... 18
AD5308/AD5318/AD5328
Rev. F | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER DAC
REGISTER
INTERFACE
LOGIC
DIN
GND
VOUTB
VOUTC
VOUTD
VOUTE
VOUTG
VOUTH
VOUTF
VDD
RESET
GAIN-SELECT
LOGIC
VOUTA
VREFEFGH
VDD
V
REF
A
BCD
SCLK
POWER-ON
RESET GAIN-SELECT
LOGIC POWER-DOWN
LOGIC
STRING
BUFFER
BUFFERBUFFER
BUFFERBUFFER
BUFFERBUFFER
BUFFERBUFFER
BUFFERBUFFER
BUFFERBUFFER
BUFFERBUFFER
DD
VDD
02812-001
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
SYNC
LDAC
LDAC
BUFFERBUFFER
GND
Figure 1.
AD5308/AD5318/AD5328
Rev. F | Page 4 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise specified.
Table 1.
A Version1 B Version1
Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments
DC PERFORMANCE3, 4
AD5308
Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.75 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by
design over all codes
AD5318
Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±3 LSB
Differential Nonlinearity ±0.05 ±0.50 ±0.05 ±0.50 LSB Guaranteed monotonic by
design over all codes
AD5328
Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±12 LSB
Differential Nonlinearity ±0.2 ±1.0 ±0.2 ±1.0 LSB Guaranteed monotonic by
design over all codes
Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, gain = 2, see
Figure 27 and Figure 28
Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR VDD = 4.5 V, gain = 2, see
Figure 27 and Figure 28
Lower Deadband5 10 60 10 60 mV Lower deadband exists only
if offset error is negative, see
Figure 27
Upper Deadband5 10 60 10 60 mV Upper deadband exists only
if VREF = VDD and offset plus
gain error is positive, see
Figure 28
Offset Error Drift6 −12 −12 ppm of
FSR/°C
Gain Error Drift6 −5 −5 ppm of
FSR/°C
DC Power Supply Rejection Ratio6 −60 −60 dB VDD = ±10%
DC Crosstalk6 200 200 μV RL = 2 kΩ to GND or VDD
DAC REFERENCE INPUTS6
VREF Input Range 1.0 VDD 1.0 VDD V Buffered reference mode
0.25 VDD 0.25 VDD V Unbuffered reference mode
VREF Input Impedance (RDAC) >10.0 >10.0 MΩ Buffered reference mode
and power-down mode
37.0 45.0 37.0 45.0 kΩ Unbuffered reference mode,
0 V to VREF output range
18.0 22.0 18.0 22.0 kΩ Unbuffered reference mode,
0 V to 2 VREF output range
Reference Feedthrough −70.0 −70.0 dB Frequency = 10 kHz
Channel-to-Channel Isolation −75.0 −75.0 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage7 0.001 0.001 V This is a measure of the
minimum and maximum
Maximum Output Voltage7 V
DD −
0.001
V
DD − 0.001 V Drive capability of the
output amplifier
DC Output Impedance 0.5 0.5 Ω
AD5308/AD5318/AD5328
Rev. F | Page 5 of 28
A Version1 B Version1
Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments
Short Circuit Current 25.0 25.0 mA VDD = 5 V
16.0 16.0 mA VDD = 3 V
Power-Up Time 2.5 2.5 μs Coming out of power-down
mode, VDD = 5 V
5.0 5.0 μs Coming out of power-down
mode, VDD = 3 V
LOGIC INPUTS6
Input Current ±1 ±1 μA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%
0.8 0.8 V VDD = 3 V ± 10%
0.7 0.7 V VDD = 2.5 V
VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V, TTL and
CMOS compatible
Pin Capacitance 3.0 3.0 pF
POWER REQUIREMENTS
VDD 2.5 5.5 2.5 5.5 V
IDD (Normal Mode)8 VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 1.0 1.8 1.0 1.8 mA All DACs in unbuffered
mode, in buffered mode
VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA Extra current is typically x μA
per DAC; x = (5 μA +
VREF/RDAC)/4
IDD (Power-Down Mode)9 VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 μA
VDD = 2.5 V to 3.6 V 0.12 1 0.12 1 μA
1 Temperature range (A, B version): −40°C to +125°C; typical at 25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded unless stated otherwise.
4 Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization; not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
8 Interface inactive. All DACs active. DAC outputs unloaded.
9 All eight DACs powered down.
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. AC Characteristics1
A, B Version2
Parameter3 Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time VREF = VDD = 5 V
AD5308 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5318 7 9 μs 1/4 scale to 3/4 scale change (0x100 To 0x300)
AD5328 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate 0.7 V/μs
Major-Code Change Glitch Energy 12 nV-sec 1 LSB change around major carry
Digital Feedthrough 0.5 nV-sec
Digital Crosstalk 0.5 nV-sec
Analog Crosstalk 1 nV-sec
DAC-to-DAC Crosstalk 3 nV-sec
Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p, unbuffered mode
Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Temperature range (A, B version): –40°C to +125°C; typical at 25°C.
3 See the Terminology section.
AD5308/AD5318/AD5328
Rev. F | Page 6 of 28
Table 3. Timing Characteristics1, 2, 3
A, B Version
Parameter Limit at TMIN, TMAX Unit Conditions/Comments
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +105°C
15 ns min
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +125°C
t5 5 ns min Data set up time
t6 4.5 ns min Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 50 ns min Minimum SYNC high time
t9 20 ns min LDAC pulse width
t10 20 ns min SCLK falling edge to LDAC rising edge
t11 0 ns min SCLK falling edge to LDAC falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
02812-002
SCLK
DIN DB15 DB0
t
1
t
2
t
8
t
3
t
4
t
5
t
6
t
9
t
11
t
7
t
10
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
LDAC
1
LDAC
2
SYNC
Figure 2. Serial Interface Timing Diagram
AD5308/AD5318/AD5328
Rev. F | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise specified.
Table 4.
Parameter Rating1
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
VOUTA–VOUTD to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ MAX) 150°C
16-Lead TSSOP
Power Dissipation (TJ MAX − TA)/θJA
θJA Thermal Impedance 150.4°C/W
Lead Temperature JEDEC industry-standard
Soldering J-STD-020
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5308/AD5318/AD5328
Rev. F | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
VDD
VOUTA
VOUTD
VOUTC
VOUTB
LDAC
DIN
GND
VOUTH
VOUTE
V
REFABCD VREFEFGH
VOUTF
VOUTG
SCLK
AD5308/
AD5318/
AD5328
TOP VIEW
(Not to Scale)
02812-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 LDAC This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simul-
taneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
3 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
7 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
8 VREFABCD Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or VDD input to the four
DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
9 VREFEFGH Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or VDD input to the four
DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
10 VOUTE Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
11 VOUTF Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
12 VOUTG Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
13 VOUTH Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
14 GND Ground Reference Point for All Circuitry on the Part.
15 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input. The DIN input buffer is powered down after each write cycle.
16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
AD5308/AD5318/AD5328
Rev. F | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
02812-006
INL ERROR (LSB)
–1.0
–0.5
0
0.5
1.0
0 50 100 150 200 250
CODE
T
A
= 25°C
V
DD
= 5V
Figure 4. AD5308 Typical INL Plot
02812-007
–3
–2
–1
0
1
2
3
INL ERROR (LSB)
0 200 400 600 800 1000
CODE
T
A
= 25°C
V
DD
= 5V
Figure 5. AD5318 Typical INL Plot
02812-008
–12
–8
–4
0
4
8
12
INL ERROR (LSB)
20001500500 10000 2500 3000 3500 4000
CODE
T
A
= 25°C
V
DD
= 5V
Figure 6. AD5328 Typical INL Plot
02812-009
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
DNL ERROR (LSB)
0 50 100 150 200 250
CODE
T
A
= 25°C
V
DD
= 5V
Figure 7. AD5308 Typical DNL Plot
02812-010
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
DNL ERROR (LSB)
0 200 400 600 800 1000
CODE
T
A
= 25°C
V
DD
= 5V
Figure 8. AD5318 Typical DNL Plot
02812-011
DNL ERROR (LSB)
–1.0
–0.5
0
0.5
1.0
20001500500 10000 2500 3000 3500 4000
CODE
T
A
= 25°C
V
DD
= 5V
Figure 9. AD5328 Typical DNL Plot
AD5308/AD5318/AD5328
Rev. F | Page 10 of 28
02812-012
MAX INL
MAX DNL
MIN INL
0.50
0.25
0
–0.25
–0.50 012345
T
A
= 25
°
C
V
DD
= 5V
MIN DNL
ERROR (LSB)
V
REF
(V)
Figure 10. AD5308 INL and DNL Error vs. VREF
02812-013
ERROR (LSB)
TEMPERATURE (°C)
0.5
0.2
–0.5
– 40 0 40
0
–0.2
80 120
–0.4
–0.3
–0.1
0.1
0.3
0.4 VREF = 3V
VDD = 5V MAX INL
MIN DNL
MIN INL
MAX DNL
Figure 11. AD5308 INL Error and DNL Error vs. Temperature
ERROR (% FSR)
–1.0
–0.5
0
0.5
1.0
TEMPERATURE (°C)
0–40 40 80 120
V
DD
= 5V
V
REF
= 2V
OFFSET ERROR
02812-014
GAIN ERROR
Figure 12. AD5308 Offset Error and Gain Error vs. Temperature
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
ERROR (% FSR)
0
0.1
0.2
2301 456
VDD (V)
TA = 25°C
VREF = 2V
GAIN ERROR
02812-015
OFFSET ERROR
Figure 13. Offset Error and Gain Error vs. VDD
0
1
2
3
4
5
V
OUT
(V)
2301 45
SINK/SOURCE CURRENT (mA)
6
5V SOURCE
3V SOURCE
5V SINK 3V SINK
02812-016
Figure 14. VOUT Source and Sink Current Capability
02812-017
DAC CODE
I
DD
(mA)
1.0
ZERO SCALE FULL SCALE
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
HALF SCALE
T
A
= 25°C
V
DD
= 5V
Figure 15. Supply Current vs. DAC Code
AD5308/AD5318/AD5328
Rev. F | Page 11 of 28
02812-018
I
DD
(mA)
SUPPLY VOLTAGE (V)
1.3
0.6
0.7
0.9
1.0
2.0
1.2
1.1
0.8
2.5 3.0 3.5 4.0 4.5 5.0
T
A
= 25°C
V
REF
= V
DD
V
REF
= 2V, GAIN = +1,
BUFFERED
V
REF
= 2V, GAIN = +1, UNBUFFERED
V
REF
= V
DD
, GAIN = +1, UNBUFFERED
Figure 16. Supply Current vs. Supply Voltage
02812-019
V
DD
(V)
I
DD
POWER-DOWN (
μ
A)
1.0
0
0.8
0.2
0.4
0.6
2.0
0.9
0.7
0.1
0.3
0.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
T
A
= 25°C
Figure 17. Power-Down Current vs. Supply Voltage
02812-020
V
LOGIC
(V)
I
DD
(mA)
0.6 0 1.0
0.7
0.8
1.0
1.2
1.4
2.0 3.0 4.0
DECREASING
V
DD
= 3V
INCREASING
0.9
1.1
1.3
1.5 2.5 3.50.5 4.5 5.0
T
A
= 25°C
V
DD
= 5V
Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing
and Decreasing
02812-021
CH1
CH2
VOUTA
SCLK
CH1 1V, CH2 5V, TIME BASE = 1μs/DIV
TA = 25°C
VDD = 5V
VREF = 5V
Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
02812-022
C
H1
C
H2
CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV
V
OUT
A
V
DD
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
Figure 20. Power-On Reset to 0 V
02812-023
CH1
CH2
V
OUT
A
CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV
PD
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
Figure 21. Exiting Power-Down to Midscale
AD5308/AD5318/AD5328
Rev. F | Page 12 of 28
02812-024
I
DD
(mA)
FREQUENCY
0.6
35
30
25
20
15
10
5
00.7 0.8 0.9 1.0 1.1
MEAN: 0.693798
MEAN: 1.02055
SS = 300
V
DD
= 3V
V
DD
= 5V
02812-027
V
REF
(V)
FULL-SCALE ERROR (V)
0.02
–0.020123456
0.01
–0.01
0
T
A
= 25°C
V
DD
= 5V
Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 25. Full-Scale Error vs. VREF
02812-028
100ns/DIV
1mV/DIV
02812-025
1μs/DIV
2.48
2.49
V
OUT
(V)
2.47
2.50
Figure 26. DAC-to-DAC Crosstalk
Figure 23. AD5328 Major-Code Transition Glitch Energy
02812-026
FREQUENCY (Hz)
10
–40
10
–20
–30
0
–10
(dB)
100 1k 10k 100k 1M 10M
–50
–60
Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)
AD5308/AD5318/AD5328
Rev. F | Page 13 of 28
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer func-
tion. Typical INL vs. code plots can be seen in Figure 4, Figure 5,
and Figure 6.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL vs. code plots can be seen
in Figure 7, Figure 8, and Figure 9.
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier (see Figure 27 and Figure 28). It can be negative or
positive, and is expressed in millivolts.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in microvolts.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (that is, LDAC is high). It is expressed in decibels.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in decibels.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-sec and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 ... 11 to
100 ... 00 or 100 ... 00 to 011 ... 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-sec and is measured
with a full-scale change on the digital input pins, that is, from
all 0s to all 1s and vice versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-sec.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose digital
code is not changed. The area of the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its atten-
uated version using the DAC. The sine wave is used as the refer-
ence for the DAC and the THD is a measure of the harmonics
present on the DAC output. It is measured in decibels.
AD5308/AD5318/AD5328
Rev. F | Page 14 of 28
02812-004
DAC CODE
ACTUAL
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
NEGATIVE
OFFSET
ERROR
AMPLIFIER
FOOTROOM
LOWER
DEADBAND
CODES
IDEAL
Figure 27. Transfer Function with Negative Offset (VREF = VDD)
DAC CODE FULL SCALE
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
OUTPUT
VOLTAGE
GAIN ERROR
PLUS
OFFSET ERROR
UPPER
DEADBAND
CODES
02812-005
Figure 28. Transfer Function with Positive Offset
AD5308/AD5318/AD5328
Rev. F | Page 15 of 28
THEORY OF OPERATION
The AD5308/AD5318/AD5328 are octal resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains eight output buffer ampli-
fiers and is written to via a 3-wire serial interface. They operate
from single supplies of 2.5 V to 5.5 V and the output buffer
amplifiers provide rail-to-rail output swing with a slew rate of
0.7 V/µs. DAC A, DAC B, DAC C, and DAC D share a common
reference input, VREFABCD. DAC E, DAC F, DAC G, and DAC H
share a common reference input, VREFEFGH. Each reference
input can be buffered to draw virtually no current from the
reference source, can be unbuffered to give a reference input
range from 0.25 V to VDD, or can come from VDD. The devices
have a power-down mode in which all DACs can be turned off
individually with a high impedance output.
DIGITAL-TO-ANALOG CONVERTER
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the VREF pin provides the reference voltage for the corre-
sponding DAC. Figure 29 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by
N
REF
OUT
DV
V
2
×
=
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for AD5308 (8 bits)
0 to 1023 for AD5318 (10 bits)
0 to 4095 for AD5328 (12 bits)
N is the DAC resolution.
INPUT
REGISTER
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER GAIN MODE
(GAIN = +1 OR +2)
V
OUT
A
V
REF
ABCD
V
DD
BUF
RESISTOR
STRING
DAC
REGISTER
02812-029
V
DD
Figure 29. Single DAC Channel Architecture
DAC Reference Inputs
There is a reference pin for each quad of DACs. The reference
inputs can be buffered from VDD, or unbuffered. The advantage
with the buffered input is the high impedance it presents to the
voltage source driving it. However, if the unbuffered mode is
used, the user can have a reference voltage as low as 0.25 V and
as high as VDD since there is no restriction due to the headroom
and footroom of the reference amplifier.
If there is a buffered reference in the circuit (for example, the
REF192), there is no need to use the on-chip buffers of the
AD5308/AD5318/AD5328. In unbuffered mode, the input
impedance is still large at typically 45 k per reference input
for 0 V to VREF mode and 22 k for 0 V to 2 VREF mode.
RESISTOR STRING
The resistor-string section is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
02812-030
R
R
R
R
R
TO OUTPUT
AMPLIFIER
Figure 30. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, the gain of the output amplifier, the offset
error, and the gain error.
If a gain of 1 is selected (gain bit = 0), the output range is
0.001 V to VREF.
If a gain of 2 is selected (gain bit = 1), the output range is
0.001 V to 2 VREF. Because of clamping, however, the maximum
output is limited to VDD − 0.001 V.
The output amplifier is capable of driving a load of 2 k to
GND or VDD, in parallel with 500 pF to GND or VDD. The
source and sink capabilities of the output amplifier can be seen
in the plot in Figure 14.
The slew rate is 0.7 V/s with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 s.
AD5308/AD5318/AD5328
Rev. F | Page 16 of 28
POWER-ON RESET
The AD5308/AD5318/AD5328 are provided with a power-on
reset function so that they power up in a defined state. The
power-on state is
• Normal operation
• Reference inputs unbuffered
• 0 V to VREF output range
• Output voltage set to 0 V
• LDAC bits set to LDAC high
Both input and DAC registers are filled with 0s and remain so
until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5308/AD5318/AD5328 have low power consumption,
typically dissipating 2.4 mW with a 3 V supply and 5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down
mode, which is described in the Serial Interface section.
When in default mode, all DACs work normally with a typical
power consumption of 1 mA at 5 V (800 A at 3 V). However,
when all DACs are powered down, that is, in power-down
mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V).
Not only does the supply current drop, but the output stage is
also internally switched from the output of the amplifier,
making it open-circuit. This has the advantage that the output is
three-state while the part is in power-down mode, and provides
a defined input condition for whatever is connected to the
output of the DAC amplifier. The output stage is illustrated in
Figure 31.
The bias generator, the output amplifiers, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. In fact, it is
possible to load new data to the input registers and DAC regis-
ters during power-down. The DAC outputs update as soon as
the device comes out of power-down mode. The time to exit
power-down is typically 2.5 s when VDD = 5 V and 5 s when
VDD = 3 V.
02812-035
POWER-DOWN
CIRCUITRY
RESISTOR-
STRING DAC
AMPLIFIER
V
OUT
Figure 31. Output Stage During Power-Down
SERIAL INTERFACE
The AD5308/AD5318/AD5328 are controlled over a versatile
3-wire serial interface that operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 2.
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK falling edge set-up time, t4. After SYNC goes
low, serial data is shifted into the device’s input shift register on
the falling edges of SCLK for 16 clock pulses.
To end the transfer, SYNC must be taken high after the falling
edge of the 16th SCLK pulse, observing the minimum SCLK
falling edge to SYNC rising edge time, t7.
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer is aborted and the DAC input
registers are not updated.
Data is loaded MSB first (Bit 15). The first bit determines
whether it is a DAC write or a control function.
DAC Write
The 16-bit word consists of 1 control bit and 3 address bits fol-
lowed by 8, 10, or 12 bits of DAC data, depending on the device
type. In the case of a DAC write, the MSB is a 0. The next 3
address bits determine whether the data is for DAC A, DAC B,
DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The
AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits
and ignores the 2 LSBs. The AD5308 uses 8 bits and ignores the
last 4 bits. These ignored LSBs should be set to 0. The data
format is straight binary, with all 0s corresponding to 0 V
output and all 1s corresponding to full-scale output.
Table 6. Address Bits for the AD5308/AD5318/AD5328
A2 (Bit 14) A1 (Bit 13) A0 (Bit 12) DAC Addressed
0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 0 0 DAC E
1 0 1 DAC F
1 1 0 DAC G
1 1 1 DAC H
AD5308/AD5318/AD5328
Rev. F | Page 17 of 28
Control Functions BUF
In the case of a control function, the MSB (Bit 15) is a 1. This is
followed by two control bits, which determine the mode. There
are four different control modes: reference and gain mode, LDAC
mode, power-down mode, and reset mode. The write sequences
for these modes are shown in . Table 7
This controls whether the reference of a group of DACs is
buffered or unbuffered. The reference of the first group of DACs
(A, B, C, and D) is controlled by setting Bit 2, and the second
group of DACs (E, F, G, and H) is controlled by setting Bit 3.
0: unbuffered reference.
1: buffered reference.
Reference and Gain Mode
GAIN
This mode determines whether the reference for each group of
DACs is buffered, unbuffered, or from VDD. It also determines
the gain of the output amplifier. To set up the reference of both
groups, set the control bits to (00), set the GAIN bits, the BUF
bits, and the VDD bits.
The gain of the DACs is controlled by setting Bit 4 for the first
group of DACs (A, B, C, and D) and Bit 5 for the second group
of DACs (E, F, G, and H).
0: output range of 0 V to VREF.
1: output range of 0 V to 2 VREF.
Table 7. Control Words for the AD53x8
D/C Control Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode
GAIN Bits BUF Bits VDD Bits Gain of output amplifier and
1 0 0 x x x x x x x E...H A...D E...H A...D E...H A...D reference selection
LDAC Bits
LDAC
1 0 1 x x x x x x x x x x x 1/0 1/0
Channels
1 1 0 x x x x x H G F E D C B A Power-down
Reset
1 1 1 1/0 x x x x x x x x x x x x Reset
LDAC Mode
02812-031
A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
BIT 0
(LSB)
BIT 15
(MSB)
DATA BITS
A1A2
D/C
LDAC mode controls LDAC, which determines when data is
transferred from the input registers to the DAC registers. There
are three options when updating the DAC registers, as shown in
. Table 8
Figure 32. AD5308 Input Shift Register Contents
02812-032
DATA BITS
A0
BIT 0
(LSB)
BIT 15
(MSB)
A1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0A2D/C
Table 8. LDAC Mode
Bit 15 Bit 14 Bit 13 Bits 12:2 Bit 1 Bit 0 Description
LDAC low
1 0 1 x ... x 0 0
Figure 33. AD5318 Input Shift Register Contents
LDAC high
1 0 1 x ... x 0 1
02812-033
DATA BITS
A0
BIT 0
(LSB)
BIT 15
(MSB)
A1A2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10D11D/C
LDAC single
update
1 0 1 x ... x 1 0
1 0 1 x ... x 1 1 Reserved
Figure 34. AD5328 Input Shift Register Contents LDAC Low (00): This option sets LDAC permanently low,
allowing the DAC registers to be updated continuously.
VDD
These bits are set when VDD is to be used as a reference. The
first group of DACs (A, B, C, and D) can be set up to use VDD by
setting Bit 0, and the second group of DACs (E, F, G, and H) by
setting Bit 1. The VDD bits have priority over the BUF bits.
LDAC High (01): This option sets LDAC permanently high.
The DAC registers are latched and the input registers can
change without affecting the contents of the DAC registers.
This is the default option for this mode.
When VDD is used as the reference, it is always unbuffered and
has an output range of 0 V to VREF regardless of the state of the
GAIN and BUF bits.
LDAC Single Update (10): This option causes a single pulse on
LDAC, updating the DAC registers once.
Reserved (11): reserved.
AD5308/AD5318/AD5328
Rev. F | Page 18 of 28
Power-Down Mode
The individual channels of the AD5308/AD5318/AD5328 can
be powered down separately. The control mode for this is (10).
On completion of this write sequence, the channels that have
been set to 1 are powered down.
Reset Mode
This mode consists of two possible reset functions, as outlined
in Table 9 .
Table 9. Reset Mode
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ... 0 Description
1 1 1 0 x ... x DAC data reset
1 1 1 1 x ... x Data and control reset
DAC Data Reset: On completion of this write sequence, all
DAC registers and input registers are filled with 0s.
Data and Control Reset: This function carries out a DAC data
reset and resets all the control bits (GAIN, BUF, VDD, LDAC, and
power-down channels) to their power-on conditions.
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
LOAD DAC INPUT (LDAC) FUNCTION
Access to the DAC registers is controlled by both the LDAC pin
and the LDAC mode bits. The operation of the LDAC function
can be likened to the configuration shown in . Figure 35
02812-034
LDAC FUNCTION
EXTERNAL LDAC PIN
INTERNAL LDAC MODE
Figure 35. LDAC Function
If the user wishes to update the DAC through software, the
LDAC pin should be tied high and the LDAC mode bits set as
required. Alternatively, if the user wishes to control the DAC
through hardware, that is, the LDAC pin, the LDAC mode bits
should be set to LDAC high (default mode).
Use of the LDAC function enables double-buffering of the DAC
data, and the GAIN, BUF and VDD bits. There are two ways in
which the LDAC function can operate:
Synchronous LDAC: The DAC registers are updated after new
data is read in on the falling edge of the 16th SCLK pulse.
LDAC can be permanently low or pulsed as in . Figure 2
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
DOUBLE-BUFFERED INTERFACE
The AD5308/AD5318/AD5328 DACs all have double-buffered
interfaces consisting of two banks of registers: input and DAC.
The input registers are connected directly to the input shift
register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
registers contain the digital code used by the resistor strings.
When the LDAC pin is high and the LDAC bits are set to (01),
the DAC registers are latched and the input registers can change
state without affecting the contents of the DAC registers. How-
ever, when the LDAC bits are set to (00) or when the LDAC pin
is brought low, the DAC registers become transparent and the
contents of the input registers are transferred to them.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
up to seven of the input registers individually and then, by
bringing LDAC low when writing to the remaining DAC input
register, all outputs will update simultaneously.
These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time LDAC was low. Normally, when LDAC is brought low,
the DAC registers are filled with the contents of the input regis-
ters. In the case of the AD5308/AD5318/AD5328, the part
updates the DAC register only if the input register has been
changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
AD5308/AD5318/AD5328
Rev. F | Page 19 of 28
MICROPROCESSOR INTERFACE
ADSP-2101/ADSP-2103-to-
AD5308/AD5318/AD5328 INTERFACE
Figure 36 shows a serial interface between the AD5308/AD5318/
AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low framing,
and 16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled. The data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5308/AD5318/ AD5328 on the falling edge
of the DAC’s SCLK.
02812-036
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
AD5308/
AD5318/
AD5328*
SYNC
DT
SCLK SCLK
DIN
Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface
68HC11/68L11-to-AD5308/AD5318/AD5328
INTERFACE
Figure 37 shows a serial interface between the AD5308/AD5318/
AD5328 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328,
and the MOSI output drives the serial data line (DIN) of the DAC.
The sync signal is derived from a port line (PC7). The set up
conditions for the correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit is a
0 and its CPHA bit is a 1. When data is being transmitted to the
DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11
is configured as just described, data appearing on the MOSI output
is valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5308/AD5318/AD5328, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
02812-037
68HC11/68L11
*ADDITIONAL PINS OMITTED FOR CLARITY
PC7
AD5308/
AD5318/
AD5328*
SYNC
MOSI
SCK DIN
SCLK
Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface
80C51/80L51-to-AD5308/AD5318/AD5328
INTERFACE
Figure 38 shows a serial interface between the AD5308/AD5318/
AD5328 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5308/AD5318/AD5328, while RxD drives the serial data
line of the part. The SYNC signal is again derived from a bit
programmable pin on the port. In this case, port line P3.3 is used.
When data is transmitted to the AD5308/AD5318/AD5328, P3.3
is taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a format
that has the LSB first. The AD5308/AD5318/AD5328 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
02812-038
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
AD5308/
AD5318/
AD5328*
SYNC
RxD
TxD
DIN
SCLK
Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface
AD5308/AD5318/AD5328
Rev. F | Page 20 of 28
MICROWIRE-to-AD5308/AD5318/AD5328
INTERFACE
Figure 39 shows an interface between the AD5308/AD5318/
AD5328 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5308/AD5318/AD5328 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
02812-039
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
AD5308/
AD5318/
AD5328*
SYNC
SO
SK DIN
SCLK
Figure 39. MICROWIRE-to-AD5308/AD5318/AD5328 Interface
AD5308/AD5318/AD5328
Rev. F | Page 21 of 28
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
The AD5308/AD5318/AD5328 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0.25 V to VDD.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780, ADR381, and REF192 (2.5 V references). For 2.5 V
operation, a suitable external reference is the AD589 or the
AD1580 (1.2 V band gap references). Figure 40 shows a typical
setup for the AD5308/AD5318/AD5328 when using an external
reference.
02812-040
AD5308/AD5318/
AD5328
GND
DIN
SYNC
SERIAL
INTERFACE
V
OUT
EXT
REF
0.1μF
V
REF
ABCD
V
REF
EFGH
A
D780/ADR3811/REF192
W
ITH V
DD
= 5V OR
A
D589/AD1580 WITH
V
DD
= 2.5V
V
DD
= 2.5V TO 5.5V
V
IN
10μF
1μF
SCL
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
Figure 40. AD5308/AD5318/AD5328 Using a 2.5 V or 5 V External Reference
DRIVING VDD FROM THE REFERENCE VOLTAGE
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference input to VDD. As this supply can be noisy
and not very accurate, the AD5308/AD5318/AD5328 can be
powered from a voltage reference. For example, using a 5 V
reference, such as the REF195, works because the REF195
outputs a steady supply voltage for the AD5308/AD5318/
AD5328. The typical current required from the REF195 is a
1 A supply current and ≈ 112 A into the reference inputs (if
unbuffered); this is with no load on the DAC outputs. When the
DAC outputs are loaded, the REF195 also needs to supply the
current to the loads. The total current required (with a10 k
load on each output) is
1.22 mA + 8(5 V/10 k) = 5.22 mA
The load regulation of the REF195 is typically 2.0 ppm/mA,
which results in an error of 10.4 ppm (52 V) for the 5.22 mA
current drawn from it. This corresponds to a 0.003 LSB error at
8 bits and 0.043 LSB error at 12 bits.
BIPOLAR OPERATION USING THE
AD5308/AD5318/AD5328
The AD5308/AD5318/AD5328 have been designed for single-
supply operation, but a bipolar output range is also possible
using the circuit in Figure 41. This circuit gives an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820, the AD8519, or an OP196
as the output amplifier.
02812-041
+5V
–5V
AD820/
AD8519/
OP196
10μF
+6V TO +16V
0.1μF
R1
10kΩ
±5V
R2
10kΩ
GND
GND
V
OUT
REF192
+5V
SERIAL
INTERFACE
SCLK SYNC
DIN
1
μ
F
AD5308/
AD5318/
AD5328
V
REF
ABCD
V
REF
BV
OUT
C
V
OUT
B
V
OUT
A
V
OUT
H
V
IN
V
DD
Figure 41. Bipolar Operation with the AD5308/AD5318/AD5328
The output voltage for any input code can be calculated as
follows:
(
)
()
()
R1RREFIN
R1
RR1DREFIN
V
N
OUT /2
22/ ×−
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡+××
=
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
with
REFIN = 5 V , R1 = R2 = 10 k
(
)
VDV N
OUT 52/10 −×=
OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
The AD5308/AD5318/AD5328 have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise and
safety requirements, or distance, it may be necessary to isolate
the AD5308/AD5318/AD5328 from the controller. This can
easily be achieved by using opto-isolators that provide isolation
in excess of 3 kV. The actual data rate achieved may be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5308/AD5318/AD5328 makes them ideally suited for
use in opto-isolated applications. Figure 42 shows an opto-
isolated interface to the AD5308/AD5318/AD5328 where DIN,
SCLK, and SYNC are driven from optocouplers. The power
supply to the part also needs to be isolated. This is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5308/
AD5318/AD5328.
AD5308/AD5318/AD5328
Rev. F | Page 22 of 28
0.1μF
02812-042
10μF
GND
DIN
AD5308/AD5318/
AD5328
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
F
V
OUT
G
V
OUT
H
V
OUT
A
V
REF
ABCD
V
REF
EFGH
V
DD
V
DD
10kΩ
5V
REGULATOR
SCLK
SYNC
SCLK
V
DD
10kΩ
SYNC
POWER
V
DD
10kΩ
DIN
Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface
DECODING MULTIPLE AD5308/AD5318/AD5328s
The SYNC pin on the AD5308/AD5318/AD5328 can be used in
applications to decode a number of DACs. In this application,
the DACs in the system receive the same serial clock and serial
data but only the SYNC to one of the devices is active at any one
time, allowing access to four channels in this 16-channel sys-
tem. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded-address inputs are changing state.
shows a diagram of a typical setup for decoding
multiple AD5308 devices in a system.
Figure 43
02812-043
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
DIN
SCLK
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
74HC139
1G 1Y0
1Y1
1Y2
1Y3
ENABLE
CODED
ADDRESS 1A
1B
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
AD5308
SCLK
DIN
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
SYNC
V
CC
V
DD
DGND
Figure 43. Decoding Multiple AD5308 Devices in a System
AD5308/AD5318/AD5328
Rev. F | Page 23 of 28
Table 10. Overview of AD53xx Serial Devices
Part No. Resolution DNL VREF Pins Settling Time (μs) Interface Package Pins
SINGLES
AD5300 8 ±0.25 0 (VREF = VDD) 4 SPI SOT-23, MSOP 6, 8
AD5310 10 ±0.50 0 (VREF = VDD) 6 SPI SOT-23, MSOP 6, 8
AD5320 12 ±1.00 0 (VREF = VDD) 8 SPI SOT-23, MSOP 6, 8
AD5301 8 ±0.25 0 (VREF = VDD) 6 2-Wire SOT-23, MSOP 6, 8
AD5311 10 ±0.50 0 (VREF = VDD) 7 2-Wire SOT-23, MSOP 6, 8
AD5321 12 ±1.00 0 (VREF = VDD) 8 2-Wire SOT-23, MSOP 6, 8
DUALS
AD5302 8 ±0.25 2 6 SPI MSOP 10
AD5312 10 ±0.50 2 7 SPI MSOP 10
AD5322 12 ±1.00 2 8 SPI MSOP 10
AD5303 8 ±0.25 2 6 SPI TSSOP 16
AD5313 10 ±0.50 2 7 SPI TSSOP 16
AD5323 12 ±1.00 2 8 SPI TSSOP 16
QUADS
AD5304 8 ±0.25 1 6 SPI MSOP 10
AD5314 10 ±0.50 1 7 SPI MSOP 10
AD5324 12 ±1.00 1 8 SPI MSOP 10
AD5305 8 ±0.25 1 6 2-Wire MSOP 10
AD5315 10 ±0.50 1 7 2-Wire MSOP 10
AD5325 12 ±1.00 1 8 2-Wire MSOP 10
AD5306 8 ±0.25 4 6 2-Wire TSSOP 16
AD5316 10 ±0.50 4 7 2-Wire TSSOP 16
AD5326 12 ±1.00 4 8 2-Wire TSSOP 16
AD5307 8 ±0.25 2 6 SPI TSSOP 16
AD5317 10 ±0.50 2 7 SPI TSSOP 16
AD5327 12 ±1.00 2 8 SPI TSSOP 16
OCTALS
AD5308 8 ±0.25 2 6 SPI TSSOP 16
AD5318 10 ±0.50 2 7 SPI TSSOP 16
AD5328 12 ±1.00 2 8 SPI TSSOP 16
Table 11. Overview of AD53xx Parallel Devices
Part No. Resolution DNL VREF Pins Settling Time (μs) Additional Pin Functions Package Pins
SINGLES BUF GAIN HBEN CLR
AD5330 8 ±0.25 1 6 ✓ ✓ ✓ TSSOP 20
AD5331 10 ±0.50 1 7 ✓ ✓ TSSOP 20
AD5340 12 ±1.00 1 8 ✓ ✓ ✓ TSSOP 24
AD5341 12 ±1.00 1 8 ✓ ✓ ✓ ✓ TSSOP 20
DUALS
AD5332 8 ±0.25 2 6 ✓ TSSOP 20
AD5333 10 ±0.50 2 7 ✓ ✓ ✓ TSSOP 24
AD5342 12 ±1.00 2 8 ✓ ✓ ✓ TSSOP 28
AD5343 12 ±1.00 1 8 ✓ ✓ TSSOP 20
QUADS
AD5334 8 ±0.25 2 6 ✓ ✓ TSSOP 24
AD5335 10 ±0.50 2 7 ✓ ✓ TSSOP 24
AD5336 10 ±0.50 4 7 ✓ ✓ TSSOP 28
AD5344 12 ±1.00 4 8 TSSOP 28
AD5308/AD5318/AD5328
Rev. F | Page 24 of 28
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM PLI ANT TO JEDEC STANDARDS MO-153 - AB
Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 , 2 Temperature Range Package Description Package Option
AD5308ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD5308WARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AD5308/AD5318/AD5328
Rev. F | Page 25 of 28
AUTOMOTIVE PRODUCTS
The AD5308WARUZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirement s of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information
and to obtain the specific Automotive Reliability report for this model.
AD5308/AD5318/AD5328
Rev. F | Page 26 of 28
NOTES
AD5308/AD5318/AD5328
Rev. F | Page 27 of 28
NOTES
AD5308/AD5318/AD5328
Rev. F | Page 28 of 28
NOTES
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02812-0-4/11(F)
