1995-2012 Microchip Technology Inc. DS21127G-page 1
24LCS21
Features:
Completely implements DDC1/DDC2 interface
for monitor identification
Hardware write-protect pin
Single supply with operation down to 2.5V
Low-power CMOS technology:
- 1 mA active current, typical
-10 A standby current, typical at 5.5V
2-wire s erial interfac e bus, I2C comp ati ble (SCL)
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
100 kHz (2.5V) and 400 kHz (5V) compatibility
(SCL)
1,000,000 erase/write cycles ensured
Data rete ntion > 200 years
8-pin PDIP and SOIC package
Available for extended temperature ranges:
Description:
The Microchip Technology Inc. 24LC S21 is a 128 x 8-bit
dual-mode Electrically Erasable PROM. This device is
designed for use in applications requiring storage and
serial transmission of configuration and control informa-
tion. Two modes of operation have been implemented:
Transmit-Only mode and Bidirectional mode. Upon
power-up, the devi ce will be in the Transmit-Only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I2C protoc ol.
The 24LCS21 also enables the user to write-protect the
entire memory contents using its write-protect pin. The
24LCS21 is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.
Package Types
Block Diagram
- Commercial (C): 0°C to +70°C
- Industrial (I) -40°C to +85°C
24LCS21
SOIC
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
NC
NC
WP
VSS
24LCS21
PDIP
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
NC
NC
WP
VSS
I/O
Control
Logic
EEPROM
Array
Page Latches
HV Generator
Sense Amp
R/W Control
Memory
Control
Logic XDEC
YDEC
VCC
VSS
SDA SCL
VCLK
WP
1K 2.5V Dual Mode I2C Serial EEPROM
Not recommended for new designs –
Please use 24LCS21A.
24LCS21
DS21127G-page 2 1995-2012 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ...................................... ...... ..... ...... ............................ ...... ..... ...... .... -0.6V to VCC + 1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied................................................................................................-40C to +125C
Soldering temperature of leads (10 seconds) .......................................................................................................+300C
ESD protection on all pins4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal operati on of the devic e at thes e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS VCC = +2.5V to 5.5V
Commercial (C): TA = 0C to +70C
Industrial (I): TA =-40C to +85C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High-level in put voltage
Low-level input voltage VIH
VIL 0.7 VCC 0.3 VCC V
V
Input levels on VCLK pin:
High-level in put voltage
Low-level input voltage VIH
VIL 2.0 0.8
0.2 VCC V
VVCC 2.7V (Note 1)
VCC < 2.7V (Note 1)
Hysteresis of Schmitt Trigger inputs VHYS .05 VCC —V(Note 1)
Low-level output voltage VOL10.4 V IOL = 3 mA, VCC = 2.5V (Note 1)
Low-level output voltage VOL20.6 V IOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 AVIN = 0.1V to VCC
Output lea ka ge current ILO -10 10 AVOUT = 0.1V to VCC
Pin capacitance (all inputs/outputs) CINT 10 pF VCC = 5.0V (Note 1),
TA = 25C, FCLK = 1 MHz
Operati ng current ICC Write
ICC Read
3
1mA
mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —30
100 A
AVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
1995-2012 Microchip Technology Inc. DS21127G-page 3
24LCS21
TABLE 1-2: AC CHARACTERISTICS
Parameter Symbol VCC = 2.5-5.5V VCC = 4.5-5.5V Units Remarks
Min Max Min Max
Clock frequency FCLK 01000400kHz
Clock high time THIGH 4000 600 ns
Clock low time TLOW 4700 1300 ns
SDA and SCL rise time TR 1000 300 ns (Note 1)
SDA and SCL fall time TF 300 300 ns (Note 1)
Start condition hold time THD:STA 4000 600 ns After this period the first
clock pulse is generated
Start condition setup time TSU:STA 4700 600 ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0—0ns(Note 2)
Data input setup time TSU:DAT 250 100 ns
Stop condition setup time TSU:STO 4000 600 ns
Output valid from clock TAA 3500 900 ns (Note 2)
Bus free time TBUF 4700 1300 ns Time the bus must be free
before a new transmission
can st a rt
Output fall time from VIH
minimum to VIL maximum TOF 250 20 + 0.1
CB250 ns (Note 1), CB 100 pF
Input filter spike suppression
(SDA and S CL pins) TSP —10050ns(Note 3)
Write cycle time TWR 10 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA 2000 1000 ns
VCLK high time TVHIGH 4000 600 ns
VCLK low time TVLOW 4700 1300 ns
VCLK setup time TVHST 0—0ns
VCLK hold time TSPVL 4000 600 ns
Mode transition time TVHZ 500 500 ns
Transmit-onl y po wer-up time TVPU 0—0ns
Input filter spike suppression
(VCLK pin) TSPV 100 100 ns
Endurance 1M 1M cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by charact erization. For endura nce estimates in a speci fic
applic atio n, pl eas e c ons ul t the Total Endur anc e Mo de l wh ic h ca n be ob t a i ned from Mic roc hip’s web site
at www.microchip.com.
24LCS21
DS21127G-page 4 1995-2012 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21 operates in two modes, the Transmit-
Only mode and the Bidirectional mode. There is a
sep arate two-wire pro tocol to support e ach mode, each
having a separate clock input but sharing a common
data line (SDA). The device enters the Transmit-Only
mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the VCLK pin. Th e devi ce wi l l re ma i n in
this mode until a valid high-to-low transition is placed
on the SCL input. When a valid transition on SCL is
recognized, the device will switch into the Bidirectional
mode. The only way to switch the device back to the
Transmit-Only mode is to remove power from the
device.
2.1 Transmit-Only Mode
The dev ic e w il l p ower-up in the Transmit-On ly mode at
address 00h. This mode supports a unidirectional two-
wire protocol for continuous transmission of the
content s of th e memory a rray. This devic e requires th at
it be initialized prior to valid data being sent in the
Transmit-Only mode (see Initialization Procedure,
below). In this mode, data is transmitted on the SDA pin
in 8-bit bytes, with each byte f ollowed by a ninth, nul l bit
(Figure 2-1). The clock source for the Transmit-Only
mode i s prov ided on the VCLK pin, and a dat a bit is out-
put on the rising ed ge on this pin. The e ight bit s in eac h
byte are tran smitted Most Sig nificant bit first. Eac h byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal Address Pointers will wrap around to the
first memory location (00h) and continue. The
Bidirectional mode clock (SCL) pin must be held high
for the device to remain in the Transmit-Only mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-Onl y mode. Nine clock cy cles on th e VCLK pin mus t
be give n to t he device f or it to p erform i nternal s ynchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit in address 00h.
(Figure 2-2).
FIGURE 2-1: TRANSMIT -ONLY MODE
FIGURE 2-2: DEVICE INITI ALIZATION
SCL
SDA
VCLK
TVAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
TVLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-impedance for 9 clock cycles
TVPU
12 891011
SCL
SDA
VCLK
VCC
1995-2012 Microchip Technology Inc. DS21127G-page 5
24LCS21
3.0 BIDIRECTIONAL MODE
The 24LCS21 can be switched into the Bidirectional
mode (Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is di sregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidi rectional data
tran sm is si on pr o t oc ol (I 2C). In this protocol, a device
that se nds data on the bus is de fined to be the transm it-
ter and a device that receives data from the bus is
defi ned t o be the r ece iver. The bu s must be con trol led
by a master device that generates the Bidirectional
mode c lock (SCL), co ntrols acce ss to the bu s and ge n-
erates the Start and Stop conditions, while the
24LCS2 1 act s as the sla ve. Both mast er a nd sla ve ca n
operate as transmitter or receiver, but the master
device determines which mode is activated.
In this mode, the 24LCS21 only responds to
commands for device 1010 000X’.
3.1 Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stab le whene ver the cl ock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Fig ure 3-2).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA TRANSFER (B)
A hig h- to - lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1: MODE TRANSITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bidirectional mode
TVHZ
Transmit-Only mode
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA
24LCS21
DS21127G-page 6 1995-2012 Microchip Technology Inc.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of t he cl oc k si gna l. There is one clock puls e per
bit of data.
Each da t a tra nsfer is init iate d with a Start conditi on an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
first-out (FIFO) fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. Th e mast er device mus t ge nera te a n ex tra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknowledge bi t o n t he las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
Note: Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.
Note: The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
TSU:STA THD:STA
VHYS
TSU:STO
Start Stop
SCL
SDA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TR
1995-2012 Microchip Technology Inc. DS21127G-page 7
24LCS21
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master
transmi ts t he slav e addre ss co nsis ting of a 7 -bit dev ice
code ‘1010000’ for the 24LCS21.
The eigh th bit of th e slave a ddress determ ines wheth er
the master device wants to read or write to the
24LCS21 (Figure 3-5).
The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-5: CONTROL BYTE
ALLOCATION
Operation Slave Address R/W
Read 1010000 1
Write 1010000 0
Slave Address
101000 0
R/WA
Start Read/Write
24LCS21
DS21127G-page 8 1995-2012 Microchip Technology Inc.
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit,
which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has gen erated an Ackno wledge bit durin g
the ninth clock cycle. Therefore, the next byte
tran smit ted by the ma ster is the word add res s and wi ll
be written into the Address Pointer of the 24LCS21.
After receiving another Acknowledge signal from the
24LCS2 1, the master de vice will tran smit the dat a word
to be written into the addressed memory location. The
24LCS21 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS21 will not
generate Acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during comman d and data transfer in order to pr ogram
the device. This applies to both byte write and page
write operation. Note, however , that the VCLK is ignored
during the self-timed program operation. Changing
VCLK from high-to-low during the self-timed program
operation will not halt programming of the device.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
Bus Ac tivity
SDA Line
Bus Ac tivity
Control
Byte Word
Address Data S
T
O
P
S
T
A
R
T
A
C
K
SP
A
C
K
A
C
K
VCLK
Activity
TSPVL
TSU:STOTHD:STA
TVHST
VCLK
SDA
IN
SCL
1995-2012 Microchip Technology Inc. DS21127G-page 9
24LCS21
4.2 Page Write
The write control byte, word address and the first data
byte a re transm itted t o the 2 4LCS21 i n the same w ay
as in a byte write. But instead of generating a Stop
condition, the master transmit s up to eight dat a bytes to
the 24LCS21, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the rece ipt of eac h word, the three l ower order Add ress
Pointer bits are internally incremented by one. The
higher order five bits of the word address remains
const a nt. If the master s ho uld tra ns mi t m ore tha n eig ht
words prior to generating the Stop condition, the
address counter will roll over and the previously
receive d dat a wil l be overwri tten. As with the by te writ e
operation, once the Stop condition is received an
internal write cycle will begin (Figure 5-2).
It is required that VCLK be held at a logic high level
during comman d and data transfer in order to pr ogram
the device. This applies to both byte write and page
write operation. Note, however , that the VCLK is ignored
during the self-timed program operation. Changing
VCLK from high-to-low during the self-timed program
operation will not halt programming of the device.
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the nu mb er o f by tes ac tua ll y
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to the next page as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
24LCS21
DS21127G-page 10 1995-2012 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be us ed to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1: ACKNOWLEDGE
POLLING FLOW
FIGURE 5-2: PAG E WRITE
Did De vi ce
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
Bus
Master
SDA Line
Bus
Control
Byte Word
Address S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
Activity
Activity A
C
K
A
C
K
Data n + 1 Data n + 7
Data (n)
P
S
VCLK
1995-2012 Microchip Technology Inc. DS21127G-page 11
24LCS21
6.0 WRITE PROTECTION
When using the 24LCS21 in the Bid irectiona l mode, the
VCLK pin operates as th e wri te-p rote ct co ntro l pin . Set-
ting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
arra y. C o nn e cti ng t h e VCLK pin to VSS would allow the
24LCS21 to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-Only mode.
Additionally, pin 3 performs a flexible write-protect
function. The 24LCS21 contains a write protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP pin. Until th is fuse is set, the 24LCS21
is always write enabled (if VCLK = 1). After the fuse is
set, the w rite capab ility o f the 2 4LCS21 is det ermin ed
by WP (Figure 6-1).
TABLE 6-1: WRITE-PROTECT TRUTH
TABLE
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave a ddress is set to one. The re are three bas ic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LCS21 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would ac ce ss d at a from address n + 1. U pon rec ei pt of
the slav e address with R /W bit set to one, the 24LCS2 1
issues an ackn owledge an d trans mits the eight -bit dat a
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21
discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS
READ
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, first the wo rd address must
be set. This is done b y sending the word address to the
24LCS21 as part of a write operation. After the word
address is sent, the master generat es a Start co nditio n
following the acknowledge. This terminates the write
operatio n, but not before the internal Address Pointer is
set. Then t he ma ster issu es the cont rol byte ag ain but
with the R/W bit set to a one. The 24LCS21 will then
issue an acknowledge and transmits the eight-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21
discontinues transmission (Figure 7-2).
VCLK WP Add. 7Fh
Written Mode
0XXRead-only
1XNo R/W
11/open Yes R/W
10Yes Read-only
Control
A
C
K
S
S
T
A
R
T
S
T
O
P
P
Byte Data n
Bus Activit y
SDA Line
Bus Ac tivity A
C
K
N
O
Master
10100001
24LCS21
DS21127G-page 12 1995-2012 Microchip Technology Inc.
FIGURE 7-2: RANDOM READ
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LCS21 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LCS21 to transmit the next sequentially
addressed 8-bit word (Figure 8-1).
To provide sequential reads, the 24LCS21 contains an
internal Address Pointer whic h is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operati on .
7.4 Noise Protection
The 24LC S21 emplo ys a VCC thresh old detector ci rcuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filte r circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
Bus Activity
Master
SDA Line
Bus Activit y
Control
Byte Word
Address Da ta n
A
C
K
S
T
A
R
T
N
O
S
T
A
R
Control
Byte
A
C
K
A
C
KA
C
K
SS
T
P
S
T
O
P
10100000 00000111
1995-2012 Microchip Technology Inc. DS21127G-page 13
24LCS21
8.0 PIN DESCRIPTIONS
TABLE 8-1: PIN FUNCTION TABLE
8.1 SDA
This p in is use d to transfer addresses and data into and
out of the device , when the devi ce is in th e Bidirectiona l
mode. In the Transmit-Only mode, which only allows
data to be read from the device, dat a is also tr ansferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10 K for 100 kHz, 2 K for 400 kHz).
For normal data t ransfer in the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2 SCL
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit-Only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-Only mode.
8.3 VCLK
This pin is the clock input for the Transmit-Only mode
(DDC1). In the Transmit-Only mode, each bit is clocked
out on the ris ing edg e of this si gnal. In the Bidire ctiona l
mode, a high logic level is req uired on this pin to enabl e
write capability.
8.4 WP
This pin is used for flexible write protection of the
24LCS21. When the last memory location (7Fh) is
written with any data, this pin is enabled and
determines the write capability of the 24LCS21
(Figure 6-1).
FIGURE 8-1: SEQUENTI AL READ
Name Function
WP Write-protect (active low)
VSS Ground
SDA Ser ial Ad dress/Data I/O
SCL Serial Clock (Bidirectional mode)
VCLK Serial Clock (Transmit-Only mode)
VCC +2.5V to 5.5V Power Supply
NC No Connection
A
C
K
P
Bus Activit y
Master
SDA Line
Bus Activity
Control
Byte
Data n Data n+1 Data n+2 Data n+X
A
C
K
A
C
K
A
C
KN
O
A
C
K
S
T
O
P
24LCS21
DS21127G-page 14 1995-2012 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXNNN
8-Lead PDIP
XXXXXXXX
YYWW 017
Example
24LCS21
0410
8-Lead SOIC (.150”)
XXXXXXXX
XXXXYYWW
NNN
Example
24LCS21
/SN0410
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the ful l Micro chip p ar t numbe r cannot be marke d on one li ne, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
1995-2012 Microchip Technology Inc. DS21127G-page 15
24LCS21
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
B1
B
A1
A
L
A2
p
E
eB
c
E1
n
D
1
2
Units INCHES*MILLIMETERS
Dimens i on Limi ts MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thic kness c.008 .012 .015 0.20 0.29 0.38
Upper Lea d Width B1 .04 5 .058 .070 1.14 1 .46 1. 78
Lower Lea d Width B .014 .018 .022 0.36 0.46 0.56
Overall Row S pacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top 5 10 15 5 10 15
Mold Draft Angle Bottom 5 10 15 5 10 15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
§ Significant Characteristic
Note: For th e mo s t c urr e nt pac kag e d r awi n gs , plea se se e th e M ic roc hi p Pa c ka gi n g Spec if ic at i on lo c ate d
at http://www.microchip.com/packaging
24LCS21
DS21127G-page 16 1995-2012 Microchip Technology Inc.
8-Lead Plastic Small Outl ine (SN) – N arrow, 150 mil Body (SOIC)
Foot A ngle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146
E1
Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27
.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
c
45
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microc hi p.c om/packaging
1995-2012 Microchip Technology Inc. DS21127G-page 17
24LCS21
APPENDIX A: REVISION HISTORY
Revision E
Added note to page 1 header (Not recommended for
new designs).
Added Section 9.0: Package Marking Information.
Added On-li ne Supp ort p ag e.
Updated document format.
Revision F
Revised Section 8.4
Revision G
Added a note to each package outline drawing.
24LCS21
DS21127G-page 18 1995-2012 Microchip Technology Inc.
NOTES:
1995-2012 Microchip Technology Inc. DS21127G-page 19
24LCS21
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. This web si te i s used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
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Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
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will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
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“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is a vailable through the web si te
at: http://microchip.com/support
24LCS21
DS21127G-page 20 1995-2012 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please li st the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
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Address
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Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21127G24LCS21
1. What are the best featu res of this document ?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1995-2012 Microchip Technology Inc. DS21127G-page 21
24LCS21
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: 24LCS21: Dual Mode I2C Serial EEPROM
24LCS21T: Dual Mode I2C Serial EEPROM (Tape and Reel)
Temperature
Range: Blank = 0C to +70C
I= -40C to +85C
Package: P = Plastic DIP (300 mi l Body ), 8-le ad
SN = Plastic SOIC (150 mil Body), 8-lead
.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24LCS21
DS21127G-page 22 1995-2012 Microchip Technology Inc.
NOTES:
1995-2012 Microchip Technology Inc. DS21127G-page 23
Information contained in this publication regarding device
applications a nd the lik e is p rovided on ly for your convenien ce
and may be supers eded by update s . I t is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC 32 logo, rfPIC, SST, SST Logo, SuperF lash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE , In - Circuit Seria l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germ any II GmbH & C o. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1995-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767313
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS21127G-page 24 1995-2012 Microchip Technology Inc.
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