PHB191NQ06LT,118 - NXP Semiconductors / Philips Semiconductors

PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Rev. 01 — 05 May 2004 Product data

1. Product proﬁle

1.1 Description

Logic level N-channel enhancement mode ﬁeld-effect transistor in a plastic package

using TrenchMOS™ technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

2. Pinning information

[1] It is not possible to make connection to pin 2 of the SOT404 package.

■Logic level threshold ■Very low on-state resistance.

■Motors, lamps, solenoids ■Uninterruptible power supplies

■DC-to-DC converters ■General industrial applications.

■VDS ≤55 V ■ID≤75 A

■Ptot ≤300 W ■RDSon ≤3.7 mΩ.

Table 1: Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simpliﬁed outline and symbol

Pin Description Simpliﬁed outline Symbol

1 gate (g)

SOT78 (TO-220AB) SOT404 (D2-PAK)

2 drain (d) [1]

3 source (s)

mb mountingbase;

connected to

drain (d)

MBK106

MBK116

MBB076

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 2 of 13

3. Ordering information

4. Limiting values

Table 2: Ordering information

Type number Package

Name Description Version

PHP191NQ06LT TO-220AB Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78

PHB191NQ06LT D2-PAK Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage (DC) 25 °C≤Tj≤175 °C - 55 V

VDGR drain-gate voltage (DC) 25 °C≤Tj≤175 °C; RGS =20kΩ-55V

VGS gate-source voltage (DC) - ±15 V

IDdrain current (DC) Tmb =25°C; VGS =10V;Figure 2 and 3-75A

Tmb = 100 °C; VGS =10V;Figure 2 -75A

IDM peak drain current Tmb =25°C; pulsed; tp≤10 µs; Figure 3 - 240 A

Ptot total power dissipation Tmb =25°C; Figure 1 - 300 W

Tstg storage temperature −55 +175 °C

Tjjunction temperature −55 +175 °C

Source-drain diode

ISsource (diode forward) current (DC) Tmb =25°C - 75 A

ISM peak source (diode forward) current Tmb =25°C; pulsed; tp≤10 µs - 240 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

avalanche energy unclamped inductive load; ID=75A;

tp= < 0.21 ms; VDD ≤55 V; RGS =50Ω;

VGS = 10 V; starting Tj=25°C

- 560 mJ

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 3 of 13

Fig 1. Normalized total power dissipation as a

function of mounting base temperature. Fig 2. Normalized continuous drain current as a

function of mounting base temperature.

Tmb =25°C; IDM is single pulse; VGS =10V

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa16

120

0 50 100 150 200

(°C)

der

(%)

03aq99

120

0 50 100 150 200

Tmb (°C)

Ider

(%)

Pder Ptot

Ptot 25 C

()

----------------------- 100%×=Ider ID

ID25C

()

------------------- 100%×=

03ar01

102

103

1 10 102

VDS (V)

(A)

100 ms

10 ms

Limit RDSon = VDS / ID

1 ms

tp = 10 µs

100 µs

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 4 of 13

5. Thermal characteristics

5.1 Transient thermal impedance

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to mounting base Figure 4 - - 0.5 K/W

Rth(j-a) thermal resistance from junction to ambient

SOT78 vertical in still air - 60 - K/W

SOT404 mounted on a printed-circuit

board; vertical in still air;

minimum footprint.

- 50 - K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

03ar00

10-2

10-1

10-4 10-3 10-2 10-1 1

tp (s)

Zth(j-mb)

(K/W)

single pulse

δ = 0.5

0.2

0.1

0.05

0.02

δ =

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 5 of 13

6. Characteristics

Table 5: Characteristics

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown voltage ID= 250 µA; VGS =0V

Tj=25°C 55--V

Tj=−55 °C 50--V

VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V

GS;Figure 9 and 10

Tj=25°C 1 1.5 2 V

Tj= 175 °C 0.5 - - V

Tj=−55 °C - - 2.2 V

IDSS drain-source leakage current VDS =55V; V

GS =0V

Tj=25°C --1µA

Tj= 175 °C - - 500 µA

IGSS gate-source leakage current VGS =±15 V; VDS = 0 V - 2 100 nA

RDSon drain-source on-state resistance VGS = 10 V; ID=25A;Figure 7 and 8

Tj=25°C - 3.1 3.7 mΩ

Tj= 175 °C - - 7.4 mΩ

VGS =5V; I

D=25A;Figure 7 and 8- 3.5 4.2 mΩ

VGS = 4.5 V; ID=25A;Figure 8 - - 4.4 mΩ

Dynamic characteristics

Qg(tot) total gate charge ID=25A;V

DD =44V;V

GS =5V;Figure 13 - 95.6 - nC

Qgs gate-source charge - 17.2 - nC

Qgd gate-drain (Miller) charge - 37.6 - nC

Ciss input capacitance VGS =0V; V

DS = 25 V; f = 1 MHz;

Figure 11 -7665-pF

Coss output capacitance - 1045 - pF

Crss reverse transfer capacitance - 465 - pF

td(on) turn-on delay time VDD =30V; R

L= 1.2 Ω;

VGS =5V;R

G=10Ω-63-ns

trrise time - 232 - ns

td(off) turn-off delay time - 273 - ns

tffall time - 178 - ns

Source-drain diode

VSD source-drain (diode forward) voltage IS= 25 A; VGS =0V;Figure 12 - 0.79 1.2 V

trr reverse recovery time IS= 20 A; dIS/dt = −100 A/µs; VGS =0V - 78 - ns

Qrrecovered charge - 171 - nC

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 6 of 13

Tj=25°CT

j=25°C and 175 °C; VDS >IDxR

DSon

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

Tj=25°C

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values. Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

03ar02

160

240

0 0.5 1 1.5 2

VDS (V)

(A)

Tj = 25 °C

VGS = 2. 4 V

10 V

3.2 V

2.8 V

4 V

5 V

3.6 V

03ar04

0123

VGS (V)

(A) VDS > ID x RDSon

Tj = 175 °C25 °C

03ar03

0 80 160 240

ID (A)

RDSon

(mΩ)VGS = 3.2 VTj = 25 °C

10 V

5 V

3.6 V

4 V

03ne89

0.5

1.5

-60 0 60 120 180

Tj (°C)

aRDSon

RDSon 25 C

()

-----------------------------

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 7 of 13

ID= 1 mA; VDS =V

GS Tj=25°C; VDS =5V

Fig 9. Gate-source threshold voltage as a function of

junction temperature. Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

VGS = 0 V; f = 1 MHz

Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.

03aa33

0.5

1.5

2.5

-60 0 60 120 180

Tj (°C)

VGS(th)

(V)

max

typ

min

03aa36

-6

-5

-4

-3

-2

-1

0123

VGS (V)

(A)

maxtypmin

03ar06

102

103

104

105

10-1 1 10 102

VDS (V)

(pF)

Ciss

Coss

Crss

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 8 of 13

Tj=25°C and 175 °C; VGS =0V I

D= 25 A; VDD = 14 Vand 44 V

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

values.

Fig 13. Gate-source voltage as a function of gate

charge; typical values.

03ar05

0 0.3 0.6 0.9 1.2

VSD (V)

(A)

Tj = 25 °C

175 °C

VGS = 0 V

03ar07

0 50 100 150 200

QG (nC)

VGS

(V) ID = 25 A

Tj = 25 °C

VDD = 44 V

14 V

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 9 of 13

7. Package outline

Fig 14. SOT78 (TO-220AB).

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT78 SC-463-lead TO-220AB

123

L1(1)

0 5 10 mm

scale

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78

DIMENSIONS (mm are the original dimensions)

Note

1. Terminals in this zone are not tinned.

UNIT A1b1D1ep

mm 2.54

AbD

cL2

max.

3.0 3.8

3.6

15.0

13.5 3.30

2.79 3.0

2.7 2.6

2.2

0.7

0.4 15.8

15.2

0.9

0.7 1.3

1.0

4.5

4.1 1.39

1.27 6.4

5.9 10.3

9.7

L1(1)

00-09-07

01-02-16

mounting

base

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 10 of 13

Fig 15. SOT404 (D2-PAK)

UNIT A

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

A1D1

max. EeL

pHDQc

2.54 2.60

2.20

15.80

14.80

2.90

2.10

11 1.60

1.20 10.30

9.70

4.50

4.10 1.40

1.27 0.85

0.60 0.64

0.46

DIMENSIONS (mm are the original dimensions)

SOT404

0 2.5 5 mm

scale

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads

(one lead cropped) SOT404

e e

mounting

base

99-06-25

01-02-12

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 11 of 13

8. Revision history

Table 6: Revision history

Rev Date CPCN Description

01 20040505 - Product data (9397 750 13168)

9397 750 13168

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 12 of 13

9397 750 13168

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 01 — 05 May 2004 12 of 13

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

9. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

12. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 05 May 2004 Document order number: 9397 750 13168

Contents

Philips Semiconductors PHP/PHB191NQ06LT

N-channel TrenchMOS™ logic level FET

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

5.1 Transient thermal impedance . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

9 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 12

10 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12