S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW
1-1
1PRODUCT OVERVIEW
OVERVIEW
Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
—Efficient register-oriented architecture
—Selectable CPU clock sources
—Idle and Stop power-down mode release by interrupt
—Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MICROCONTROLLER
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 single-chip CMOS microcontroller is fabricated using a
highly advanced CMOS process and is based on Samsung's newest CPU architecture.
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is the microcontroller which has mask-programmable ROM.
The S3P80A4/P80A8/P80A5/P80B4/P80B8/P80B5 is the microcontroller which has one-time-programmable
EPROM.
Using a proven modular design approach, Samsung engineers developed the
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 by integrating the following peripheral modules with the powerful
SAM87 RC core:
—Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins.
—Internal LVD circuit and eight bit-programmable pins for external interrupts.
—One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).
—One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.
—One 8-bit counter with auto-reload function and one-shot or repeat control.
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is a versatile general-purpose microcontroller which is
especially suitable for use as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP
package.
PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
1-2
FEATURES
CPU
•SAM87RC CPU core
Memory
• Program memory (ROM)
– S3C80A4/C80B4: 4-Kbyte
(0000H–0FFFH)
– S3C80A8/C80B8: 8-Kbyte
(0000H–1FFFH)
– S3C80A5/C80B5: 15,872 byte
(0000H–3E00H)
•Data memory: 256-byte RAM
Instruction Set
•78 instructions
•IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
•500 ns at 8-MHz fOSC (minimum)
Interrupts
•13 interrupt sources with 10 vector.
• 5 level, 10 vector interrupt structure
I/O Ports
•Two 8-bit I/O ports (P0-P1) and one 3-bit port
(P2) for a total of 19 bit-programmable pins
•Eight input pins for external interrupts
Carrier Frequency Generator
•One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
Back-up mode
•When VDD is lower than VLVD, the chip enters
Back-up mode to block oscillation and reduce the
current consumption.
Timers and Timer/Counters
•One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
function
•One 8-bit timer/counter (Timer 0) with two
operating modes; Interval mode and PWM mode.
•One 16-bit timer/counter with one operating
modes; Interval mode
Low Voltage Detect Circuit
•Low voltage detect for reset or Back-up mode.
• Low level detect voltage
– S3C80A4/C80A8/C80A5:
2.20 V (Typ) ± 200 mV
– S3C80B4/C80B8/C80B5:
1.90 V (Typ) ± 200 mV
Auto Reset Function
•Reset occurs when stop mode is released by P0.
•When a falling edge is detected at Port 0 during
Stop mode, system reset occurs.
Operating Temperature Range
• –40°C to + 85°C
Operating Voltage Range
•1.7 V to 3.6 V at 4 MHz fOSC
•2.0 V to 3.6 V at 8 MHz fOSC
Package Type
•24-pin SOP/SDIP
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
8-bit
Basic
Timer
P0.0-P0.7/INT0-INT4 P1.0-P1.7
Port I/O and Interrupt
Control
SAM87RI CPU
Internal Bus
XIN
XOUT
Port 0(INTR) Port 1
Main
OSC P2.0/T0PWM
15-Kbyte ROM 256-Byte
Register File
8-bit
Timer/
Counter
16-bit
Timer/
Counter
Port 2
Carrier
Generator
(Counter A)
P2.1/REM
P2.2
LVD
TEST
Figure 1-1. Block Diagram
PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
1-4
PIN ASSIGNMENTS
VSS
XIN
XOUT
TEST
P0.0/INT0/INTR
P0.1/INT1/INTR
RESETRESET/P0.2/INT2/INTR
P0.3/INT3/INTR
P0.4/INT4/INTR
P0.5/INT4/INTR
P0.6/INT4/INTR
P0.7/INT4/INTR
S3C80A4/C80A8/C80A5
C80B4/C80B8/C80B5
24-SOP/SDIP
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
VDD
P2.2
P2.1/REM/SCLK
P2.0/T0PWN/T0CK/SDAT
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
24
23
22
21
20
19
18
17
16
15
14
13
Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin
Names Pin
Type Pin
Description Circuit
Type 24-Pin
Number Shared
Functions
P0.0–P0.7 I/O I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually
as external interrupt inputs with noise filters,
interrupt enable/ disable, and interrupt
pending control. Interrupt with Reset(INTR)
is assigned to Port 0.
1 5–12 INT0 – INT4/INTR
P1.0–P1.7 I/O I/O port with bit-programmable pins.
Configurable to input mode or output mode.
Pin circuits are either push-pull or n-
channel open-drain type. Pull-up resistors
are assignable by software.
2 13–20
P2.0
P2.1
P2.2
I/O 3-bit I/O port with bit-programmable pins.
Configurable to input mode, push-pull
output mode, or n-channel open-drain
output mode. Input mode with pull-up
resistors are assignable by software. The
two pins of port 2 have high current drive
capability.
3
4
5
21–23 REM/T0CK
XIN, XOUT –System clock input and output pins –2, 3 –
TEST ITest signal input pin (for factory use only;
must be connected to VSS). – 4 –
VDD –Power supply input pin – 24 –
VSS –Ground pin – 1 –
PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
1-6
PIN CIRCUITS
V
DD
Pull-up
Enable
V
DD
Input/Output
Pull-up
Resistor
Output
Disable
Data
V
SS
Noise
filter
External
Interrupt
Stop INTR (Interrupt with
RESET)
Figure 1-3. Pin Circuit Type 1 (Port 0)
NOTE
Interrupt with reset (INTR) is assigned to port 0 of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port
0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs
automatically. It is designed for a application which are using “stop mode” like remote controller. If stop
mode is not used, INTR do not operates and it can be discarded.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW
1-7
V
DD
Pull-up
Enable
V
DD
Input/Output
Pull-up
Resistor
Output Disable
Data
V
SS
Noise
filter
Normal
Input
Open-drain
Figure 1-4. Pin Circuit Type 2 (Port 1)
VDD
Pull-up
Enable
VDD
P2.0/T0PWN
Pull-up Resistor
(Typical 21K
Ω
)
Open-drain
Port 2.0 Data
VSS
M
U
X
P2.0 Input
Output
Disable
Data
T0_PWN
P2CON.0
Figure 1-5. Pin Circuit Type 3 (P2.0)
PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
1-8
VDD
Pull-up
Enable
VDD
P2.1/REM/T0CK
Pull-up
Resistor
(Typical 21KΩ)
Open-Drain
Port 2.1 Data
VSS
P2.1 Input
M
U
X
P2CON.1
Data
Output
Disable
Noise filterT0CK
CAOF(CACON.0)
Carrier On/Off (P2.5)
Figure 1-6. Pin Circuit Type 4 (P2.1)
VDD
Pull-up
Enable
VDD
In/Out
Pull-up Resistor
(Typical 21KΩ)
Open-drain
VSS
Normal Input
Output
Disable
Data
Figure 1-7. Pin Circuit Type 5 (P2.2)
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-1
2ADDRESS SPACES
OVERVIEW
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller has two types of address space:
—Internal program memory (ROM)
—Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3C80A5/C80B5 has an internal 15,872 byte programmable ROM, the S3C80A8/C80B8 has an internal 8-
Kbyte programmable ROM, and the S3C80A4/C80B4 has an internal 4-Kbyte programmable ROM. An external
memory interface is not implemented. The 256-byte physical RAM space is expanded into an addressable area
of 320 bytes by the use of addressing modes.
There are 312 mapped registers in the internal register file. Of these, 272 are for general-purpose use. (This
number includes a 16-byte working register common area that is used as a " scratch area" for data operations, a
256 prime register area that is used for general purpose and stack operation). Eighteen 8-bit registers are used
for CPU and system control and 22 registers are mapped peripheral control and data registers.
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-2
PROGRAM MEMORY (ROM)
Program memory stores program code or table data. The S3C80A5/C80B5 has 15, 872 bytes of internal
programmable program memory, and the program memory address range is therefore 0000H-3E00H of ROM .
The S3C80A8/C80B8 has 8-Kbyte(0000H-1FFFH) of internal programmable program memory and the
S3C80A4/C80B4 has 4-Kbyte(0000H-0FFFH) of internal programmable program memory (see Figure 2-1).
The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you do use the vector address area to store program
code, be careful to avoid overwriting vector addresses stored in these locations.
The ROM address at which program execution starts after a reset is 0100H.
15,872
15-Kbyte
ROM
8-Kbyte
ROM
4-Kbyte
ROM
Interrupt
Vector Area
8,191
4,095
255
0
3E00H
1FFFH
0FFFH
0FFH
0H
S3C80A4/C80B4
(Decimal) (HEX)
S3C80A8/C80B8
S3C80A5/C80B5
Figure 2-1. Program Memory Address Space
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-3
REGISTER ARCHITECTURE
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 register file has 312 registers. The upper 64 bytes register
files are addressed as system control register and working register. The lower 192-byte area of the physical
register file(00H–BFH) contains freely-addressable, general-purpose registers called prime registers. It can be
also used for stack operation.
The extension of register space into separately addressable sets is supported internally by addressing mode
restrictions.
Specific register types and the area (in bytes) they occupy in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
internal register space are summarized in Table 2-1.
Table 2-1. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Register Type Summary
Register Type Number of Bytes
General-purpose registers (including the 16-byte
common working register area, the 256-byte prime
register area.)
272
CPU and system control registers 18
Mapped clock, peripheral, and I/O control and data
registers 22
Total Addressable Bytes 312
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-4
Set 2Set 1
~
BFH
00H
Prime Data Registers
(All Addressing Modes)
General-Purpose
Data Register
(Indirect Register or
Indexed addressing
modes or
stack operations)
FFH
C0H
192-Bytes
FFH
C0H
System and Peripheral
Control Registers
(Register Addressing
Mode)
System Registers
(Register Addressing
Mode)
64-Bytes
256-Bytes
~ ~
Working Registers
(Working Register
Addressing Mode)
CFH
D0H
DFH
E0H
Figure 2-2. Internal Register File Organization
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-5
REGISTER PAGE POINTER (PP)
The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by
the register page pointer (PP, DFH). In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, a
paged register file expansion is not implemented and the register page pointer settings therefore always point to
"page 0."
Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always
'0000', automatically selecting page 0 as the source and destination page for register addressing. These page
pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.
Register Page Pointer (PP)
DFH, Set 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Dectination register page selection bits:
0 0 0 0 Destination: page 0
Source register page selection bits:
0 0 0 0 Source: page 0
NOTE:In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller,
only pate 0 is implemented.
A hardware reset operation writes the 4-bit destination and source values
shown above to the register pate pointer. These values should not be
modified.
Figure 2-3. Register Page Pointer (PP)
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-6
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into
two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to
address one bank or the other. In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, bank 1 is
not implemented. A hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1
instructions are not necessary.
The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The
lower 32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–
C0H). You can use the common working register area as a "scratch" area for data operations being performed in
other areas of the register file.
Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing. (For more information about
working register addressing, please refer to Section 3, "Addressing Modes," .)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH)
are addressed as part of page 0 in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 register space.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only
Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect
addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
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PRIME REGISTER SPACE
The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space
or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other
words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All
registers in prime area locations are addressable immediately following a reset.
FFH
C0H
00H
Set 2
Prime
Register
Space
FFH
D0H
C0H
Set 1
FCH
E0H
General-purpose registers
CPU and system registers
Peripheral control registers
Figure 2-4. Set 1, Set 2 and Prime Area Register Map
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-8
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as
consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
—One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15)
—One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)
All of the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
1 1 1 1 1 X X X
RP1 (Registers R8-R15)
RP0 (Registers R0-R7)
Slice 32
Slice 31
~ ~
CFH
C0H
FFH
F8H
F7H
F0H
FH
8H
7H
0H
Slice 2
Slice 1
10H
Set 1
Only
0 0 0 0 0 X X X
Figure 2-5. 8-Byte Working Register Areas (Slices)
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-9
USING THE REGISTER POINTERS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see
Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see
Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)
areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can
define the working register area very flexibly to support program requirements.
++PROGRAMMING TIP — Setting the Register Pointers
SRP #70H ;RP0 → 70H, RP1 → 78H
SRP1 #48H ;RP0 → no change, RP1 → 48H,
SRP0 #0A0H ;RP0 → A0H, RP1 → no change
CLR RP0 ;RP0 → 00H, RP1 → no change
LD RP1,#0F8H ;RP0 → no change, RP1 → 0F8H
FH (R15)
0H (R0)
16-Byte
Contiguous
Working
Register block
Register File
Contains 32
8-Byte Slices
RP0
RP1 8H
7H
0 0 0 0 1 X X X
0 0 0 0 0 X X X
8-Byte Slice
8-Byte Slice
Figure 2-6. Contiguous 16-Byte Working Register Block
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-10
16-Byte
Contiguous
working
Register block
Register File
Contains 32
8-Byte Slices
0 0 0 0 0 X X X
RP1
1 1 1 1 0 X X X
RP0
0H (R0)
7H (R15)
F0H (R0)
F7H (R7)
8-Byte Slice
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
++PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H
contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0 #80H ;RP0 → 80H
ADD R0,R1 ;R0 → R0 + R1
ADC R0,R2 ;R0 → R0 + R2 + C
ADC R0,R3 ;R0 → R0 + R3 + C
ADC R0,R4 ;R0 → R0 + R4 + C
ADC R0,R5 ;R0 → R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used
to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD 80H,81H ;80H → (80H) + (81H)
ADC 80H,82H ;80H → (80H) + (82H) + C
ADC 80H,83H ;80H → (80H) + (83H) + C
ADC 80H,84H ;80H → (80H) + (84H) + C
ADC 80H,85H ;80H → (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-11
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access all locations in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the
least significant byte is always stored in the next (+ 1) odd-numbered register.
Working register addressing differs from Register addressing because it uses a register pointer to identify a
specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
Rn+1
n = Even address
Figure 2-8. 16-Bit Register Pair
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-12
RP1
RP0
00H
C0H
BFH
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
FFH
C0H
Set 2
CFH
D7H
D6H
Set 1
FFH
D0H
Special-Purpose Registers General-Purpose Register
Register
Pointers
Control
Registers
All
Addressing
Modes
Page 0
Indirect
Register,
Indexed
Addressing
Modes
Page 0
Register Addressing Only
Can be Pointed by Register Pointer
Prime
Registers
System
Registers
NOTE: Only page 0 is implemented. Page 0
Contains all of the addressable registers
in the internal register file.
Figure 2-9. Register File Addressing
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-13
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0 → C0H–C7H
RP1 → C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.
Register a hardware reset, register
pointers RP0 and RP1 point to the
commom working register area,
locations C0H-CfH.
RP0 = 1 1 0 0 0 0 0 0
RP1 = 1 1 0 0 1 0 0 0
FFH
C0H
BFH
Set 2
00H
Prime
Area
Set 1
FFH
CFH
C0H
FCH
E0H
DFH
Page 0
~ ~
Figure 2-10. Common Working Register Area
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-14
++PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Example 1:
LD 0C2H,40H ;Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
LD R2,40H ;R2 (C2H) ← the value in location 40H
Example 2:
ADD 0C3H,#45H ;Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
ADD R3,#45H ;R3 (C3H) ← R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
—The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);
—The five high-order bits in the register pointer select an 8-byte slice of the register space;
—The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing: The high-order bit of the instruction
'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-15
Together They Create an
8-bit Register Address
Register Pointer
Provides Five
High-order Bits
Address OPCODE
Selects
RP0 or RP1
RP1
RP0
4-bit Address
Provides Three
Low-order Bits
Figure 2-11. 4-Bit Working Register Addressing
Register
Address
(76H)
RP0
0 1 1 1 0 0 0 0
0 1 1 1 0 1 1 0
R6
0 1 1 0 1 1 1 0
Selects RP0
Instruction:
'INC R6'
OPCODE
RP1
0 1 1 1 1 0 0 0
Figure 2-12. 4-Bit Working Register Addressing Example
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-16
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing: The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
8-bit Logical
Address
8-bit Physical Address
Register Pointer
Provides Five
High-order Bits
Address
Selects
RP0 or RP1
RP1
RP0
Three low-
order Bits
These Address
Bits Indicate 8-bit
Working Register
Addressing
1 1 0 0
Figure 2-13. 8-Bit Working Register Addressing
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-17
8-bit Address
Form Instruction
'LD R11, R2'
RP0
0 1 1 0 0 0 0 0
1 1 0 0 1 0 1 1
Selects RP1
R11
RP1
1 0 1 0 1 0 0 0
1 0 1 0 1 0 1 1
Specifies Working
Register Addressing
Register Address (0ABH)
Figure 2-14. 8-Bit Working Register Addressing Example
ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
2-18
SYSTEM AND USER STACKS
S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations.
The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 architecture supports stack operations in the internal register
file.
Stack Operations
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
Stack Contents
After a Call
Instruction
Stack Contents
After an Interrupt
Top of
Stack FLAGS
PCH
PCL
PCL
PCH
Top of
Stack
Low Address
High Address
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL)
Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset,
the SPL value is undetermined. Because only internal memory 256-byte is implemented in
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5, the SPL must be initialized to an 8-bit value in the range 00H–
FFH.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES
2-19
++PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD SPL,#0FFH ;SPL ← FFH
;(Normally, the SPL is set to 0FFH by the initialization
;routine)
•
•
•
PUSH PP ;Stack address 0FEH ← PP
PUSH RP0 ;Stack address 0FDH ← RP0
PUSH RP1 ;Stack address 0FCH ← RP1
PUSH R3 ;Stack address 0FBH ← R3
•
•
•
POP R3 ;R3 ← Stack address 0FBH
POP RP1 ;RP1 ← Stack address 0FCH
POP RP0 ;RP0 ← Stack address 0FDH
POP PP ;PP ← Stack address 0FEH
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-1
3ADDRESSING MODES
OVERVIEW
The program counter is used to fetch instructions that are stored in program memory for execution. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in instructions may be condition codes,
immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction:
—Register (R)
—Indirect Register (IR)
—Indexed (X)
—Direct Address (DA)
—Indirect Address (IA)
—Relative Address (RA)
—Immediate (IM)
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-2
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).
Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-
byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
dst
Value used in
Instruction Execution
OPCODE OPERAND
8-bit Register
File Address Point to One
Register in Register
File
One-Operand
Instruction
(Example)
Sample Instruction:
DEC CNTR ; Where CNTR is the label of an 8-bit register address
Register FileProgram Memory
Figure 3-1. Register Addressing
4-bit
Working Register Points to the
Working Register
(1 of 8)
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2 ; Where R1 and R2 are registers in the currently
selected working register area.
Program Memory
Register File
3 LSBs
RP0 or RP1
Selected
RP Points
to Start
of Working
Register
Block
MSB Points to
RP0 ot RP1
dst
OPCODE
src OPERAND
Figure 3-2. Working Register Addressing
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-3
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be
accessed using Indirect Register addressing mode.
dst
Address of Operand
used by Instruction
OPCODE ADDRESS
8-bit Register
File Address Point to One
Register in
Register File
One-Operand
Instruction
(Example)
Sample Instruction:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address.
Program Memory Register File
Value used in
Instruction Execution OPERAND
Figure 3-3. Indirect Register Addressing to Register File
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-4
INDIRECT REGISTER ADDRESSING MODE (Continued)
dst
OPCODE Points to
Register Pair
Example
Instruction
References
Program
Memory
Sample Instructions:
CALL @RR2
JP @RR2
Program Memory
Register File
Value used in
Instruction OPERAND
Register Pair
Program Memory
16-Bit
Address
Points to
Program
Memory
Figure 3-4. Indirect Register Addressing to Program Memory
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-5
INDIRECT REGISTER ADDRESSING MODE (Continued)
dst
OPCODE ADDRESS
4-bit
Working
Register
Address Point to the
Working Register
(1 of 8)
Sample Instruction:
OR R3, @R6
Program Memory
Register File
src 3 LSBs
Selected
RP Points
to Start of
Woking
Register
Block
RP0 or RP1
MSB Points to
RP0 or RP1
~ ~
~ ~
Value used in
Instruction OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-6
INDIRECT REGISTER ADDRESSING MODE (Continued)
dst
OPCODE
4-bit Working
Register Address
Sample Instructions:
LDC R5,@RR6 ; Program memory access
LDE R3,@RR14 ; External data memory access
LDE @RR4, R8 ; External data memory access
Program Memory
Register File
src
Value used in
Instruction OPERAND
Example Instruction
References either
Program Memory or
Data Memory Program Memory
or
Data Memory
Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects
Register
Pair
16-Bit
Address
Points to
Program
Memory or
Data
Memory
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP Points
to Start of
Working
Register
Block
NOTE: LDE command is not available, because an external interface is not implemented for
the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-7
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory (if implemented). You cannot, however, access
locations C0H–FFH in set 1 using Indexed addressing.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128
to +127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory (if implemented).
dst/src
OPCODE
Two-Operand
Instruction
Example Point to One of the
Working Register
(1 of 8)
Sample Instruction:
LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Program Memory
Register File
x3 LSBs
Value used in
Instruction OPERAND
INDEX
Base Address
RP0 or RP1
Selected RP
Points to
Start of
Working
Register
Block
~ ~
~ ~
+
MSB Points to
RP0 or RP1
Figure 3-7. Indexed Addressing to Register File
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-8
INDEXED ADDRESSING MODE (Continued)
Register File
OPERAND
Program Memory
or
Data Memory
Point to Working
Register Pair
(1 of 4)
LSB Selects
16-Bit
Address
Added to
Offset
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP Points
to Start of
Working
Register
Block
dst/src
OPCODE
Program Memory
x
OFFSET
4 Bit Working
Register Address
Sample Instructions:
LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H) are
loaded into register R4.
LDE R4,#04H[RR2] ; Identical operation to LDC example, except that
external program memory is accessed.
Next 2 Bits Register
Pair
Value used In
Instruction
8 Bits 16 Bits
16 Bits
+
~ ~
NOTE: LDE command is not available, because an external interface is not implemented for
the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-9
INDEXED ADDRESSING MODE (Continued)
Register File
OPERAND
Program Memory
or
Data Memory
Point to Working
Register Pair
LSB Selects
16 Bit
Address
Added to
Offset
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP Points
to Start of
Working
Register
Block
Sample Instructions:
LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)
are loaded into register R4.
LDE R4, #1000H[RR2] ; Identical operation to LDC example, except that
external program memory is accessed.
Next 2 Bits Register
Pair
Value used in
Instruction
8-Bits 16-Bits
16-Bits
dst/src
OPCODE
Program Memory
x
OFFSET
4 Bit Working
Register Address
OFFSET
+
~ ~
NOTE: LDE command is not available, because an external interface is not implemented for
the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
Figure 3-9. Indexed Addressing to Program or Data Memory
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-10
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Sample Instructions:
LDC R5,1234H; The values in the program address (1234H)
are loaded into register R5.
LDE R5,1234H; Identical operation to LDC example, except that
external program memory is accessed.
dst/src
OPCODE
Program Memory
"0" or "1"
Lower Address Byte
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Memory
Address
Used
Upper Address Byte
Program or
Data Memory
NOTE: LDE command is not available, because an external interface
is not implemented for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
Figure 3-10. Direct Addressing for Load Instructions
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-11
DIRECT ADDRESS MODE (Continued)
OPCODE
Program Memory
Lower Address Byte
Program Memory
Address Used
Upper Address Byte
Sample Instructions:
JP C,JOB1 ; Where JOB1 is a 16 bit immediate address
CALL DISPLAY ; Where DISPLAY is a 16 bit immediate address
Next OPCODE
Figure 3-11. Direct Addressing for Call and Jump Instructions
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-12
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be
executed. Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Current
Instruction
Program Memory
Locations 0-255
Program Memory
OPCODE
dst
Lower Address Byte
Upper Address Byte
Next Instruction
LSB Must be Zero
Sample Instruction:
CALL #40H ; The 16 bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES
3-13
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
OPCODE
Program Memory
Displacement
Program Memory
Address Used
Sample Instructions:
JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Next OPCODE
+
Signed Displacement
Value
Current Instruction
Current
PC Value
Figure 3-13. Relative Addressing
ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
3-14
IMMEDIATE MODE (IM)
In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.
The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing
mode is useful for loading constant values into registers.
(The Operand value is in the instruction)
OPCODE
Sample Instruction:
LD R0,#0AAH
Program Memory
OPERAND
Figure 3-14. Immediate Addressing
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-1
4CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 control registers are
presented in an easy-to-read format. You can use this section as a quick-reference source when writing
application programs. Figure 4-1 illustrates the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference section. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-2
Table 4-1. Mapped Registers (Set 1)
Register Name Mnemonic Decimal Hex R/W
Timer 0 counter T0CNT 208 D0H R(note)
Timer 0 data register T0DATA 209 D1H R/W
Timer 0 control register T0CON 210 D2H R/W
Basic timer control register BTCON 211 D3H R/W
Clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Locations D8H is not mapped.
Stack pointer (low byte) SPL 217 D9H R/W
Instruction pointer (high byte) IPH 218 DAH R/W
Instruction pointer (low byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH R (note)
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W
Port 0 data register P0 224 E0H R/W
Port 1 data register P1 225 E1H R/W
Port 2 data register P2 226 E2H R/W
Location E3H–E6H is not mapped.
Port 0 pull-up resistor enable register P0PUR 231 E7H R/W
Port 0 control register (high byte) P0CONH 232 E8H R/W
Port 0 control register (low byte) P0CONL 233 E9H R/W
Port 1 control register (high byte) P1CONH 234 EAH R/W
Port 1 control register (low byte) P1CONL 235 EBH R/W
Port 1 pull-up resistor enable register P1PUR 236 ECH R/W
Location EDH–EFH is not mapped.
Port 2 control register P2CON 239 F0H R/W
Port 0 interrupt enable register P0INT 241 F1H R/W
Port 0 interrupt pending register P0PND 242 F2H R/W
Counter A control register CACON 243 F3H R/W
Counter A data register (high byte) CADATAH 244 F4H R/W
Counter A data register (low byte) CADATAL 245 F5H R/W
Timer 1 counter register (high byte) T1CNTH 246 F6H R (note)
Timer 1 counter register (low byte) T1CNTL 247 F7H R (note)
Timer 1 data register (high byte) T1DATAH 248 F8H R/W
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-3
Table 4-1. Mapped Registers (Continued)
Register Name Mnemonic Decimal Hex R/W
Timer 1 data register (low byte) T1DATAL 249 F9H R/W
Timer 1 control register T1CON 250 FAH R/W
STOP Control register STOPCON 251 FBH W
Locations FCH is not mapped.
Basic timer counter BTCNT 253 FDH R (note)
External memory timing register EMT 254 FEH R/W
Interrupt priority register IPR 255 FFH R/W
NOTE:You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-4
FLAGS - System Flags Register
.7 Carry Flag (C)
.6 Zero Flag (Z)
.5
Bit Identifier
RESETRESET Value
Read/Write
Bit Addressing Mode
R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used
Addressing mode or
modes you can use
to modify register
values
RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one
Bit number(s) that is/are appended to
the register name for bit addressing Name of individual
bit or related bits
Register nameRegister ID
Sign Flag (S)
0Operation does not generate a carry or borrow condition
0Operation generates carry-out or borrow into high-order bit 7
0Operation result is a non-zero value
0Operation result is zero
0Operation generates positive number (MSB = "0")
0Operation generates negative number (MSB = "1")
Description of the
effect of specific
bit settings
Set 1
Register location
in the internal
register file
D5H
Register address
(hexadecimal)
.7 .6 .5
xxx
R/W R/W R/W
Register addressing mode only
.4 .3 .2 .1 .0
x
R/W
x
R/W
x
R/W
x
R/W
0
R/W
Bit number:
MSB = Bit 7
LSB = Bit 0
Figure 4-1. Register Description Format
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-5
BTCON — Basic Timer Control Register D3H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit Addressing Register addressing mode only
.7–.4 Watchdog Timer Function Disable Code (for System Reset)
1010Disable watchdog timer function
Any other value Enable watchdog timer function
.3–.2 Basic Timer Input Clock Selection Bits
0 0 fOSC/4096
0 1 fOSC/1024
1 0 fOSC/128
1 1 Invalid setting; not used for
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
.1 Basic Timer Counter Clear Bit (1)
0No effect
1Clear the basic timer counter value
.0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 (2)
0No effect
1Clear both clock frequency dividers
NOTES:
1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to '00H'. Immediately following the write
operation, the BTCON.1 value is automatically cleared to "0".
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-6
CACON — Counter A Control Register F3H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 Counter A Input Clock Selection Bits
0 0 fOSC
0 1 fOSC/2
1 0 fOSC/4
1 1 fOSC/8
.5–.4 Counter A Interrupt Timing Selection Bits
0 0 Elapsed time for Low data value
0 1 Elapsed time for High data value
1 0 Elapsed time for combined Low and High data values
1 1 Invalid setting; not used for
S3C80A4/C80A8/C80A5/C80B4/C80B8/C800B8.
.3 Counter A Interrupt Enable Bit
0Disable interrupt
1Enable interrupt
.2 Counter A Start Bit
0Stop counter A
1Start counter A
.1 Counter A Mode Selection Bit
0One-shot mode
1Repeating mode
.0 Counter A Output flip-flop Control Bit
0Flip-flop Low level (T-FF = Low)
1Flip-flop High level (T-FF = High)
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-7
CLKCON — System Clock Control Register D4H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 Oscillator IRQ Wake-up Function Enable Bit
Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.6–.5 Main Oscillator Stop Control Bits
Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.4–.3 CPU Clock (System Clock) Selection Bits (1)
0 0 fOSC/16
0 1 fOSC/8
1 0 fOSC/2
1 1 fOSC (non-divided)
.2–.0 Subsystem Clock Selection Bit (2)
101Invalid setting for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
Other value Select main system clock (MCLK)
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits are required only for systems that have a main clock and a subsystem clock. The
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 uses only the main oscillator clock circuit. For this reason, the setting
'101B' is invalid.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-8
EMT — External Memory Timing Register (note) FEH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET RESET Value 0111110–
Read/Write R/W R/W R/W R/W R/W R/W R/W –
Addressing Mode Register addressing mode only
.7 External WAITWAIT Input Function Enable Bit
0Disable WAIT input function for external device
1Enable WAIT input function for external device
.6 Slow Memory Timing Enable Bit
0Disable WAIT input function for external device
1Enable WAIT input function for external device
.5–.4 Program Memory Automatic Wait Control Bits
0 0 No wait
0 1 Wait one cycle
1 0 Wait two cycles
1 1 Wait three cycles
.3–.2 Data Memory Automatic Wait Control Bits
0 0 No wait
0 1 Wait one cycle
1 0 Wait two cycles
1 1 Wait three cycles
.1 Stack Area Selection Bit
0Select internal register file area
1Select external data memory area
.0 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
NOTE:The EMT register is not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5, because an external
peripheral interface is not implemented in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT
values during normal operation may cause a system malfunction.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-9
FLAGS — System Flags Register D5H
Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value xxxxxx0 0
Read/Write R/W R/W R/W R/W R/W R/W RR/W
Addressing Mode Register addressing mode only
.7 Carry Flag (C)
0Operation does not generate a carry or borrow condition
1Operation generates a carry-out or borrow into high-order bit 7
.6 Zero Flag (Z)
0Operation result is a non-zero value
1Operation result is zero
.5 Sign Flag (S)
0Operation generates a positive number (MSB = "0")
1Operation generates a negative number (MSB = "1")
.4 Overflow Flag (V)
0Operation result is ≤ +127 or ≥ –128
1Operation result is > +127 or < –128
.3 Decimal Adjust Flag (D)
0Add operation completed
1Subtraction operation completed
.2 Half-Carry Flag (H)
0No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
.1 Fast Interrupt Status Flag (FIS)
0Interrupt return (IRET) in progress (when read)
1Fast interrupt service routine in progress (when read)
.0 Bank Address Selection Flag (BA)
0Bank 0 is selected
(normal setting for S3C80A48C80A8/C80A5/C80B4/C80B8/C8085)
1Invalid selection (bank 1 is not implemented)
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-10
IMR — Interrupt Mask Register DDH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
1Enable (un-mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0Disable (mask)
1Enable (un-mask)
.5 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.4 Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt
0Disable (mask)
1Enable (un-mask)
.3–.2 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0Disable (mask)
1Enable (un-mask)
.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0Disable (mask)
1Enable (un-mask)
NOTES:
1. When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
2. Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt
structure.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-11
IPH — Instruction Pointer (High Byte) DAH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL — Instruction Pointer (Low Byte) DBH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-12
IPR — Interrupt Priority Register FFH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit Addressing Register addressing mode only
.7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C
000Group priority undefined
001B > C > A
010A > B > C
011B > A > C
100C > A > B
101C > B > A
110A > C > B
111Group priority undefined
.6 Interrupt Subgroup C Priority Control Bit
0IRQ6 > IRQ7
1IRQ7 > IRQ6
.5, .3 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.2 Input Group B Priority Control Bit
0IRQ4
1IRQ4
.0 Interrupt Group A Priority Control Bit
0IRQ0 > IRQ1
1IRQ1 > IRQ0
NOTE:The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure uses only five levels:
IRQ0, IRQ1, IRQ4, IRQ6–IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and
group C settings (IPR.2,.3 and IPR.5) are not evaluated.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-13
IRQ — Interrupt Request Register DCH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write RRRRRRRR
Addressing Mode Register addressing mode only
.7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4
0Not pending
1Pending
.6 Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
0Not pending
1Pending
.5 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.4 Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt
0Not pending
1Pending
.3–.2 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
.1 Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow
0Not pending
1Pending
.0 Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow
0Not pending
1Pending
NOTE:Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
interrupt structure.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-14
P0CONH — Port 0 Control Register (High Byte) E8H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P0.7/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5–.4 P0.6/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.3–.2 P0.5/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.1–.0 P0.4/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector
address (E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-15
P0CONL — Port 0 Control Register (Low Byte) E9H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P0.3/INT3 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5–.4 P0.2/INT2 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.3–.2 P0.1/INT1 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.1–.0 P0.0/INT0 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector
address.
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-16
P0INT — Port 0 External Interrupt Enable Register F1H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write RRRRRRRR
Addressing Mode Register addressing mode only
.7 P0.7 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.6 P0.6 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.5 P0.5 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.4 P0.4 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.3 P0.3 External Interrupt (INT3) Enable Bit
0Disable interrupt
1Enable interrupt
.2 P0.2 External Interrupt (INT2) Enable Bit
0Disable interrupt
1Enable interrupt
.1 P0.1 External Interrupt (INT1) Enable Bit
0Disable interrupt
1Enable interrupt
.0 P0.0 External Interrupt (INT0) Enable Bit
0Disable interrupt
1Enable interrupt
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-17
P0PND — Port 0 External Interrupt Pending Register F2H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P0.7 External Interrupt (INT4) Pending Flag (note)
0No P0.7 external interrupt pending (when read)
1P0.7 external interrupt is pending (when read)
.6 P0.6 External Interrupt (INT4) Pending Flag
0No P0.6 external interrupt pending (when read)
1P0.6 external interrupt is pending (when read)
.5 P0.5 External Interrupt (INT4) Pending Flag
0No P0.5 external interrupt pending (when read)
1P0.5 external interrupt is pending (when read)
.4 P0.4 External Interrupt (INT4) Pending Flag
0No P0.4 external interrupt pending (when read)
1P0.4 external interrupt is pending (when read)
.3 P0.3 External Interrupt (INT3) Pending Flag
0No P0.3 external interrupt pending (when read)
1P0.3 external interrupt is pending (when read)
.2 P0.2 External Interrupt (INT2) Pending Flag
0No P0.2 external interrupt pending (when read)
1P0.2 external interrupt is pending (when read)
.1 P0.1 External Interrupt (INT1) Pending Flag
0No P0.1 external interrupt pending (when read)
1P0.1 external interrupt is pending (when read)
.0 P0.0 External Interrupt (INT0) Pending Flag
0No P0.0 external interrupt pending (when read)
1P0.0 external interrupt is pending (when read)
NOTE:To clear an interrupt pending condition, write a "0" to the appropriate pending flag. Writing a "1" to an interrupt
pending flag (POND.0–7) has no effect.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-18
P0PUR — Port 0 Pull-up Resistor Enable Register E7H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P0.7 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.6 P0.6 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.5 P0.5 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.4 P0.4 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.3 P0.3 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.2 P0.2 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.1 P0.1 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.0 P0.0 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-19
P1CONH — Port 1 Control Register (High Byte) EAH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P1.7 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.5–.4 P1.6 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.3–.2 P1.5 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.1–.0 P1.4 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-20
P1CONL — Port 1 Control Register (Low Byte) EBH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P1.3 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.5–.4 P1.2 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.3–.2 P1.1 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
.1–.0 P1.0 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid setting
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-21
P1PUR — Port 0 Pull-up Resistor Enable Register ECH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P1.7 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.6 P1.6 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.5 P1.5 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.4 P1.4 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.3 P1.3 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.2 P1.2 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.1 P1.1 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.0 P1.0 Pull-up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-22
P2CON — Port 2 Control Register F0H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P2.2 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
.5–.4 P2.1 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
.3–.2 P2.0 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input with pull up mode
.1 P2.1 Alternative Function Selection Bits
0Normal I/O function
0REM/T0CK function
.0 P2.0 Alternative Function Selection Bits
0Normal I/O function
0T0PWN function
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS
4-23
PP — Register Page Pointer DFH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Destination Register Page Selection Bits
0000Destination: page 0 (note)
.3–.0 Source Register Page Selection Bits Bits
0000Source: page 0 (note)
NOTE:In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, a paged expansion of the
internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values
for the source and destination register page are automatically set to '0000B' following a hardware reset. These
values should not be changed during normal operation.
CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
4-24
RP0 — Register Pointer 0 D6H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET RESET Value 11000–––
Read/Write R/W R/W R/W R/W R/W –––
Addressing Mode Register addressing mode only
.7–.3 Destination Register Page Selection Bits
Register pointer 0 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8-byte working register
slice C0H–C7H.
.2–.0 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
RP1 — Register Pointer 1 D7H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESETRESET Value 11001–––
Read/Write R/W R/W R/W R/W R/W –––
Addressing Mode Register addressing mode only
.7–.3 Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8-byte working register
slice C8H–CFH.
.2–.0 Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.
