This is information on a product in full production.
May 2016 DocID028092 Rev 6 1/38
VNH7100AS
Automotive fully integrated H-bridge motor driver
Datasheet - production data
Features
Automotive qualified
Output current: 15 A
3 V CMOS-compatible inputs
Undervoltage shutdown
Overvoltage clamp
Thermal shutdown
Cross-conduction protection
Current and power limitation
Very low standby power consumption
Protection against loss of ground and loss of
VCC
PWM operation up to 20 kHz
MultiSense diagnostic functions
– Analog motor current feedback
– Output short to ground detection
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
Output protected against short to ground and
short to VCC
Standby Mode
Half Bridge Operation
Package: ECOPACK®
Description
The device is a full bridge motor driver intended
for a wide range of automotive applications. The
device incorporates a dual monolithic high-side
driver and two low-side switches.
Both switches are designed using
STMicroelectronics’ well known and proven
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembled in SO-16N package on electrically
isolated leadframes.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface the microcontroller to select the motor
direction and the brake condition. A SEL0 pin is
available to address the information available on
the MultiSense to the microcontroller. The
MultiSense pin allows to monitor the motor
current by delivering a current proportional to the
motor current value.
The PWM, up to 20 kHz, allows to control the
speed of the motor in all possible conditions. In all
cases, a low level state on the PWM pin turns off
both the LSA and LSB switches.
Type RDS(on) Iout VCCmax
VNH7100AS 100 mtyp
per leg) 12 A 41 V
SO-16N
GAPGCFT00648
Table 1. Device summary
Package
Order codes
Tube Tape and reel
SO-16N — VNH7100ASTR
www.st.com
Contents VNH7100AS
2/38 DocID028092 Rev 6
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 OFF-state open-load detection – External circuitry dimensioning . . . . . . 23
3.3 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24
3.4 Device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 SO16-N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1 Thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28
4.2.2 Thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID028092 Rev 6 3/38
VNH7100AS List of tables
3
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . 10
Table 8. Switching (VCC =13V; R
LOAD =5.2Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . 11
Table 10. CS (7 V < VCC <18V; -40°C<T
j< 150 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. On-state fault conditions - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Off-state - truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Thermal model for junction temperature calculation in steady-state conditions\ . . . . . . . . 29
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. SO-16N carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of figures VNH7100AS
4/38 DocID028092 Rev 6
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input reset time for HSD - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input reset time for LSD - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . . . 17
Figure 12. Normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. OUT shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Application schematic with reverse battery protection connected to Vbatt . . . . . . . . . . . . . 22
Figure 16. Application schematic with reverse battery protection connected to GND . . . . . . . . . . . . . 22
Figure 17. Suggested PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2 . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. PCB 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Chipset configuration configuration in steady state conditions . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air condition . . . . . . . . 29
Figure 25. HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 26. LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. Electrical equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 28. SO-16N package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 29. SO-16N reel 13” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 30. SO-16N carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 31. SO-16N schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 32. SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID028092 Rev 6 5/38
VNH7100AS Block diagram and pin description
37
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Block description
Name Description
Logic control Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Undervoltage Shuts down the device for battery voltage lower than 4 V.
High-side and low-side clamp voltage Protect the high-side and the low-side switches from the
high voltage on the battery line.
High-side and low-side driver Drive the gate of the concerned switch to allow a proper
Ron for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
High-side and low-side overtemperature
protection
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
Low-side overload detector Detects when low side current exceeds shutdown current
and latches off the concerned Low side.
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Block diagram and pin description VNH7100AS
6/38 DocID028092 Rev 6
Figure 2. Configuration diagram (top view)
Fault detection Signalizes the abnormal behavior of the switch through
MultiSense pin.
Power limitation Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Table 3. Pin definitions and functions
Pin N° Symbol Function
1, 16 GNDASource of low-side switch A
2, 15 OUTASource of high-side switch A / drain of low-side switch A
3IN
AClockwise input
4, 5, 12 VCC Power supply voltage
6IN
BCounter clockwise input
7, 10 OUTBSource of high-side switch B / drain of low-side switch B
8, 9 GNDBSource of low-side switch B
11 PWM
Voltage controlled input pin with hysteresis, CMOS compatible. Gates
of low-side FETS get modulated by the PWM signal during their on
phase allowing speed control of the motor. Active high.
13 CS Multiplexed analog sense output pin; it delivers a current proportional
to the motor current.
14 SEL0
Active high compatible with 3 V and 5 V CMOS outputs pin; in
combination with INA, INB, it addresses the CurrentSense information
delivered to the micro according to the operative truth table.
Table 2. Block description (continued)
Name Description
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DocID028092 Rev 6 7/38
VNH7100AS Electrical specifications
37
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
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Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage 38 V
-VCC Reverse DC Supply Voltage 0.3 V
Imax Maximum output current (continuous) Internally limited A
IR Reverse output current (continuous) -15 A
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010
Test B clamped to 40 V; RL = 4 )40 V
VCCJS
Maximum jump start voltage for single pulse short circuit
protection 28 V
IIN Input current (INA and INB pins) -1 to 10 mA
ISEL0 SEL0 DC input current -1 to 10 mA
IPWM PWM input current -1 to 10 mA
ISENSE
CS pin DC output current (VGND =V
CC and VSENSE <0V) 10
mA
CS pin DC output current in reverse (VCC <0V) -20
Electrical specifications VNH7100AS
8/38 DocID028092 Rev 6
2.2 Thermal data
VESD
Electrostatic discharge
(Human body model: R = 1.5 k; C = 100 pF)
–IN
A,INB, PWM
– SEL0
–CS
–V
CC
– Output
2
2
2
4
4
kV
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TcJunction operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Max. value Unit
Rthj-pin Thermal resistance junction-pin
HSD 32 °C/W
LSD 45 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(1)
1. Device mounted on two-layers 2s0p PCB.
See Figure 24 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2)
2. Device mounted on four-layers 2s2p PCB.
HSD 40.7 °C/W
LSD 55.4 °C/W
DocID028092 Rev 6 9/38
VNH7100AS Electrical specifications
37
2.3 Electrical characteristics
Values specified in this section are for VCC = 7 V up to 28 V; -40°C < Tj < 150°C, unless
otherwise specified.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC
Operating supply
voltage 428V
ISSupply current
Off-state (standby)
INA=IN
B= 0; SEL0=0;
PWM = 0; Tj=25°C; V
CC =13V;
1µA
Off-state (standby)
INA=IN
B= 0; SEL0 = 0;
PWM = 0; VCC =13V; T
j= 85°C
1µA
Off-state (standby)
INA=IN
B= 0; SEL0 = 0;
PWM = 0; VCC =13V; T
j= 125 °C
3µA
Off-state (no standby)
INA=IN
B= 0; SEL0=5V;
PWM= 0
24mA
On-state: INA or INB=5V;
PWM = 0 or PWM = 5; SEL0=X 3.5 6 mA
tD_STBY(1)
1. To power on the device from the standby, it is recommended to:
— toggle INA or INB from 0 to 1 first to come out from STBY mode
— toggle PWM from 0 to 1 with a delay of 20 µs
this avoids any over-stress on the device in case of existing short-to-battery.
Standby mode blanking
time
VCC =13V;
INA=IN
B=PMW=0V;
VSEL0 from 5 V to 0 V
0.2 1 1.8 ms
RONHS
Static high-side
resistance
IOUT =2.5A; T
j=25°C 60 m
IOUT =2.5A; T
j=-40 to 150°C 120 m
RONLS
Static low-side
resistance
IOUT = 2.5A; T
j= 25°C 40 m
IOUT = 2.5 A; Tj=-40°C to 150°C 80 m
Vf
Free-wheeling diode
forward voltage IOUT =-2.5A; T
j= 150°C 0.7 0.9 V
IL(off)
Off-state output current
of one leg
INA=IN
B=0; PWM=0;
VCC =13V; T
j=25°C 00.5µA
INA=IN
B=0; PWM=0;
VCC =13V; T
j=125°C 03µA
IL(off_h)
Off-state output current
of one leg with other
HSD on
INA=0; IN
B=5V; PWM=0;
VCC =13V 20 60 µA
Electrical specifications VNH7100AS
10/38 DocID028092 Rev 6
Table 7. Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40°C < Tj < 150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
VIH Input high level voltage 2.1 V
VIHYST Input hysteresis voltage 0.2 V
VICL Input clamp voltage
IIN =1mA 5.3 7.2 V
IIN =-1mA -0.7 V
IINL Input current VIN =0.9V 1 µA
IINH Input current VIN =2.1V 10 µA
SEL0 (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
VSELL Input low level voltage 0.9 V
ISELL Low level input current VSEL =0.9V 1 µA
VSELH Input high level voltage 2.1 V
ISELH High level input current VSEL =2.1V 10 µA
VSEL(hyst) Input hysteresis voltage 0.2 V
VSELCL Input clamp voltage
ISEL =1mA 5.3 7.5 V
ISEL =-1mA -0.8 V
PWM (VCC= 7 V up to 28 V; -40°C < Tj < 150°C)
VPWM Input low level voltage 0.9 V
IPWM Low level input current VPWM =0.9V 1 µA
VPWM Input high level voltage 2.1 V
IPWMH High level input current VPWM =2.1V 10 µA
VPWM(hyst) Input hysteresis voltage 0.2 V
VPMWCL Input clamp voltage
IPWM =1mA 5.3 7.2 V
IPWM =-1mA -0.7 V
Table 8. Switching (VCC =13V; R
LOAD =5.2Ω)
Symbol Parameter Test conditions Min. Typ. Max. Unit
f(1)
1. Parameter guaranteed by design and characterization; not subjected to production test.
PWM frequency 0 20 kHz
td(on) Turn-on delay time Input rise time < 1µs (see Figure 6)20 µs
td(off) Turn-off delay time Input rise time < 1µs (see Figure 6)13 µs
trRise time See Figure 5 0.7 1.5 µs
tfFall time See Figure 5 0.2 0.5 µs
tcross
Low-side turn-on delay
time Input rise time < 1 µs (see Figure 7) 40 150 350 µs
DocID028092 Rev 6 11/38
VNH7100AS Electrical specifications
37
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VUSD Undervoltage shutdown 4 V
VUSDreset
Undervoltage shutdown
reset 5V
VUSDHyst
Undervolatge shutdown
Hysteresis 0.4 V
ILIM_H
High-side current
limitation 12 18 24 A
ISD_LS Shutdown LS current 14 22 30 A
tSD_LS
Time to shutdown for the
low-side
VINA =V
INB =0V;
PWM = 5 V (see Figure 8)5µs
VCL_HSD
High-side clamp voltage
(VCC to OUTA=0 or
OUTB=0)
IOUT = 100 mA;
tCLAMP =1ms 38 46 V
VCL_LSD
Low-side clamp voltage
(OUTA=V
CC or
OUTB = VCC to GND)
IOUT = 100 mA;
tCLAMP =1ms 38 46 V
TTSD_HS
High-side thermal
shutdown temperature INx= 2.1 V 150 175 200 °C
TTR_HS
High-side thermal reset
temperature 135 °C
THYST_HS
High-side thermal
hysteresis (TSD_HS -
TR_HS)
7°C
TTSD_LS
Low-side thermal
shutdown temperature INx= 0 V 150 175 200 °C
VCL
Total clamp voltage
(VCC to GND)
IOUT =100mA;
tCLAMP =1ms 38 46 52 V
VOL
OFF-state open-load
voltage detection
threshold
INA=IN
B=0; PWM=0;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V and within
tD_STBY for CHB
234V
IL(off2)
OFF-state output sink
current
INA=IN
B=0; V
OUTx =V
OL;
PWM = 0 V; VSEL0 =5 V for
CHA; VSEL0 = 0 V and within
tD_STBY for CHB
-100 -15 µA
tDSTKON
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 4)
INA= 5 V to 0 V; INB=0V;
VSEL0 =5V; I
OUT =0A;
VOUTA =4V; PWM=0V
40 150 350 µs
tD_VOL(1)
OFF-state diagnostic
delay time from rising
edge of VOUT (see
Figure 11)
INA=IN
B= 0 V; PWM = 0 V;
VOUTx = 0 V to 4 V;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V and within
tD_STBY for CHB
530µs
Electrical specifications VNH7100AS
12/38 DocID028092 Rev 6
tLatch_RST_HD(1)
Input reset time for high-
side fault unlatch (see
Figure 9)
VINx = 5 V to 0 V; HSDx
faulting 31020µs
tLatch_RST_LS(1)
Input reset time for low-
side fault unlatch (see
Figure 10)
VINx = 0 V to 5 V; LSDx
faulting 31020µs
1. Parameter guaranteed by design and characterization; not subjected to production test.
Table 10. CS (7 V < VCC <18V; -40°C<T
j<150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL
MultiSense clamp
voltage
VCC =18V; I
SENSE =-5mA 11 V
VCC =18V; I
SENSE = 5 mA -13 -9 V
K0IOUT/ISENSE
IOUT = 0.05 A; VSENSE =0.5V;
Tj= -40°C to 150°C 420
K1IOUT/ISENSE
IOUT =0.2A; V
SENSE =0.5V;
Tj= -40°C to 150°C 710 1190 1670
K2IOUT/ISENSE
IOUT = 2.5 A; VSENSE =4V;
Tj= -40°C to 150°C 980 1120 1247
K3IOUT/ISENSE
IOUT = 4 A; VSENSE =4V;
Tj= -40°C to 150°C 990 1120 1235
dK0/K0(1)(2) Analog sense current
drift
IOUT = 0.05 A; VSENSE =0.5V;
Tj= -40°C to 150°C -25 25 %
dK1/K1(1)(2) Analog sense current
drift
IOUT =0.2A; V
SENSE =0.5V;
Tj= -40°C to 150°C -21 21 %
dK2/K2(1)(2) Analog sense current
drift
IOUT =2.5A; V
SENSE =4V;
Tj= -40°C to 150°C -5 5 %
dK3/K3(1)(2) Analog sense current
drift
IOUT =4A; V
SENSE =4V;
Tj= -40°C to 150°C -4 4 %
VSENSE_SAT
Max analog sense
output voltage
VCC =7V; R
SENSE = 10 kΩ;
VSEL0 =5V; I
OUTA =4A;
VINA =5V; PWM=0; T
j=150°C
5V
ISENSE0
MultiSense leakage
current
IOUT =0A; V
SENSE =0V;
INx= 0 V; SEL0=0;
Tj= -40°C to 150°C (standby)
00.5µA
IOUT =0A; V
SENSE =0V;
INx= 0 V; SEL0=5V;
Tj = -40°C to 150°C (no standby)
00.5µA
INx = 5 V; PWM = 5 V:
Tj=-40°C to 150°C; IOUT =0A 05µA
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID028092 Rev 6 13/38
VNH7100AS Electrical specifications
37
Figure 4. TDSTKON
VSENSEH
MultiSense output
voltage in fault
condition
VCC =13V; R
SENSE =1kΩ
– E.g: OUTA in open-load
INA=0V; I
OUTA =0A;
VOUTA =4V; V
SEL0 =5V
57V
VOUT_MSD(2) Output Voltage for
MultiSense shutdown
VINA =5V; V
INB =0V;
VSEL0 =5V; R
SENSE =2.7k
IOUT =2.5A
5V
ISENSE_SAT(2) MultiSense
saturation current
VCC =13V; V
SENSE =4V;
VINA =5V; V
INB =0V;
VSEL0 =5V; T
j=150°C
5.8 mA
IOUT_SAT(2) Output saturation
current
VCC =13V; V
SENSE =4V;
VINA =5V; V
INB =0V;
VSEL0 =5V; I
OUT =7A; T
j=150°C
7A
ISENSEH
MultiSense output
voltage in fault
condition
VCC =13V; V
SENSE =V
SENSEH 72030mA
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and
9V < V
CC < 18 V) with respect to its value measured at Tj = 25 °C, VCC = 13 V.
2. Parameter guaranteed by design and characterization; not subjected to production test.
Table 10. CS (7 V < VCC <18V; -40°C<T
j< 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
7
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Electrical specifications VNH7100AS
14/38 DocID028092 Rev 6
Figure 5. Definition of the low-side switching times
Figure 6. Definition of the high-side switching times
t
f
PWM
t
t
V
OUTA, B
20%
90% 80%
10%
t
r
t
t
V
OUTA
V
INA
90%
10%
t
D(on)
t
D(off)
DocID028092 Rev 6 15/38
VNH7100AS Electrical specifications
37
Figure 7. Low-side turn-on delay time
Figure 8. Time to shutdown for the low-side driver
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Electrical specifications VNH7100AS
16/38 DocID028092 Rev 6
Figure 9. Input reset time for HSD - fault unlatch
Figure 10. Input reset time for LSD - fault unlatch
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VNH7100AS Electrical specifications
37
Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL)
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Electrical specifications VNH7100AS
18/38 DocID028092 Rev 6
Note: Other logic combinations on digital input pins not reported on the above table don’t allow to detect a
latched off channel.
Table 11. Operative condition - truth table
Pin status HSDs and LDSs Status
INAINBSEL0PWM CS HSDA LSDA HSDB LSDB
11
1
x
Current Monitoring HSDA
On Off On Off
0 Current Monitoring HSDB
10 1
1
Current Monitoring HSDA
On Off Off On
0 On Off Off Off
10 0
1
Hi-Z
On Off Off On
0 On Off Off Off
01 1
1
Hi-Z
Off On On Off
0 Off Off On Off
01 0
1
Current Monitoring HSDB
Off On On Off
0 Off Off On Off
00
1
1Hi-ZOffOnOffOn
0
00
1
0x
(1)
1. Refer to Table 13: Off-state - truth table
Off Off Off Off
0(2)
2. For INA =INB=SEL0 = PWM = 0, the device enters in standby after tD_STBY
Off Off Off Off
Table 12. On-state fault conditions - truth table
Digital Input pins
CS Comment
INA INB PWM SEL0
0 0 1 0 VsenseH LSB protection triggered; LSB latched off
0 0 1 1 VsenseH LSA protection triggered; LSA latched off
0 1 X 0 VsenseH HSB protection triggered; HSB latched off
0 1 1 1 VsenseH LSA protection triggered; LSA latched off
1 0 1 0 VsenseH LSB protection triggered; HSB latched off
1 0 X 1 VsenseH HSA protection triggered; HSA latched off
1 1 X 0 Hi-Z HSB protection triggered; HSB latched off
1 1 X 1 Hi-Z HSA protection triggered; HSA latched off
DocID028092 Rev 6 19/38
VNH7100AS Electrical specifications
37
Table 13. Off-state - truth table
INAINBSEL0PWM OutAOutBCS Description
Off-state diagnostic
00
1
0
VoutA>VOL xV
SENSEH
Case 1. OutA shorted to VCC if no
pull-up is applied
Case 2. No open-load in full bridge
configuration with an external pull-
up on OutB
Case 3. open-load in half bridge
configuration with an external pull-
up on OutA(motor connected
between OutA and Ground)
VoutA<VOL x Hi-Z
Case 1. Open-load in full Bridge
configuration with an external pull-
up on OutB
Case 2. No open-load in half Bridge
configuration with external pull-up
on OutA (motor connected between
OutA and Ground)
0(1)(2)
XV
outB>VOL VSENSEH
Case 1. OutB shorted to VCC if
no pull-up is applied
Case 2. No open-load in full
bridge configuration with
external pull-up on OutA
Case 3. Open-load in half bridge
configuration with external pull-up
on OutB (motor connected between
OutB and Ground)
XV
outB<VOL Hi-Z
Case1. Open-load in full Bridge
configuration with an external pull-
up on OutA
Case 2. No open-load in half Bridge
configuration with external pull-up
on OutB (motor connected between
OutB and Ground)
1. The device enters standby mode after tD_STBY
2. To power on the device from the standby, it is recommended to toggle INA or INB from 0 to 1 first and then PWM from 0 to 1
to avoid any over-stress on the device in case of short-to-battery.
Electrical specifications VNH7100AS
20/38 DocID028092 Rev 6
2.4 Waveforms
Figure 12. Normal operative conditions
Figure 13. OUT shorted to ground and short clearing
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VNH7100AS Electrical specifications
37
Figure 14. OUT shorted to Vcc and short clearing
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Application information VNH7100AS
22/38 DocID028092 Rev 6
3 Application information
Here following there is the typical application schematic suggested for a proper operation of
the device in DC or PWM conditions.
Figure 15. Application schematic with reverse battery protection connected to Vbatt
Figure 16. Application schematic with reverse battery protection connected to GND
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DocID028092 Rev 6 23/38
VNH7100AS Application information
37
Figure 17. Suggested PCB layout
Note: PCB layout recommendation:
Optimized connection (short) between Drain LSD and Source HSD
Optimized GNDa and GNDb connection (symmetric connection)
3.1 Reverse battery protection
Three possible solutions can be considered:
A Schottky diode D connected to VCC pin
An N-channel MOSFET connected to the GND pin
A P-channel MOSFET connected to the VCC pin
In case the reverse battery protection is not present, the device sustains no more than -15 A
because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery
condition the I/Os of the device is pulled down to the VCC line (approximately -1.5 V).
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is:
3.2 OFF-state open-load detection – External circuitry
dimensioning
The detection of an open-load in off state requires an external circuitry to be connected
between Output and VBATT
.
For the detection it is necessary to put one network on each leg in case of Half Bridge
operation or one network on one of the output in case of full bridge (see Table 13: Off-state -
truth table).
The external circuitry is made up by an external pull-up resistor Rpull_up connecting the
output to a positive supply voltage VPU (VBatt).
RVIOs VCC
–
IRmax
------------------------------=
Application information VNH7100AS
24/38 DocID028092 Rev 6
It is preferable to switch-off VPU by using an external pull_up switch to reduce the overall
standby current during he module standby mode.
Rpull_up must be dimensioned to ensure that in normal operative conditions VOUT > VOLmax.
To satisfy this condition the Rpull_up must be selected according to:
if the device is used in half bridge configuration, the equation is:
if the device is used in H-bridge configuration, the equation is:
3.3 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 14.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Rpull_up
VBATTmin VOLmax
–
IL(off2)min[@VOLmax]
--------------------------------------------------------
Rpull_up
VBATTmin VOLmax
–
2IL(off2)min[@VOLmax]
--------------------------------------------------------------
Table 14. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and
pulse generator
internal impedance
Level US(1)
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
min max
1 III -112 V 500 pulses 0,5 s 2ms, 10
2a III +55 V 500 pulses 0,2 s 5 s 50µs, 2
3a IV -220 V 1h 90 ms 100 ms 0.1µs, 50
3b IV +150 V 1h 90 ms 100 ms 0.1µs, 50
4(2) IV -7 V 1 pulse 100ms, 0.0 1
Load dump according to ISO 16750-2:2010
Test B(3) 40 V 5 pulse 1 min 400 ms, 2
DocID028092 Rev 6 25/38
VNH7100AS Application information
37
3.4 Device configurations
Figure 18. Half-bridge configuration (case a)
Note: The VNH7100AS can be used in half bridge configuration as the two legs can be
independently driven. The SEL0 pin can be used to address the diagnostic on the CS
according to the operative truth table.
Figure 19. Half-bridge configuration (case b)
Note: The VNH7100AS can be used in applications where an half-bridge with a resistance of
50 mΩ per leg is needed.
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj< 150°C).
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Application information VNH7100AS
26/38 DocID028092 Rev 6
Figure 20. Multi-motors configuration
Note: The VNH7100AS can easily be designed in multi motor driving configuration in the
applications where only one motor at a time must be activated. The SEL0 pin can be used to
read the diagnostic on the CS according to the operative truth table.
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VNH7100AS Package and PCB thermal data
37
4 Package and PCB thermal data
4.1 SO16-N thermal data
Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2
Package and PCB thermal data VNH7100AS
28/38 DocID028092 Rev 6
Figure 22. PCB 4 layer
Note: Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board
dimension 77x86 mm; Board Material FR4; Cu thickness 0.070mm (outer layers); Cu
thickness 0.035mm (inner layers); Thermal vias separation 1.2 mm; Thermal via diameter
0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm.
4.2 Package thermal data
4.2.1 Thermal characterization in steady state conditions
Figure 23. Chipset configuration configuration in steady state conditions
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VNH7100AS Package and PCB thermal data
37
Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air
condition
4.2.2 Thermal characterization during transients
Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zlsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zlsls + Tamb
Table 15. Thermal model for junction temperature calculation in steady-state
conditions\
Chip 1 Chip 2 Chip 3 Tjchip1 Tjchip2 Tjchip3
ON OFF ON Pdchip1 • RthA + Pdchip3
• RthAC + Tamb
Pdchip1 • RthAB + Pdchip3
• RthBC + Tamb
Pdchip1 • RthAC + Pdchip3
• RthC + Tamb
ON ON OFF Pdchip1 • RthA + Pdchip2
• RthAB + Tamb
Pdchip1 • RthAB + Pdchip2
• RthB + Tamb
Pdchip1 • RthAC + Pdchip2
• RthBC + Tamb
ON OFF OFF Pdchip1 • RthA+ Tamb Pdchip1 • RthAB + Tamb Pdchip1 • RthAC + Tamb
ON ON ON
Pdchip1 • RthA + (Pdchip2
+ Pdchip3) • RthAB +
Tamb
Pdchip2 • RthB + Pdchip1 •
RthAB + Pdchip3 • RthBC
+ Tamb
Pdchip1 • RthAB + Pdchip2
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Package and PCB thermal data VNH7100AS
30/38 DocID028092 Rev 6
Figure 25. HSD thermal impedance junction ambient single pulse
Figure 26. LSD thermal impedance junction ambient single pulse
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DocID028092 Rev 6 31/38
VNH7100AS Package and PCB thermal data
37
Figure 27. Electrical equivalent model
Table 16. Thermal parameters
Area/island (cm2)FP 2 8 4L
R1 (°C/W) 5.3 5.3 5.3 5.3
R2 (°C/W) 12 12 12 12
R3 (°C/W) 30 25 25 30
R4 (°C/W) 42 12 12 2
R5 (°C/W) 85 45 30 17
R6 (°C/W) 5.3 5.3 5.3 5.3
R7 (°C/W) 5.1 5.1 5.1 5.1
R8 (°C/W) 12 12 12 12
R9 (°C/W) 30 30 30 42
R10 (°C/W) 68 52 48 10
R11 (°C/W) 75 80 60 26
R12 (°C/W) 5.1 5.1 5.1 5.1
R13 (°C/W) 12 12 12 12
R14 (°C/W) 30 30 30 42
R15 (°C/W) 68 52 48 10
R16 (°C/W) 75 80 60 26
R17 (°C/W) 120 100 100 100
R18 (°C/W) 120 100 100 100
R19 (°C/W) 180 170 170 170
R20 (°C/W) 180 170 170 170
Package and PCB thermal data VNH7100AS
32/38 DocID028092 Rev 6
C1 (W·s/°C) 0.00065 0.00065 0.00065 0.00065
C2 (W·s/°C) 0.018 0.018 0.018 0.018
C3 (W·s/°C) 0.08 0.1 0.1 0.1
C4 (W·s/°C) 0.2 0.5 1 2
C5 (W·s/°C) 1.5 2 6 12
C6 (W·s/°C) 0.00065 0.00065 0.00065 0.00065
C7 (W·s/°C) 0.001 0.001 0.001 0.001
C8 (W·s/°C) 0.02 0.02 0.02 0.02
C9 (W·s/°C) 0.06 0.06 0.06 0.06
C10 (W·s/°C) 0.08 0.1 0.2 0.5
C11 (W·s/°C) 1 2.5 3 6
C12 (W·s/°C) 0.00065 0.00065 0.00065 0.00065
C13 (W·s/°C) 0.02 0.02 0.02 0.02
C14 (W·s/°C) 0.06 0.06 0.06 0.06
C15 (W·s/°C) 0.08 0.1 0.2 0.5
C16 (W·s/°C) 1 2.5 3 6
Table 16. Thermal parameters (continued)
Area/island (cm2)FP 2 8 4L
DocID028092 Rev 6 33/38
VNH7100AS Package and packing information
37
5 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.1 SO-16N mechanical data
Figure 28. SO-16N package dimensions
("1($'5
Package and packing information VNH7100AS
34/38 DocID028092 Rev 6
5.2 SO-16N packing information
Figure 29. SO-16N reel 13”
Table 17. SO-16N mechanical data
Symbol
Millimeters
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e1.27
h 0.25 0.50
L 0.40 1.27
k0 8
ccc 0.10
"DDFTT)PMFBU
4MPU-PDBUJPO
NNNJO
*GQSFTFOU
UBQFTMPUJODPSF
GPSUBQFTUBSU
NNNJOXJEUIY
NNNJOEFQUI
5"1($'5
$
/
8
8
%
"
#
DocID028092 Rev 6 35/38
VNH7100AS Package and packing information
37
Figure 30. SO-16N carrier tape
Table 18. Reel dimensions
Description Value(1)
1. All dimensions are in mm.
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N100
W1 (+2 /-0) 16.4
W2 (max) 22.4
Table 19. SO-16N carrier tape dimensions
Description Value
A06.55 ± 0.1
B010.38 ± 0.1
K02.10 ± 0.1
K11.80 ± 0.1
F7.50 ± 0.1
("1($'5
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36/38 DocID028092 Rev 6
Figure 31. SO-16N schematic drawing of leader and trailer tape
5.3 SO-16N marking information
Figure 32. SO-16N marking information
Note: Engineering Samples: these samples can be clearly identified by a dedicated special
symbol in the marking of each unit. These samples are intended to be used for electrical
compatibility evaluation only; usage for any other purpose may be agreed only upon written
authorization by ST. ST is not liable for any customer usage in production and/or in reliability
qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no usage
restrictions.
P18.00 ± 0.1
W 16.00 ± 0.3
Table 19. SO-16N carrier tape dimensions (continued)
Description Value
("1($'5
40/5017*&8
OPUJOTDBMF
4QFDJBMGVODUJPOEJHJU
&4&OHJOFFSJOHTBNQMF
CMBOL$PNNFSDJBMTBNQMF
.BSLJOHBSFB
DocID028092 Rev 6 37/38
VNH7100AS Revision history
37
6 Revision history
Table 20. Document revision history
Date Revision Changes
16-Jul-2015 1 Initial release.
01-Sep-2015 2
Table 8: Switching (VCC = 13 V; RLOAD = 5.2 Ω):
–t
cross: updated values
Table 9: Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj
< 150°C):
–I
SD_LS, tDSTKON: updated values
Table 10: CS (7 V < VCC < 18 V; -40 °C < Tj < 150 °C):
–K
2, K3, ISENSE_SAT
: updated values
04-Sep-2015 3 Table 4: Absolute maximum ratings:
–I
R: updated value
07-Oct-2015 4
Table 4: Absolute maximum ratings:
–-I
GND: removed row
Updated Table 5: Thermal data
Table 6: Power section:
–V
f: updated parameter
Updated Figure 9: Input reset time for HSD - fault unlatch and
Figure 10: Input reset time for LSD - fault unlatch
Added Section 2.4: Waveforms and Chapter 4: Package and PCB
thermal data
Updated Chapter 3: Application information
21-Oct-2015 5 Updated Table 12: On-state fault conditions - truth table
23-May-2016 6
Table 8: Switching (VCC = 13 V; RLOAD = 5.2 Ω):
–T
r, Tf: updated maximum values
Updated Table 12: On-state fault conditions - truth table
VNH7100AS
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