Table 7. Chip power modes (continued)
Chip mode Description Core mode Normal
recovery
method
• Default mode out of reset
• On-chip voltage regulator is on.
Normal Wait -
via WFI
Allows peripherals to function while the core is in Sleep mode,
reducing power.
• NVIC remains sensitive to interrupts
• Peripherals continue to be clocked.
Sleep Interrupt
Normal Stop -
via WFI
Places chip in static state. Lowest power mode that retains all registers
while maintaining LVD protection.
• NVIC is disabled.
• AWIC is used to wake up from interrupt.
• Peripheral clocks are stopped.
Sleep Deep Interrupt
VLPR (Very
Low-Power Run)
On-chip voltage regulator is in a low-power mode that supplies only
enough power to run the chip at a reduced frequency. Only MCG
modes BLPI and BLPE can be used in VLPR.
• Reduced frequency Flash access mode (1 MHz)
• LVD off
• In BLPI clock mode, only the fast internal reference oscillator is
available to provide a low power nominal 4 MHz source for the
core with the nominal bus and flash clock required to be <800
kHz
• Alternatively, BLPE clock mode can be used with an external
clock or the crystal oscillator providing the clock source.
Run —
VLPW (Very
Low-Power
Wait) -via WFI
Same as VLPR but with the core in Sleep mode to further reduce
power.
• NVIC remains sensitive to interrupts (FCLK = ON).
• On-chip voltage regulator is in a low-power mode that supplies
only enough power to run the chip at a reduced frequency.
Sleep Interrupt
VLPS (Very
Low-Power
Stop)-via WFI
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional.
• Peripheral clocks are stopped, but OSC, LPTMR, RTC, CMP,
TSI can be used.
• TPM and UART can optionally be enabled if their clock source is
enabled.
• NVIC is disabled (FCLK = OFF); AWIC is used to wake up from
interrupt.
• On-chip voltage regulator is in a low-power mode that supplies
only enough power to run the chip at a reduced frequency.
• All SRAM is operating (content retained and I/O states held).
Sleep Deep Interrupt
LLS1 (Low-
Leakage Stop)
State retention power mode
• Most peripherals are in state retention mode (with clocks
stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be used.
• NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by
the interrupt controller to avoid a scenario
where the system does not fully exit stop
mode on an LLS recovery
• All SRAM is operating (content retained and I/O states held).
Sleep Deep Wake-up
Interrupt2
VLLS3 (Very
Low-Leakage
Stop3)
• Most peripherals are disabled (with clocks stopped), but OSC,
LLWU, LPTMR, RTC, CMP, TSI can be used.
Sleep Deep Wake-up Reset3
Table continues on the next page...
Power modes
KL02/KL04/KL05 Product Brief, Rev 3.3, 07/2013
Freescale Semiconductor, Inc. 21