MIC8030/8031 High-Voltage Display Driver General Description The MIC8030/MIC8031 is a CMOS high voltage liquid crystal display driver. Up to 38 segments can be driven from four CMOS level inputs (CLOCK, DATA IN, LOAD and CHIP SELECT). The MIC8031 is rated at 100V and the MIC8030 is rated at 50V. Data is loaded serially into a shift register, and transferred to latches which hold the data until new data is received. The backplane can be driven from external source, or the internal oscillator can be used. If the internal oscillator is used, the frequency of the backplane will be determined by an external resistor and capacitor. The oscillator need not be used if a DC output is desired. Features * High Voltage Outputs capable of a driving up to 100 volt outputs from 5 to 15 volt logic Drives 30, 32, or 38 segments Cascadable On chip Oscillator or External Backplane Input CMOS construction for wide supply range and low power consumption Schmitt Triggers on all inputs * CMOS, PMOS, and NMOS compatible Applications * Dichroic and Standard Liquid Crystal Displays Flat Panel Displays Print Head Drives Vacuum Fluorescent Displays Functional Diagram Data Che Data Out 38 38 Bit Static Shift Register Data Out 32 ry Data Out 30 im 38 Bit Latch N\ Voltage Transtators LCD Oo LEDe Opt | Oscillator Vollage Translator HV Output Driver HV Output Drivers J Segments Back Plane Ordering Information Part Number Temperature Range | Package MIC8030-01AEB | -55C to+125C =| 44-lead CER QUAD MIC8030-01CV 0C to +70C 44-pin PLCC MIC8030-02CN 0C to +70C 48-pin Plastic DIP * AEB indicates units screened to MIL-STD 883, Method 5004, condition B, and burned-in for 1-week.MIC8030/8031 Micrel! 44-Pin CER QUAD -E 44-Pin LCC -L 44-Pin PLCC -V Pin Configuration nN oO gD 5 3 4888 a & 3 % z 5 ? nm D a ESFZP FE BZ? B ete T SHS Seg 26 39} Seg 17 Seg 27 [38] Seg 16 Seg 28 [37] Seg 15 Seg 29 (36) Vee Seg 30 [35] Seg 14 MiC8030-01 Seg 31 MiC8031-01 [34] Seg 13 Seg 32 [33] Seg 12 Vss [32] Seg 11 Thip Select [31] Seg 10 Clock 30] Seg 9 Load [29] Seg 8 8 Eger aN OF oon oO a gs 2* FF 88 FF B a & Oo 4 Functional Description With CHIP SELECT tied low, serial data is clocked into the shift register at each falling edge of the CLOCK input. Pulling LOAD high will cause a parallel loading of the shift register contents into the latches. If load is left high, the latches are transparent. A logic 1 clocked into the shift register corresponds to that segment being on, and that segment is out of phase with the backplane. The backplane may be externally driven or the internal oscillator can be used. If LCD is externally driven, the backplane will be in phase with the input; LCDo OPT is not connected. The internal oscillator is used by shorting LCDo OPT to LCD9, connecting a capacitor to ground, and a resistor to Vcc. The frequency of the backplane will be 1/256 of the input frequency, and is given as: f = 10/[R(C + .0002)) at Vop = 5V, R in kQ, Cin pF. Example: R = 150 kQ2, C = 420 pF: f= 108 Hz Pin Configuration 48-Pin Plastic DIP - N Seg 22 CO] ed [48] Seg 21 Seg 23 [2] [47] Seg 20 Seg 24 [3] [46] Data Out 38 Seg 25 4] 45] Back Plane Seg 26 GB] [34] Seg 19 Seg 27 Ce] [43] Seg 18 Seg 28 CG] [42] Seg 17 Seg 29 [a] [41] Seg 16 Seg 30 ie [4g] Seg 15 Seg 31 [iO] [38] Vee Seg 32 [11] [38] Seg 14 seg 33 [ie] ME909082 FA seg 13 Seg 34 [13] [36] Seg 12 Seg 35 [4] [35] Seg 11 Seg 36 fe) 34] Seg 10 Vss Le 33] Seg 9 Chip Select G7] [32] Seg 8 Clock [ia] ai] Seg 7 Load fe [30] Seg 6 Data In [20] [29] Seg 5 LCDe ey 28] Seg 4 Veco 2] [27] Seg 3 Seg 37 [23] [26] Seg 2 Seg 38 [24] [25] Seg 1 For displays with more than 38 segments, two or more MIC8030/MIC8031 may be cascaded by connecting DATA OUT of the previous stage with DATA IN of the next stage; CLOCK, LOAD and CHIP SELECT of all following stages should be tied to the control lines of the first MIC8030/ MIC8031. The backplane output of the first stage should be tied to LCD of all following stages, the LCD@ OPT must be left unconnected on those stages. If the internal oscillator is used, and Vgp > 50V then an external 330 kQ2 resistor must be used between the BACKPLANE of the first stage and LCDq of all following stages. Packaging options available include DATA OUT 30, 32 or 38 with the corresponding number of segments, and the avail- ability of LCD OPT. Types of packages include plastic and ceramic DIPs, surface mount packages, plastic and ceramic Leadless Chip Carriers and custom packaging. 9-18MiC8030/8031 internal Oscillator Circ uit 200kQ Po 200k Divide by Q 256 Counter 200kQ Reset Clock a 200k12 LCDe Opt Typical Application External Oscillator Chip Select Clock Load 1 [ T Tf T_T Tf Load Clock CS Load Clock S Load Clock CS Data Dataln Data Out Data in Data Out Dataln = Data Out - MIC8030 MIC8030 MiC8030 MIC8031 MIC8031 MIC8031 Pum. LCDe BP L} LCD ae / LCDo BP }_ vy V7 V7 Segments Segmenis r Segments 1-32 33- 65-96 Back Plane Internal Oscillator Chip Select Clock Load ; - T [ Tt tT it Load Clock TS Load Clock 0S Load Clock TS Data Datain Data Out Dataln Data Out Datain Data Out 150ks2 MIC8030 MIC8030 MIC8030 MIC8031 MIC8031 Mic8031 *330kKQ LCbo 6P LCDO BP }_, LCDO BP 470pF Tr LCDO Opt Segments Segments Segments 1-32 33-64 65-96 Back Plane Required if using MIC8031 with jg > 50 9-19MIC8030/8031 Micrel Absolute Maximum Ratings Voc 18V Ves (MICB030) 75V Ves (MIC8031) __ 110V Inputs (CLK, DATA IN, LOAD, CS) -0.5V to 18V Inputs (LCDO) -0.5V to 50V Storage Temperature ~65C to +150C Operating Temperature 55C to +125C Maximum Current into and out of any segment 20 mA Maximum Power Dissipation, any segment 50 mW Maximum Total power dissipation 600 mW DC Electrical Characteristics: Vcc = 5V, Vss = OV, Vag = 50V (MIC3830), Vag = 100V (MIC3831), ~55C < Ta < +125C, unless otherwise noted. Symbol | Parameter Test Conditions Min Typ | Max Units POWER SUPPLY Voc Logic Supply Voltage MIC8030 4.5 5 5.6 v Voc Logic Supply Voltage MIC8031 45 5 16.5 Vv Ves Display Supply Voltage MIC8030 20 35 50 Vv VeB Display Supply Voltage MIC8031 20 35 100 Vv lec Supply Current (external oscillator) Note 1 35 250 pA Supply Current (internal oscillator) Note 1 35 250 IpB Display Driver Current Fap = 100Hz No Loads 7 100 HA IBB Display Driver Current MIC8031, Vag = 100V 20 200 HA INPUTS (CLK, DATA IN, LOAD, CS) VIH Input High Level Veco - 1.5 | Veo - 1.8 Voc Vit Input Low Level 0 2.5 2.0 IL Input Leakage Current <1 5 pA Cc) Input Capacitance Note 2 5 10 pF INPUT LCDO Vin LCDO Input High Levelt Externally driven 0.9Vec Voc 50 Vir LCDO Input Low Level Externally driven ~0.5V 0 0.1Voc ILcbo LCDO Leakage Current Vicpo = 15V 2 10 pA lLcpo LCDO Leakage Current Vicpo = 35V 6 100 pA lLcpo LCDO Leakage Current Vicpo = S0V 1 mA CAPACITANCE LOADS (TYPICAL) Cisec Segment Output FBP < 100Hz 100 pF Cap Backplane Output FBP < 100Hz 4000 pF Voave DC Bias (Average) Any Segment FBP < 100Hz, Note 2 +25 mV OUTPUT TO BACKPLANE Rsea Segment Output Impedance IL = 100pA 1.4 10 kQ Rep Backplane Output Impedance IL = 100A 170 312 Q Rpata out | Data Out Output Impedance (L = 100nA 1.8 3 kad Note 1: CMOS input levels. No loads. Note 2: Guaranteed by design but not tested on a production basis 9-20MIC8030/8031 Micrel AC Electrical Characteristics: vcc = 5V, Vsg = OV, Vag = 50V (MIC3830), Vag = 50V (MIC3831), -55C < Ta < +125C Symbol Parameter Min Typ Max Units tcye Cycle Time 500 ns toL, tOH Clock Pulse Width low/high 250 ns tr, ty Clock rise/fall 1 ps tos Data In Setup 100 ns tesc cs Setup to Clock 100 ns tox Data Hold 10 ns tces CS Hold 220 ns tet Load Pulse Setup 250 ns tices CS Hold (rising load to rising CS) 200 ns tiw Load Pulse Width 300 ns tic Load Pulse Delay (falling load to 0 ns falling clock} tepo Data Out Valid from Clock 220 ns tos. cs Setup to LOAD 0 ns Fap Backplane Frequency 50 100 2000 Hz Timing Diagram Logic Truth Table Data Chip In jClock | Select |Load| Q1(sp) Qnisp) Qn(DRIVER) xX xX 1 x NC NC Qn) lock 0 tT 0 0 NC NC Qnit) 0 tT 0 1 NC NC Qnit) Data 0 L 0 0 0 Qn - 1-20n Qn) 0 L 0 1 0 Qn-1>0n | Qnisry ts 1 tT 0 0 NC NC QniL) 1 tT 0 1 | NC NC Qn) Load 1 4 0 0 1 Qn - 130N QniL) Data 1 L 0 1 1 Qn - 130nN QnisA) Out T = Rising Edge, J = Falling Edge * The TS high-to-low transition will generate a clock pulse. 9-21