LTC3824IMSE - Linear Technology Corporation

LTC3824

3824fg

Typical applicaTion

FeaTures

applicaTions

DescripTion

High Voltage Step-Down

Controller With 40µA

Quiescent Current

The LTC

3824 is a step-down DC/DC controller designed

to drive an external P-channel MOSFET. With a wide input

range of 4V to 60V and a high voltage gate driver, the

LTC3824 is suitable for many industrial and automotive

high power applications. Constant frequency current mode

operation provides excellent performance.

The LTC3824 can be configured for Burst Mode operation.

Burst Mode operation enhances low current efficiency

(only 40µA quiescent current) and extends battery run

time. The switching frequency can be programmed up to

600kHz and is easily synchronizable.

Other features include current limit, soft-start, micropower

shutdown, and Burst Mode disable.

The LTC3824 is available in a 10-lead MSE power package.

5V/2A Buck Converter

n Wide Input Range: 4V to 60V

n Current Mode Constant Frequency PWM

n Very Low Dropout Operation: 100% Duty Cycle

n Programmable Switching Frequency:

200kHz to 600kHz

n Selectable High Efﬁcient Burst Mode

Operation:

40µA Quiescent Current

n Easy Synchronization

n 8V, 2A Gate Drive (VCC > 10V) for Industrial High

Voltage P-Channel MOSFET

Programmable Soft-Start

Programmable Current Limit

n Available in a Small 10-Pin Thermally Enhanced

MSE Package

Industrial and Automotive Power Supplies

Telecom Power Supplies

Distributed Power Systems

L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5731964.

Efficiency and Power Loss vs Load Current

3824 TA01

10k

80.6k

0.025Ω

51Ω

CCAP

0.1µF

422k

100pF

COUT

100µF

×2

22µH VOUT

0.1µF

392k

CIN

33µF

100V

3.3nF

LTC3824

SENSE

GATE

CAP

VFB

VCC

RSET

GND

SYNC/MODE

VIN

5.5V TO 60V

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

10 100

3824 TA01a

100

0.5

1.0

2.0

1.5

2.5

EFFICIENCY

POWER LOSS

20001000

VIN = 12V

VIN = 40V

VIN = 12V

LTC3824

3824fg

pin conFiguraTionabsoluTe MaxiMuM raTings

VCC ........................................................................... 65V

SS, RSET, VFB .............................................................4V

VC ...............................................................................3V

SYNC/MODE ...............................................................6V

VCC – VSENSE ..............................................................1V

Operating Junction Temperature Range

(Note 2) .................................................. –55°C to 150°C

Storage Temperature Range ..................... –65° to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

(Note 1)

GND

SYNC/MODE

RSET

VFB

CAP

GATE

VCC

SENSE

TOP VIEW

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 43°C/W, θJC = 3°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3824EMSE#PBF LTC3824EMSE#TRPBF LTBRZ 10-Lead Plastic MSOP –40°C to 125°C

LTC3824IMSE#PBF LTC3824IMSE#TRPBF LTCGZ 10-Lead Plastic MSOP –40°C to 125°C

LTC3824HMSE#PBF LTC3824HMSE#TRPBF LTCGZ 10-Lead Plastic MSOP –40°C to 150°C

LTC3824MPMSE#PBF LTC3824MPMSE#TRPBF LTCGZ 10-Lead Plastic MSOP –55°C to 150°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3824EMSE LTC3824EMSE#TR LTBRZ 10-Lead Plastic MSOP –40°C to 125°C

LTC3824IMSE LTC3824IMSE#TR LTCGZ 10-Lead Plastic MSOP –40°C to 125°C

LTC3824HMSE LTC3824HMSE#TR LTCGZ 10-Lead Plastic MSOP –40°C to 150°C

LTC3824MPMSE LTC3824MPMSE#TR LTCGZ 10-Lead Plastic MSOP –55°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = 12V, RSET = 392k, CCAP = 0.1µF. No load on any

outputs, unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage (VCC)l4 60 V

Supply Current (IVCC) VC ≤ 0.4V (Switching Off), VCC ≤ 60V

VSYNC = 0V (Burst Mode Operation Disable)

0.8 1.3 mA

Supply Current (IVCC) Burst Mode Operation VCC ≤ 60V, SYNC/MODE Open, VC = 0.6V 40 65 µA

Supply Current in Shutdown VC ≤ 25mV, VCC ≤ 60V

9 20

µA

VC ≤ 25mV, VCC = 12V

5 10

µA

Voltage Amplifier gm

Reference Voltage (VREF)

LTC3824E/LTC3824I

LTC3824MP/LTC3824H

0.792

0.788

0.8 0.808

0.812

0.816

Transconductance VC = 0.8V, ∆IVC = ±2µA 220 260 370 µmho

FB Input Current VFB = VREF (Note 3): LTC3824E/LTC3824I

LTC3824MP/LTC3824H

VC High IVC = 0 1.6 V

LTC3824

3824fg

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3824 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3824E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C operating junction temperature. Speciﬁcations over

the –40°C to 125°C operating junction temperature range are assured by

design characterization and correlation with statistical process controls.

The LTC3824I is guaranteed over the –40°C to 125°C operating junction

temperature range. The LTC3824H is guaranteed over the –40°C to 150°C

operating junction temperature range. The LTC3824MP is guaranteed

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = 12V, RSET = 392k, CCAP = 0.1µF. No load on any

outputs, unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

VC Low IVC = 0 0.35 0.5 V

VC Source Current VVC = 0.5V to 1.3V, VFB = VREF –100mV (VSYNC = 0V) 15 µA

VC Sink Current VVC = 0.7V to 1.3V, VFB = VREF +100mV (VSYNC = 0V) 15 µA

VC Threshold for Switching Off VSYNC/MODE = 0V (Note 4) l0.4 V

Soft-Start Current ISS VSS = 0.1V to 1.5V

2.5

5 7.5

µA

VC Burst Mode Threshold VCC ≤ 60V, VC Rising, SYNC/MODE Open 0.84 V

VC Burst Mode Threshold Hysteresis VCC ≤ 60V 0.04 V

SENSE Voltage at Burst Mode Operation (VCC–VSENSE) at 30% Duty Cycle

70% Duty Cycle

Current Limit Threshold (VCC–VSENSE) VCC ≤ 60V: LTC3824E/LTC3824I

LTC3824MP/LTC3824H

100

120

FB Overvoltage Threshold VC = 1.6V 8 %

Sense Input Current VSENSE = VCC 0.1 2 µA

Oscillator

Switching Frequency RSET = 392k: LTC3824E/LTC3824I

LTC3824MP/LTC3824H

170

200

230

240

kHz

RSET = 200k l320 400 460 kHz

Synchronization Pulse Threshold

on SYNC Pin

Rising Edge VSYNC 1.3 V

Synchronization Frequency Range RSET = 392k

RSET = 200k

230

460

300

600

kHz

VRSET RSET = 392k 1.2 V

Minimum On-Time (Measured at GATE Pin) CCM Operation (Note 5) 350 ns

Switching Frequency Foldback VFB = 0.3V l35 50 75 kHz

Gate Driver

GATE Bias Voltage (VCC–VCAP) 9V ≤ VCC ≤ 60V, IGATE = 10mA: LTC3824E/LTC3824I

LTC3824MP/LTC3824H

7.0

6.8

7.9

8.8

8.9

VCC = 12V, IGATE = 15mA l6.8 V

GATE Bias Voltage (VCAP–GND) 4V ≤ VCC ≤ 8V, IGATE = 10mA

6V ≤ VCC ≤ 8V, IGATE = 15mA

0.2 0.85 1.5

2.8

GATE High Voltage (VCC–VGATE) 4V ≤ VCC ≤ 60V, IGATE = –15mA 0.5 0.8 V

GATE Peak Source Current CGATE = 10nF 2.5 A

GATE Low Voltage (VGATE–VCAP) 8V ≤ VCC ≤ 60V, IGATE = 15mA

4V ≤ VCC < 8V, IGATE = 10mA

0.1

0.05

0.5 V

GATE Peak Sink Current CGATE = 10nF 2.5 A

and tested over the full –55°C to 150°C operating junction temperature

range. High junction temperatures degrade operating lifetimes; operating

lifetime is derated for junction temperatures greater than 125°C. Note that

the maximum ambient temperature consistent with these speciﬁcations

is determined by speciﬁc operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors. The junction temperature (TJ, in °C) is calculated from the ambient

temperature (TA, in °C) and power dissipation (PD, in Watts) according to

the formula:

TJ = TA + (PD • θJA)

where θJA (in °C/W) is the package junction to ambient thermal

impedance.

LTC3824

3824fg

Typical perForMance characTerisTics

(VCC-VCAP) vs IGATE at VDRIVE Low

ICC vs VCC

Switching Frequency Change

vs VCC at RSET = 392kΩ

VREF Change vs VCC

Switching Frequency vs RSET

∆VREF vs Temperature

TA = 25°C unless otherwise noted.

IGATE (mA)

0 10

VCC-VCAP (V)

8.5

8.4

8.3

8.2

8.1

3824 G01

8.0

7.9

7.8

7.7

7.6 20 30 40 50

VCC (V)

ICC (mA)

10 20 30 40

3824 G02

50 60

VFB = 0.75V

VFB = 0.85V

VCC (V)

–3

ΔFREQUENCY (kHz)

–2

–1

10 20 30 40

3824 G03

50 60

VCC (V)

–0.4

ΔVREF (mV)

–0.2

0.2

0.4

10 20 30 40

3824 G04

50 60

DIE TEMPERATURE (°C)

–75 –50

–2

∆VREF (mV)

–1

–25 0 25 50

3824 G06

75 100 150125

Note 3: This parameter is tested in a feedback loop that servos VFB to the

reference voltage with the VC pin forced to 1V.

Note 4: This speciﬁcation represents the maximum voltage on VC where

switching (GATE pin) is guaranteed to be off. The nominal value of VC

where switching turns off is 0.7V.

Note 5: The LTC3824 typically enters Burst Mode operation when the load

is less than one third the current limit. If minimum on-time is violated,

cycle skipping may occur at higher current levels.

elecTrical characTerisTics

RSET(kΩ)

100

FREQUENCY (kHz)

200

300

400

500

700

200 300

3824 G05

400

600

LTC3824

3824fg

Burst Mode Disabled at

ILOAD = 200mA, VOUT = 5V

Burst Mode Operation VOUT = 3V

Burst Mode Operation VOUT = 5V

Typical perForMance characTerisTics

Load Current Step Response

VOUT

10mV/DIV

INDUCTOR

CURRENT

1A/DIV

4µs/DIV 3824 G07

ILOAD = 200mA

VOUT

50mV/DIV

INDUCTOR

CURRENT

1A/DIV

20µs/DIV 3824 G08

VIN =12V, VOUT= 3V, ILOAD = 200mA

VOUT

50mV/DIV

INDUCTOR

CURRENT

1A/DIV

50µs/DIV 3824 G09

VIN =12V, VOUT= 5V, ILOAD = 200mA

OUTPUT VOLTAGE

AC COUPLED

100mV/DIV

INDUCTOR

CURRENT

2A/DIV

100µs/DIV 3824 G10

TA = 25°C unless otherwise noted.

LTC3824

3824fg

pin FuncTions

GND (Pin 1): Chip Ground Pin.

SYNC/MODE (Pin 2): Synchronization Input and Burst

Mode Operation Enable/Disable. If this pin is left open

or pulled higher than 2V, Burst Mode operation will be

enabled at light load and the typical threshold of entering

Burst Mode operation is one third of current limit. If this

pin is grounded or the synchronization pulse is present

with a frequency greater than 20kHz then Burst Mode

operation is disabled and the LTC3824 goes into pulse

skipping at light loads. To synchronize the LTC3824, the

duty cycle of the synchronizing pulse can range from 10%

to 70% and the synchronizing frequency has to be higher

than the programmed frequency.

RSET

(Pin 3): A resistor from RSET to ground sets the

LTC3824 switching frequency.

VC (Pin 4): The Output of the voltage error amplifier gm

and the control signal of the current mode PWM control

loop. Switching starts at 0.7V, and higher VC corresponds

to higher inductor current. When VC is pulled below 25mV,

the LTC3824 goes into micropower shutdown.

VFB (Pin 5): Error Amplifier Inverting Input. A resistor

divider to this pin sets the output voltage. When VFB is

less than 0.5V, the switching frequency will fold back to

50kHz to reduce the minimum on-cycle.

SS (Pin 6): Soft-Start Pin. A capacitor on this pin sets

the output ramp-up rate. The typical time for SS to

reach the programmed level is (C • 0.8V)/5µ

SENSE (Pin 7): Current Sense Input Pin. A sense re-

sistor, RS, from VIN to SENSE sets the current limit to

100mV/RS.

VCC (Pin 8): Chip Power Supply. Power supply bypass-

ing is required.

GATE (Pin 9): Gate Drive for The External P-channel

MOSFET. Typical peak drive current is 2.5A and the drive

voltage is clamped to 8V when VCC is higher than 9V.

CAP (Pin 10): A Low ESR Capacitor of at Least 0.1µF is

required from this pin to VCC to bypass the internal regula-

tor for biasing the gate driver circuitry.

GND (Exposed Pad Pin 11): Ground. Must be soldered

to PCB with expanded metal trace for rated thermal per-

formance.

LTC3824

3824fg

block DiagraM

applicaTions inForMaTion

Operation

The LTC3824 is a constant frequency current mode buck

controller with programmable switching frequency up to

600kHz.

Referring to the Block Diagram, the LTC3824’s basic

functions include a transconductance amplifier gm to

regulate the output voltage and control the current mode

PWM current loop, the necessary logic to control the

PWM switching cycles, a high speed gate driver to drive

an external high power P-channel MOSFET and a voltage

regulator to bias the gate driver circuit.

In normal operation each switching cycle starts with switch

turn-on and the inductor current is sampled through the

current sense resistor. This current is amplified and then

compared to the error amplifier output VC to turn the

switch off. Voltage loop regulates the output voltage to the

programmed level through the output resistor divider and

the error amplifier. Amplifier E1 regulates the gate drive

low to approximately 8V below VCC for VCC higher than

9V, and CCAP stabilizes the voltage. Note that when VCC is

lower than 9V, gate drive high will be within 0.5V of VCC

and gate drive low within 1V of ground.

Important features include shutdown, current limit, soft-

start, synchronization and low quiescent current.

–

3824 BD

50KHz FOLDBACK

SYNC DISABLE

Burst Mode

OPERATION

CONTROL

OSC

2.5V1.8V

100k

Burst Mode

DISABLE

0.025V

VREF

0.8V

2.5V

5µA

VCSS

SHUTDOWN

1.5V

GND

1.1V

SYNC/

MODE

RSET

RFREQ

–

CCAP

0.1µF

CAP

0.5V

RF2

RF1

GATE

COUT

VOUT

VIN

470pF

CSS

0.1µF

SLOPE

COMP

VCC

0.3µA

OR1

SENSE

0.1V

50pF

PWM

VREF

REFERENCE

–

LTC3824

3824fg

applicaTions inForMaTion

Burst Mode Operation

The LTC3824 can be configured for Burst Mode operation to

enhance light load efficiency (only 40µA quiescent current)

and extend battery run time by leaving the SYNC/MODE

pin open or pulling it higher than 2V. In this mode, when

output load drops the loop control voltage VC also drops

and when VC reaches approximately 0.9V at low duty cycle

the LTC3824 goes into sleep mode with the switch turned

off. During sleep mode the output voltage drops and VC

rises up. When VC goes up to around 70mV the LTC3824

will turn on the switch and the burst cycle repeats. If the

SYNC/MODE pin is grounded the Burst Mode operation

will be disabled and the LTC3824 skips cycles at light load.

Oscillation Frequency Setting and Synchronization

The switching frequency of the LTC3824 can be set up to

600kHz by a resistor, RFREQ, from the RSET pin to ground.

For 200kHz, RFREQ = 392k. See the Switching Frequency

vs RFREQ graph in the Typical Performance Characteris-

tics section. With a 100ns one-shot timer on-chip, the

LTC3824 provides flexibility on the sync pulse width. The

sync pulse threshold voltage level is about 1.2V.

Short-Circuit Protection

In normal operation when the output voltage is in regulation,

VFB is regulated to 0.8V. If the output is shorted to ground

and VFB drops below 0.5V the switching frequency will be

reduced to 50kHz to allow the inductor current to discharge

and prevent current runaway. Note that synchronization

is enabled only when VFB is above 0.5V.

Soft-Start

During soft-start, the voltage on the SS pin (VSS) is the

reference voltage that controls the output voltage and the

output ramps up following VSS. The effective range of VSS

is from 0V to 0.8V. The typical time for the output to reach

the programmed level is:

tSS =CSS •0.8V

5μA

where CSS is the capacitor connected from the SS pin to

GND.

Overvoltage Protection

To achieve good output regulation in Burst Mode operation,

an overvoltage comparator, OVP, with a threshold adap-

tive to the VC voltage is used to monitor the FB voltage.

In Burst Mode operation with low VC voltage, the OVP

threshold is approximately 2% above VREF and the VREF

is also shifted lower by 2% to contain the output ripple

and to keep output regulation constant. As output load

increases, OVP threshold increases with VC voltage to up

to 8% above VREF.

Shutdown Mode Quiescent Current

When the VC pin is pulled down below 25mV the LTC3824

goes into micropower shutdown mode and only draws 7µA.

Output Voltage Programming

With a 0.8V feedback reference voltage, VREF, the output

voltage, VOUT, is programmed by a resistor divider as

shown in the Block Diagram.

VOUT = 0.8V (1+RF1/RF2)

Current Sense Resistor RS and Current Limit

The maximum current the LTC3824 can deliver is deter-

mined by:

IOUT(MAX) = 100mV/RS – IRIPPLE/2

where 100mV is the internal 100mV threshold across VCC

and VSENSE, and IRIPPLE is the inductor peak-to-peak ripple

current. RS should be placed very close to the power switch

with very short traces. Good kelvin sensing is required for

accurate current limit.

LTC3824

3824fg

applicaTions inForMaTion

Inductor Selection

The maximum inductor current is determined by :

IL(MAX) =IOUT(MAX) +IRIPPLE

where IRIPPLE =(VIN – VOUT )•D

f•L

and Duty Cycle D =VOUT +VD

VIN +VD

VD is the catch diode D1 forward voltage and f is the

switching frequency.

A small inductance will result in larger ripple current,

output ripple voltage and also larger inductor core loss.

An empirical starting point for the inductor ripple current

is about 40% of maximum DC current.

L=(VIN– VOUT )•D

f•0.4 •IOUT(MAX)

The saturation current level of the inductor should be

sufficiently larger than IL(MAX).

Power MOSFET Selection

Important parameters for the power MOSFET include the

drain-to-source breakdown voltage (BVDSS), the threshold

voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-

to-source voltage, the gate-to-source and gate-to-drain

charges (QGS and QGD, respectively), the maximum drain

current (ID(MAX)) and the MOSFET’s thermal resistance

(RTH(JC)) and RTH(JA).

The gate drive voltage is set by the 8V internal regulator.

Consequently, at least 10V VGS

rated MOSFETs are required

in high voltage applications.

In order to calculate the junction temperature of the power

MOSFET, the power dissipated by the device must be known.

This power dissipation is a function of the duty cycle, the

load current and the junction temperature itself (due to the

positive temperature coefficient of RDS(ON)). The power

dissipation calculation should be based on the worst-cast

specifications for VSENSE(MAX), the required load current at

maximum duty cycle, the voltage and temperature ranges,

and the RDS(ON) of the MOSFET listed in the data sheet.

The power dissipated by the MOSFET when the LTC3824

is in continuous mode is given by :

MOSFET =VOUT+VD

VIN +VD

(IOUT )2(1+ δ)RDS(ON)

+ K(VIN )2(IOUT )(CRSS )(f)

The first term in the equation represents the I2R losses in

the device and the second term is the switching losses. K

(estimated as 1.7) is an empirical factor inversely related

to the gate drive current and has the unit of 1/Amps. The δ

term accounts for the temperature coefficient of the RDS(ON)

of the MOSFET, which is typically 0.4%/°C. CRSS is the

MOSFET reverse transfer capacitance. Figure 1 illustrates

the variation of normalized RDS(ON) over temperature for

a typical power MOSFET.

Figure 1. Normalized RDS(ON) vs Temperature

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

TJ = TA + PMOSFET • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the case to the ambient temperature (RTH(CA)). This value

of TJ can then be compared to the original assumed value

used in the calculation.

Output Diode Selection

The catch diode carries load current during the switch

off-time. The average diode current is therefore dependent

JUNCTION TEMPERATURE (°C)

–50

δ NORMALIZED ON-RESISTANCE

1.0

1.5

150

3824 F01

0.5

0050 100

2.0

LTC3824

3824fg

applicaTions inForMaTion

on the P-channel switch duty cycle. At high input voltages

the diode conducts most of the time. As VIN approaches

VOUT the diode conducts only a small fraction of the time.

The worst condition for the diode is when the output is

shorted to ground. Under this condition the diode must

safely handle the maximum current at close to 100% of

the time. Therefore, the diode must be carefully chosen

to meet the worst case voltage and current requirements.

Under normal conditions, the average current conducted

by the diode is:

ID = IOUT • (1 – D)

A fast switching Schottky diode must be used to optimize

efficiency.

CIN and COUT Selection

A low ESR input capacitor, CIN, sized for the maximum

RMS P-channel switch current is required to prevent large

input voltage transients. The maximum RMS capacitor

current is given by:

IRMS =IOUT(MAX)

VOUT

VIN

VOUT

– 1

This formula has a maximum at VIN = 2VOUT, where IRMS =

IOUT/2. This simple worst-case condition is commonly used

for design because even significant deviations do not offer

much relief. Note that ripple current ratings from capacitor

manufacturers are often based on only 2000 hours of life

which makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

size or height requirements in the design.

The selection of COUT is determined by the effective series

resistance (ESR) that is required to minimize voltage ripple

and load step transients as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable.

The output ripple, ∆VOUT , is determined by:

ΔVOUT ≤ ΔILESR+1

8fCOUT











The output ripple is highest at maximum input voltage

since ∆IL increases with input voltage. Multiple capacitors

placed in parallel may be needed to meet the ESR and

RMS current handling requirements. Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Special polymer

capacitors offer very low ESR but have lower capacitance

density than other types. Tantalum capacitors have the

highest capacitance density but it is important to only

use types that have been surge tested for use in switching

power supplies. Aluminum electrolytic capacitors have

significantly higher ESR, but can be used in cost-sensitive

applications provided that consideration is given to ripple

current ratings and long-term reliability. Ceramic capaci-

tors have excellent low ESR characteristics but can have

a high voltage coefficient and audible noise.

Efficiency Considerations

The efficiency of a switching regulator is equal to the output

power divided by the input power. Percentage efficiency

can be expressed as:

% Efficiency = 100%–(L1 + L2 + L3 +......)

where L1, L2, L3...are the individual loss components as a

percentage of the input power. It is often useful to analyze

individual losses to determine what is limiting the efficiency

and which change would produce the most improvement.

Although all dissipative elements in the circuit produce

losses, the following are the main sources:

1. The supply current into VCC. The VCC current is the sum

of the DC supply current and the MOSFET driver and

control currents. The DC supply current into the VCC pin

is typically about 1mA. The driver current results from

switching the gate capacitance of the power MOSFET;

this current is typically much larger than the DC current.

Each time the MOSFET is switched on and off, a packet

of gate charge QG is transferred from the CAP pin to

VCC throughout the external bypass capacitor, CCAP

The resulting dQ/dt is a current that must be supplied

to the capacitor by the internal regulator.

IQ = 1mA + f • QG

PIC = VIN • IQ

LTC3824

3824fg

applicaTions inForMaTion

2. Power MOSFET switching and condution losses:

MOSFET =VOUT +VD

VIN +VD

(IOUT )2(1+ δ)RDS(ON)

+ K(VIN )2(IOUT )(CRSS )(f)

3. The I2R losses of the current sense resistor:

P(SENSE R) = (IOUT)2 • R • D

where D is the duty cycle

4. The inductor loss due to winding resistance:

P(WINDING) = (IOUT)2 • RW

5. Loss of the catch diode:

P(DIODE) = IOUT • VD • (1–D)

6. Other losses, including CIN and COUT ESR dissipation

and inductor core losses, generally account for less

than 2% of total losses.

PCB Layout Considerations

To achieve best performance from a LTC3824 circuit, the PC

board layout must be carefully designed. For lower power

applications, a 2-layer PC board is sufficient. However, at

higher power levels, a multiple layer PC board is recom-

mended. Using a solid ground plane under the circuit is

the easiest way to ensure that switching noise does not

affect the operation.

In order to help dissipate the power from the MOSFET and

diode, keep the ground plane on the layers closest to the

layers where power components are mounted. Use power

planes for the MOSFET and diode in order to improve the

spreading of heat from these components into the PCB.

For best electrical performance the LTC3824 circuit should

be laid out as following:

Place all power components in a tight area. This will

minimize the size of high current loops. Orient the input

and output capacitors and current sense resistor in a way

that minimizes the distance between the pads connected

to ground plane.

Place the LTC3824 and associated components tightly

together and next to the section with power components.

Use a local via to ground plane for all pads that connect to

ground. Use multiple vias for power components.

Connect the current sense input directly to the current

sense resistor pad. VCC and SENSE are the inputs of the

internal current sense amplifier and should be connected

as close to the sense resistor pads as possible. A 100pF

capacitor is required across the VCC and sense pins for

noise filtering and should be placed as close to the pins

as possible.

Design Example

As an example, the LTC3824 is designed for an automo-

tive 5V power supply with the following specifications:

Maximum IOUT = 2A, typical VIN = 6V to 18V and can reach

60V briefly during load dump condition, and operating

switching frequency = 400kHz.

For f = 400kHz, RSET is chosen to be 180k.

Allow inductor ripple current to be 0.8A (40% of the

maximum output current) at VIN = 18V,

L=(18V – 5V)5V

(400kHz •0.8A)18V =12μH

COUT will be selected based on the ESR that is required

to satisfy the output voltage ripple requirement and the

bulk capacitance needed for loop stability. For this design

a 220µF tantalum capacitor is used.

For worse-case conditions CIN should be rated for at least

1A ripple current (half of the maximum output current). A

47µF tantalum capacitor is adequate.

A current limit of 3.3A is selected and RSENSE can be

calculated by :

RSENSE =100mV

3.3A =0.03Ω

and a 25mΩ resistor can be used.

LTC3824

3824fg

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev G)

MSOP (MSE) 0910 REV G

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

8910

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

1.68 ± 0.102

(.066 ± .004)

1.88 ± 0.102

(.074 ± .004)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.68

(.066)

1.88

(.074)

0.1016 ± 0.0508

(.004 ± .002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

Typical applicaTion

12V 2A Buck Converter

package DescripTion

3824 TA02

15k

8.06k

113k

1000pF

68k

COUT

270µF

1µF

16V

X7R

33µH VOUT

12V

0.1µF

301k

CIN1

33µF

100V

CIN2

2.2µF

100V

1000pF

LTC3824

SENSESYNC/MODE

GATE

VFB

VCC

RSET

GND

VIN

12.5V TO 60V

CIN1: SANYO 63MV68AX

CIN2: TDK C4532X7R2A225M

COUT: SANYO OSCON, 16SP270M, TDKC2012X7RIC105K

L1: D104C919AS-330M

D1: SS3H9

Q1: Si7465DP

0.025Ω

100pF

CCAP

0.1µF

CAP

LTC3824

3824fg

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

F 12/10 E-grade Ordering Information updated to 125°C

EC header corrected to Operation Junction Temperature

Updated/corrected Note 2

Updated Block Diagram

Shutdown section updated

Package updated

Related Parts updated per Marketing request

G 3/11 Updated Temperature Range for MP-grade part

Added LTC3824MP to Electrical Characteristics tables

Updated Note 2

Updated Typical Application

2, 3

(Revision history begins at Rev F)

LTC3824

3824fg

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2006

LT 0311 REV G • PRINTED IN USA

relaTeD parTs

Typical applicaTion

3V 2A Buck Converter

3824 TA02a

15k

80.6k

CCAP

0.1µF

255k

100pF

51Ω

COUT

270µF

1µF

16V

33µH VOUT

3.3V

0.1µF

301k

CIN1

33µF

100V

CIN2

2.2µF

100V

1000pF

LTC3824

SENSESYNC/MODE

GATE

VFB

VCC

RSET

GND

VIN

4.5V TO 60V

0.025Ω

100pF

CIN1: SANYO 63MV68AX

CIN2: TDK C4532X7R2A225M

COUT: SANYO OSCON, 16SP270M, TDKC2012X7RIC105K

L1: D104C919AS-330M

D1: SS3H9

Q1: Si7465DP

CAP

PART NUMBER DESCRIPTION COMMENTS

LTC3891 60V, Low IQ Synchronous Step-Down DC/DC Controller with

99% Duty Cycle and Low 95ns Minimum On-Time

PLL Capable Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA

LT3845A 60V, Low IQ Synchronous Step-Down DC/DC Controller Adjustable Fixed Operating Frequency 100kHz to 500kHz,

4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, IQ = 120µA, TSSOP-16E

LTC3812-5 60V Synchronous Step-Down DC/DC Controller Constant On-Time Valley Current Mode, 4V ≤ VIN ≤ 60V,

0.8V ≤ VOUT ≤ 0.93VIN, TSSOP-16E

LTC3810 100V Synchronous Step-Down DC/DC Controller Constant On-time Valley Current Mode, 4V ≤ VIN ≤ 60V,

0.8V ≤ VOUT ≤ 0.93VIN, SSOP-28

LTC3890/LTC3890-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down DC/DC

Controllers with 99% Duty Cycle and 95ns Minimum On-Time

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,

0.8V ≤ VOUT ≤ 24V, IQ = 50µA

LTC3834/LTC3834-1

LTC3835/LTC3835-1

Low IQ, Single Output Synchronous Step-Down DC/DC

Controllers with 99% Duty Cycle

PLL Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,

0.8V ≤ VOUT ≤ 10V, IQ = 30µA/80µA

LTC3857/LTC3857-1

LTC3858/LTC3858-1

Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC

Controllers with 99% Duty Cycle

PLL Fixed Frequency 50kHz to 900kHz, 4V≤ VIN ≤ 38V,

0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA

LTC3859 Low IQ, Triple Output Buck/Buck/Boost Synchronous DC/DC

Controller

All Outputs Remain in Regulation Through Cold Crank,

2.5V ≤ VIN ≤ 38V, VOUT(BUCK) Up to 24V, VOUT(BOOST) Up to 60V,

IQ = 55µA