0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
COUT
CIN
CSS
VBIAS
CBIAS
VOUT
TPS74801
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
1.5A Low-Dropout Linear Regulator with Programmable Soft-Start
Check for Samples: TPS74801
1FEATURES
2•VOUT Range: 0.8V to 3.6V DESCRIPTION
•Ultralow VIN Range: 0.8V to 5.5V The TPS74801 low-dropout (LDO) linear regulator
•VBIAS Range 2.7V to 5.5V provides an easy-to-use robust power management
solution for a wide variety of applications.
•Low Dropout: 60mV typ at 1.5A, VBIAS = 5V User-programmable soft-start minimizes stress on the
•Power Good (PG) Output Allows Supply input power source by reducing capacitive inrush
Monitoring or Provides a Sequencing Signal current on start-up. The soft-start is monotonic and
for Other Supplies well-suited for powering many different types of
processors and ASICs. The enable input and power
•2% Accuracy Over Line/Load/Temperature good output allow easy sequencing with external
•Programmable Soft-Start Provides Linear regulators. This complete flexibility permits the user to
Voltage Startup configure a solution that meets the sequencing
•VBIAS Permits Low VIN Operation with Good requirements of FPGAs, DSPs, and other
Transient Response applications with special start-up requirements.
•Stable with Any Output Capacitor ≥2.2μFA precision reference and error amplifier deliver 2%
•Available in a Small 3mm x 3mm x 1mm accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
SON-10 and 5 x 5 QFN-20 Packages greater than or equal to 2.2μF, and is fully specified
from –40°C to +125°C. The TPS74801 is offered in a
APPLICATIONS small 3mm ×3mm SON-10 package, yielding a highly
•FPGA Applications compact, total solution size. It is also available in a 5
•DSP Core and I/O Voltages x 5 QFN-20 for compatibility with the TPS74401.
•Post-Regulation Applications
•Applications with Special Start-Up Time or
Sequencing Requirements
•Hot-Swap and Inrush Controls
Figure 2. Turn-On Response
Figure 1. Typical Application Circuit (Adjustable)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2007–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS748xx yyy z XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).(3)
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Fixed output voltages from 0.8V to 3.3V are available; minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 0.8V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ=–40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
TPS74801 UNIT
VIN, VBIAS Input voltage range –0.3 to +6 V
VEN Enable voltage range –0.3 to +6 V
VPG Power good voltage range –0.3 to +6 V
IPG PG sink current 0 to +1.5 mA
VSS Soft-start voltage range –0.3 to +6 V
VFB Feedback voltage range –0.3 to +6 V
VOUT Output voltage range –0.3 to VIN + 0.3 V
IOUT Maximum output current Internally limited
Output short-circuit duration Indefinite
PDISS Continuous total power dissipation See Thermal Information Table
TJOperating junction temperature range –40 to +150 °C
TSTG Storage junction temperature range –55 to +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
THERMAL INFORMATION TPS74801(2)
THERMAL METRIC(1) RGW DRC UNITS
20 PINS 10 PINS
θJA Junction-to-ambient thermal resistance(3) 30.5 41.5
θJCtop Junction-to-case (top) thermal resistance(4) 27.6 78
θJB Junction-to-board thermal resistance(5) N/A N/A °C/W
ψJT Junction-to-top characterization parameter(6) 0.37 0.7
ψJB Junction-to-board characterization parameter(7) 10.6 11.3
θJCbot Junction-to-case (bottom) thermal resistance(8) 4.1 6.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.
.ii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
(b) i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.ii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in ×3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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ELECTRICAL CHARACTERISTICS
At VEN = 1.1V, VIN = VOUT + 0.3V, CBIAS = 0.1μF, CIN = COUT = 10μF, CNR = 1nF, IOUT = 50mA, VBIAS = 5.0V, and TJ=–40°C to
+125°C, unless otherwise noted. Typical values are at TJ= +25°C. TPS74801
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS Bias pin voltage range 2.7 5.5 V
VREF Internal reference (Adj.) TJ= +25°C 0.796 0.8 0.804 V
Output voltage range VIN = 5V, IOUT = 1.5A VREF 3.6 V
VOUT 2.97V ≤VBIAS ≤5.5V,
Accuracy(1) –2±0.5 2 %
50mA ≤IOUT ≤1.5A
VOUT/VIN Line regulation VOUT (NOM) + 0.3 ≤VIN ≤5.5V 0.03 %/V
VOUT/IOUT Load regulation 50mA ≤IOUT ≤1.5A 0.09 %/A
IOUT = 1.5A, 60 165 mV
VIN dropout voltage(2) VBIAS –VOUT (NOM) ≥3.25V(3)
VDO VBIAS dropout voltage(2) IOUT = 1.5A, VIN = VBIAS 1.31 1.6 V
ICL Current limit VOUT = 80% ×VOUT (NOM) 2.0 5.5 A
IBIAS Bias pin current 1 2 mA
Shutdown supply current
ISHDN VEN ≤0.4V 1 50 μA
(IGND)
IFB Feedback pin current –1 0.150 1 μA
1kHz, IOUT = 1.5A, 60
VIN = 1.8V, VOUT = 1.5V
Power-supply rejection dB
(VIN to VOUT)300kHz, IOUT = 1.5A, 30
VIN = 1.8V, VOUT = 1.5V
PSRR 1kHz, IOUT = 1.5A, 50
VIN = 1.8V, VOUT = 1.5V
Power-supply rejection dB
(VBIAS to VOUT)300kHz, IOUT = 1.5A, 30
VIN = 1.8V, VOUT = 1.5V
100Hz to 100kHz,
Noise Output noise voltage 25 ×VOUT μVRMS
IOUT = 1.5A, CSS = 0.001μF
tSTR Minimum startup time RLOAD for IOUT = 1.0A, CSS = open 200 μs
ISS Soft-start charging current VSS = 0.4V 440 nA
VEN, HI Enable input high level 1.1 5.5 V
VEN, LO Enable input low level 0 0.4 V
VEN, HYS Enable pin hysteresis 50 mV
VEN, DG Enable pin deglitch time 20 μs
IEN Enable pin current VEN = 5V 0.1 1 μA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG, LO PG output low voltage IPG = 1mA (sinking), VOUT <VIT 0.3 V
IPG, LKG PG leakage current VPG = 5.25V, VOUT >VIT 0.1 1 μA
Operating junction
TJ–40 +125 °C
temperature Shutdown, temperature increasing +165
Thermal shutdown
TSD °C
temperature Reset, temperature decreasing +140
(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25V is a test condition of this device and can be adjusted by referring to Figure 8.
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t (s) =
SS
V C
I
REF SS
SS
×0.8V C (F)
0.44 A
SS
m
×
=
Thermal
Limit
Soft-Start
Discharge
OUT VOUT
FB
PG
IN
BIAS
SS
EN Hysteresis
andDeglitch
Current
Limit
UVLO
0.44 Am
0.8V
Reference
0.9 ´VREF
GND
CSS
R1
R2
(1) where tSS(s) = soft-start time in seconds.
TPS74801
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
BLOCK DIAGRAM
Table 1. Standard 1% Resistor Values for Programming the Output Voltage(1)
R1(kΩ) R2(kΩ) VOUT (V)
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1.0
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3
(1) VOUT = 0.8 ×(1 + R1/R2).
Table 2. Standard Capacitor Values for Programming the Soft-Start Time(1)
CSS SOFT-START TIME
Open 0.1ms
270pF 0.5ms
560pF 1ms
2.7nF 5ms
5.6nF 10ms
0.01μF 18ms
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OUT
OUT
FB
SS
GND
10
9
8
7
6
IN
IN
PG
BIAS
EN
1
2
3
4
5
Thermal
Pad
IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB
TPS74801
IN
EN 11
GND 12
NC 13
NC 14
SS 15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
GND
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
DEVICE INFORMATION
DRC PACKAGE RGW PACKAGE
3mm x 3mm SON 5 x 5 QFN
(TOP VIEW) (TOP VIEW)
PIN DESCRIPTIONS
NAME DRC (SON) RGW (QFN) DESCRIPTION
IN 1, 2 5-8 Input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
EN 5 11 the regulator into shutdown mode. This pin must not be left unconnected.
SS 7 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time.
If this pin is left unconnected, the regulator output soft-start ramp time is typically
200μs.
BIAS 4 10 Bias input voltage for error amplifier, reference, and internal control circuits.
Power Good pin. An open-drain, active-high output that indicates the status of
VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
PG 3 9 low-impedance state. A pull-up resistor from 10kΩto 1MΩshould be connected
from this pin to a supply of up to 5.5V. The supply can be higher than the input
voltage. Alternatively, the PG pin can be left unconnected if output monitoring is
not necessary.
Feedback pin. The feedback connection to the center tap of an external resistor
FB 8 16 divider network that sets the output voltage. This pin must not be left floating.
OUT 9, 10 1, 18-20 Regulated output voltage. A small capacitor (total typical capacitance ≥2.2μF,
ceramic) is needed from this pin to ground to assure stability.
NC N/A 2-4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
GND 6 12 Ground
Thermal Pad —Should be soldered to the ground plane for increased thermal performance.
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0.20
0.15
0.10
0.05
0
-0.05
-0.01
-0.15
-0.20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ChangeinV (%)
OUT
V V-
IN OUT (V)
5.0
+125 C°
+25 C°
- °40 C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ChangeinV (%)
OUT
V V-
BIAS OUT (V)
4.0
+125 C°+25 C°
- °40 C
1.2
1.0
0.8
0.6
0.4
0.2
0
010 20 30 40
ChangeinV (%)
OUT
I (mA)
OUT
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.05 0.5 1.0
ChangeinV (%)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°- °40 C
100
90
80
70
60
50
40
30
20
10
0
00.5 1.0
V (V V )(mV)-
DO IN OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
200
180
160
140
120
100
80
60
40
20
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDO IN
(V -VOUT)(mV)
VBIAS -VOUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =1.5A
OUT
TPS74801
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1μF, CBIAS = 4.7μF, and COUT = 10μF,
unless otherwise noted.
VIN LINE REGULATION VBIAS LINE REGULATION
Figure 3. Figure 4.
LOAD REGULATION LOAD REGULATION
Figure 5. Figure 6.
VIN DROPOUT VOLTAGE vs VIN DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ) (VBIAS –VOUT) AND TEMPERATURE (TJ)
Figure 7. Figure 8.
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200
180
160
140
120
100
80
60
40
20
0
01.51.00.5 2.0 2.5 3.0 3.5 4.0
V (mV)
DO IN OUT
(V V )-
V V-
BIAS OUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =0.5A
OUT
2200
2000
1800
1600
1400
1200
1000
800
600
00.5 1.0
V (V -
DO BIAS V )(mV)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
C =1nF
SS
I =100mA
OUT
I =1.5A
OUT
1
0.1
0.01
100 1k 10k
OutputSpectralNoiseDensity(mV/Ö)
Hz
Frequency(Hz)
100k
C =1nF
SS
C =0nF
SS
C =10nF
SS
I =100mA
OUT
V =1.2V
OUT
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1μF, CBIAS = 4.7μF, and COUT = 10μF,
unless otherwise noted.
VIN DROPOUT VOLTAGE vs VBIAS DROPOUT VOLTAGE vs
(VBIAS –VOUT) AND TEMPERATURE (TJ) IOUT AND TEMPERATURE (TJ)
Figure 9. Figure 10.
VBIAS PSRR vs FREQUENCY VIN PSRR vs FREQUENCY
Figure 11. Figure 12.
VIN PSRR vs (VIN –VOUT) NOISE SPECTRAL DENSITY
Figure 13. Figure 14.
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500
475
450
425
400
375
350
325
300
-50 -25 0 25 50 75 100
I (nA)
SS
JunctionTemperature( C)°
125
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
02 4 6 8 10 12
PGCurrent(mA)
TPS74801
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1μF, CBIAS = 4.7μF, and COUT = 10μF,
unless otherwise noted.
BIAS PIN CURRENT vs BIAS PIN CURRENT vs
IOUT AND TEMPERATURE (TJ) VBIAS AND TEMPERATURE (TJ)
Figure 15. Figure 16.
SOFT-START CHARGING CURRENT (ISS) vs
TEMPERATURE (TJ) LOW-LEVEL PG VOLTAGE vs CURRENT
Figure 17. Figure 18.
CURRENT LIMIT vs (VBIAS –VOUT)
Figure 19.
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100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
100mV/div
100mV/div
1A/div
100mV/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
1A/ sm
50mA
C =470 F(OSCON)OUT m
C =1nF
SS
1.5A
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
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TYPICAL CHARACTERISTICS
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 1A, VEN = VIN = 1.8V, VOUT = 1.5V, CIN = 1μF, CBIAS = 4.7μF, and
COUT = 10μF, unless otherwise noted.
VBIAS LINE TRANSIENT VIN LINE TRANSIENT
Figure 20. Figure 21.
OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE
Figure 22. Figure 23.
POWER-UP/POWER-DOWN
Figure 24.
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VOUT
COUT
10 Fm
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
CIN
1 Fm
CSS
VBIAS
CBIAS
1 Fm
V =0.8
OUT ´1+ R1
R2
)(
TPS74801
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SBVS074J –JANUARY 2007–REVISED JANUARY 2012
APPLICATION INFORMATION
The TPS74801 belongs to a family of low dropout R1and R2can be calculated for any output voltage
regulators that feature soft-start capability. These using the formula shown in Figure 25. Refer to
regulators use a low current bias input to power all Table 1 for sample resistor values of common output
internal control circuitry, allowing the NMOS pass voltages. In order to achieve the maximum accuracy
transistor to regulate very low input and output specifications, R2should be ≤4.99kΩ.
voltages.
The use of an NMOS-pass FET offers several critical INPUT, OUTPUT, AND BIAS CAPACITOR
advantages for many applications. Unlike a PMOS REQUIREMENTS
topology device, the output capacitor has little effect The device is designed to be stable for all available
on loop stability. This architecture allows the types and values of output capacitors ≥2.2μF. The
TPS74801 to be stable with any capacitor type of device is also stable with multiple capacitors in
value 2.2μF or greater. Transient response is also parallel, which can be of any type or value.
superior to PMOS topologies, particularly for low VIN
applications. The capacitance required on the IN and BIAS pins
strongly depends on the input supply source
The TPS74801 features a programmable impedance. To counteract any inductance in the
voltage-controlled soft-start circuit that provides a input, the minimum recommended capacitor for VIN
smooth, monotonic start-up and limits startup inrush and VBIAS is 1μF. If VIN and VBIAS are connected to
currents that may be caused by large capacitive the same supply, the recommended minimum
loads. A power good (PG) output is available to allow capacitor for VBIAS is 4.7μF. Good quality, low ESR
supply monitoring and sequencing of other supplies. capacitors should be used on the input; ceramic X5R
An enable (EN) pin with hysteresis and deglitch and X7R capacitors are preferred. These capacitors
allows slow-ramping signals to be used for should be placed as close the pins as possible for
sequencing the device. The low VIN and VOUT optimum performance.
capability allows for inexpensive, easy-to-design, and
efficient linear regulation between the multiple supply
voltages often present in processor-intensive TRANSIENT RESPONSE
systems. The TPS74801 was designed to have excellent
Figure 25 illustrates the typical application circuit for transient response for most applications with a small
the TPS74801 adjustable output device. amount of output capacitance. In some cases, the
transient response may be limited by the transient
response of the input supply. This limitation is
especially true in applications where the difference
between the input and output is less than 300mV. In
this case, adding additional input capacitance
improves the transient response much more than just
adding additional output capacitance would do. With
a solid input supply, adding additional output
capacitance reduces undershoot and overshoot
during a transient event; refer to Figure 22 in the
Typical Characteristics section. Because the
TPS74801 is stable with output capacitors as low as
2.2μF, many applications may then need very little
Figure 25. Typical Application Circuit for the capacitance at the LDO output. For these
TPS74801 (Adjustable) applications, local bypass capacitance for the
powered device may be sufficient to meet the
transient requirements of the application. This design
reduces the total solution cost by avoiding the need
to use expensive, high-value capacitors at the LDO
output.
Copyright ©2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS74801
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN V =5V 5%
BIAS ±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
COUT
t =
SS
(V C )´
REF SS
ISS
t =
SSCL
(V C )´
OUT(NOM) OUT
ICL(MIN)
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN
VIN
V =3.3V 5%
BIAS ±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
COUT
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
DROPOUT VOLTAGE The second specification (shown in Figure 27) is
referred to as VBIAS Dropout and applies to
The TPS74801 offers very low dropout performance, applications where IN and BIAS are tied together.
making it well-suited for high-current, low VIN/low This option allows the device to be used in
VOUT applications. The low dropout of the TPS74801 applications where an auxiliary bias voltage is not
allows the device to be used in place of a dc/dc available or low dropout is not required. Dropout is
converter and still achieve good efficiency. This limited by BIAS in these applications because VBIAS
provides designers with the power architecture for provides the gate drive to the pass FET; therefore,
their application to achieve the smallest, simplest, VBIAS must be 1.6V above VOUT. Because of this
and lowest cost solution. usage, IN and BIAS tied together easily consume
huge power. Pay attention not to exceed the power
There are two different specifications for dropout rating of the IC package.
voltage with the TPS74801. The first specification
(shown in Figure 26) is referred to as VIN Dropout and
is used when an external bias voltage is applied to PROGRAMMABLE SOFT-START
achieve low dropout. This specification assumes that The TPS74801 features a programmable, monotonic,
VBIAS is at least 3.25V(1) above VOUT, which is the voltage-controlled soft-start that is set with an
case for VBIAS when powered by a 5.0V rail with 5% external capacitor (CSS). This feature is important for
tolerance and with VOUT = 1.5V. If VBIAS is higher than many applications because it eliminates power-up
VOUT +3.25V(1), VIN dropout is less than specified. initialization problems when powering FPGAs, DSPs,
or other processors. The controlled voltage ramp of
the output also reduces peak inrush current during
start-up, minimizing start-up transient events to the
input power bus.
To achieve a linear and monotonic soft-start, the
TPS74801 error amplifier tracks the voltage ramp of
the external soft-start capacitor until the voltage
exceeds the internal reference. The soft-start ramp
time depends on the soft-start charging current (ISS),
soft-start capacitance (CSS), and the internal
reference voltage (VREF), and can be calculated using
Equation 1:
(1)
Figure 26. Typical Application of the TPS74801
Using an Auxiliary Bias Rail If large output capacitors are used, the device current
limit (ICL) and the output capacitor may set the
start-up time. In this case, the start-up time is given
by Equation 2:
(2)
where:
VOUT(NOM) is the nominal output voltage,
COUT is the output capacitance, and
ICL(MIN) is the minimum current limit for the device.
In applications where monotonic startup is required,
the soft-start time given by Equation 1 should be set
greater than Equation 2.
The maximum recommended soft-start capacitor is
0.015μF. Larger soft-start capacitors can be used and
Figure 27. Typical Application of the TPS74801 do not damage the device; however, the soft-start
Without an Auxiliary Bias Rail capacitor discharge circuit may not be able to fully
discharge the soft-start capacitor when enabled.
Soft-start capacitors larger than 0.015μF could be a
(1) 3.25V is a test condition of this device and can be adjusted by problem in applications where it is necessary to
referring to Figure 8.
12 Submit Documentation Feedback Copyright ©2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
V ( V )=25m
N RMS xV (V)
OUT
mVRMS
V
( )
TPS74801
GND SS
OUT
FB
EN
IN
BIAS
VIN VOUT
R2
R1
CSS
CIN
C
VBIAS
CBIAS
R
COUT
TPS74801
www.ti.com
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
rapidly pulse the enable pin and still require the 0.001μF soft-start capacitor, the output noise is
device to soft-start from ground. CSS must be reduced by half and is typically 30μVRMS for a 1.2V
low-leakage; X7R, X5R, or C0G dielectric materials output (10Hz to 100kHz). Further increasing CSS has
are preferred. Refer to Table 2 for suggested little effect on noise. Because most of the output
soft-start capacitor values. noise is generated by the internal reference, the
noise is a function of the set output voltage. The RMS
noise with a 0.001μF soft-start capacitor is given in
SEQUENCING REQUIREMENTS Equation 3:
VIN, VBIAS, and VEN can be sequenced in any order
without causing damage to the device. However, for (3)
the soft-start function to work as intended, certain
sequencing rules must be applied. Connecting EN to The low output noise of the TPS74801 makes it a
IN is acceptable for most applications, as long as VIN good choice for powering transceivers, PLLs, or other
is greater than 1.1V and the ramp rate of VIN and noise-sensitive circuitry.
VBIAS is faster than the set soft-start ramp rate. If the
ramp rate of the input sources is slower than the set ENABLE/SHUTDOWN
soft-start time, the output tracks the slower supply
minus the dropout voltage until it reaches the set The enable (EN) pin is active high and is compatible
output voltage. If EN is connected to BIAS, the device with standard digital signaling levels. VEN below 0.4V
soft-starts as programmed, provided that VIN is turns the regulator off, while VEN above 1.1V turns the
present before VBIAS. If VBIAS and VEN are present regulator on. Unlike many regulators, the enable
before VIN is applied and the set soft-start time has circuitry has hysteresis and deglitching for use with
expired, then VOUT tracks VIN. If the soft-start time has relatively slowly ramping analog signals. This
not expired, the output tracks VIN until VOUT reaches configuration allows the TPS74801 to be enabled by
the value set by the charging soft-start capacitor. connecting the output of another supply to the EN
Figure 28 shows the use of an RC-delay circuit to pin. The enable circuitry typically has 50mV of
hold off VEN until VBIAS has ramped. This technique hysteresis and a deglitch circuit to help avoid on-off
can also be used to drive EN from VIN. An external cycling as a result of small glitches in the VEN signal.
control signal can also be used to enable the device The enable threshold is typically 0.8V and varies with
after VIN and VBIAS are present. temperature and process variations. Temperature
NOTE: When VBIAS and VEN are present and VIN is variation is approximately –1mV/°C; process variation
not supplied, this device outputs approximately 50μAaccounts for most of the rest of the variation to the
of current from OUT. Although this condition does not 0.4V and 1.1V limits. If precise turn-on timing is
cause any damage to the device, the output current required, a fast rise-time signal must be used to
may charge up the OUT node if total resistance enable the TPS74801.
between OUT and GND (including external feedback If not used, EN can be connected to either IN or
resistors) is greater than 10kΩ.BIAS. If EN is connected to IN, it should be
connected as close as possible to the largest
capacitance on the input to prevent voltage droops on
that line from triggering the enable circuit.
POWER GOOD
The power good (PG) pin is an open-drain output and
can be connected to any 5.5V or lower rail through an
external pull-up resistor. This pin requires at least
1.1V on VBIAS in order to have a valid output. The PG
output is high-impedance when VOUT is greater than
Figure 28. Soft-Start Delay Using an RC Circuit to VIT + VHYS. If VOUT drops below VIT or if VBIAS drops
Enable the Device below 1.9V, the open-drain output turns on and pulls
the PG output low. The PG pin also asserts when the
device is disabled. The recommended operating
OUTPUT NOISE condition of PG pin sink current is up to 1mA, so the
The TPS74801 provides low output noise when a pull-up resistor for PG should be in the range of 10kΩ
soft-start capacitor is used. When the device reaches to 1MΩ. If output voltage monitoring is not needed,
the end of the soft-start cycle, the soft-start capacitor the PG pin can be left floating.
serves as a filter for the internal reference. By using a
Copyright ©2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS74801
P =(V V ) I- ´
D IN OUT OUT
R =
qJA
(+125 C T )° - A
PD
140
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
Board Copper Area ( )in2
DRC
RGW
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
INTERNAL CURRENT LIMIT R1in Figure 25 should be connected as close as
possible to the load. If BIAS is connected to IN, it is
The TPS74801 features a factory-trimmed, accurate recommended to connect BIAS as close to the sense
current limit that is flat over temperature and supply point of the input supply as possible. This connection
voltage. The current limit allows the device to supply minimizes the voltage drop on BIAS during transient
surges of up to 2A and maintain regulation. The conditions and can improve the turn-on response.
current limit responds in approximately 10μs to
reduce the current during a short-circuit fault. Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
The internal current limit protection circuitry of the thermal pad is critical to avoiding thermal shutdown
TPS74801 is designed to protect against overload and ensuring reliable operation. Power dissipation of
conditions. It is not intended to allow operation above the device depends on input voltage and load
the rated current of the device. Continuously running conditions and can be calculated using Equation 4:
the TPS74801 above the rated current degrades
device reliability. (4)
Power dissipation can be minimized and greater
THERMAL PROTECTION efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
Thermal protection disables the output when the required output voltage regulation.
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction On both the SON (DRC) and QFN (RGW) packages,
temperature cools to approximately +140°C, the the primary conduction path for heat is through the
output circuitry is enabled. Depending on power exposed pad to the printed circuit board (PCB). The
dissipation, thermal resistance, and ambient pad can be connected to ground or be left floating;
temperature the thermal protection circuit may cycle however, it should be attached to an appropriate
on and off. This cycling limits the dissipation of the amount of copper PCB area to ensure the device
regulator, protecting it from damage as a result of does not overheat. The maximum junction-to-ambient
overheating. thermal resistance depends on the maximum ambient
temperature, maximum device junction temperature,
Activation of the thermal protection circuit indicates and power dissipation of the device and can be
excessive power dissipation or inadequate calculated using Equation 5:
heatsinking. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design (5)
(including heatsink), increase the ambient
temperature until thermal protection is triggered; use Knowing the maximum RθJA, the minimum amount of
worst-case loads and signal conditions. For good PCB copper area needed for appropriate heatsinking
reliability, thermal protection should trigger at least can be estimated using Figure 29.
+40°C above the maximum expected ambient
condition of the application. This condition produces a
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
The internal protection circuitry of the TPS74801 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74801 into thermal
shutdown degrades device reliability.
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage drop on the input of the device during load Note: θJA value at board size of 9in2(that is, 3in ×
transients, the capacitance on IN and BIAS should be 3in) is a JEDEC standard.
connected as close as possible to the device. This Figure 29. θJA vs Board Size
capacitance also minimizes the effects of parasitic
inductance and resistance of the input source and
can, therefore, improve stability. To achieve optimal
transient performance and accuracy, the top side of
14 Submit Documentation Feedback Copyright ©2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
12
10
8
6
4
2
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
Board Copper Area (in )
2
51 3 7 9
YJT
YJB
DRC
RGW
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
TPS74801
www.ti.com
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
Figure 29 shows the variation of θJA as a function of By looking at Figure 30, the new thermal metrics (ΨJT
ground plane copper area in the board. It is intended and ΨJB) have very little dependency on board size.
only as a guideline to demonstrate the effects of heat That is, using ΨJT or ΨJB with Equation 6 is a good
spreading in the ground plane and should not be way to estimate TJby simply measuring TTor TB,
used to estimate actual thermal performance in real regardless of the application board size.
application environments.
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
ESTIMATING JUNCTION TEMPERATURE
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older θJC,Top parameter is listed as
well.
(6) Figure 30. ΨJT and ΨJB vs Board Size
Where PDis the power dissipation shown by
Equation 4, TTis the temperature at the center-top of For a more detailed discussion of why TI does not
the IC package, and TBis the PCB temperature recommend using θJC(top) to determine thermal
measured 1mm away from the IC package on the characteristics, refer to application report SBVA025,
PCB surface (see Figure 31). Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
NOTE: Both TTand TBcan be measured on actual application report SPRA953,IC Package Thermal
application boards using a thermo-gun (an infrared Metrics, also available on the TI website.
thermometer).
For more information about measuring TTand TB, see
the application note SBVA025,Using New Thermal
Metrics, available for download at www.ti.com.
Copyright ©2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS74801
(a) Example DRC (SON) Package Measurement
T on PCB
B
T on of Itop
TC
1mm
(b) Example RGW (QFN) Package Measurement
1mm
T on top
of IC
T
T on PCB
surface
B
TPS74801
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
www.ti.com
Figure 31. Measuring Points for TTand TB
16 Submit Documentation Feedback Copyright ©2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
TPS74801
www.ti.com
SBVS074J –JANUARY 2007–REVISED JANUARY 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (November 2010) to Revision J Page
•Changed TJrange in Absolute Maximum Ratings table ....................................................................................................... 2
Changes from Revision H (October, 2010) to Revision I Page
•Corrected equation for Table 2 ............................................................................................................................................. 5
Copyright ©2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS74801
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS74801DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801TDRCRQ1 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jan-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS74801, TPS74801-Q1 :
•Catalog: TPS74801
•Automotive: TPS74801-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS74801DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74801TDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS74801DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS74801DRCT SON DRC 10 250 210.0 185.0 35.0
TPS74801RGWR VQFN RGW 20 3000 367.0 367.0 35.0
TPS74801RGWT VQFN RGW 20 250 210.0 185.0 35.0
TPS74801TDRCRQ1 SON DRC 10 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2012
Pack Materials-Page 2
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