Si9110, Si9111 Vishay Siliconix High-Voltage Switchmode Controllers DESCRIPTION FEATURES The Si9110/9111 are BiC/DMOS integrated circuits designed for use as high-performance switchmode controllers. A high-voltage DMOS input allows the controller to work over a wide range of input voltages (10 to 120 VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce internal power consumption to less than 10 mW. * * * * * * * * A push-pull output driver provides high-speed switching for MOSPOWER devices large enough to supply 50 W of output power. When combined with an output MOSFET and transformer, the Si9110/9111 can be used to implement single-ended power converter topologies (i.e., flyback, forward, and cuk). 10 V to 120 V Input Range Current-Mode Control High-Speed, Source-Sink Output Drive High Efficiency Operation (> 80 %) Internal Start-Up Circuit Internal Oscillator (1 MHz) SHUTDOWN and RESET Reference Selection Si9110 - 1 % Si9111 - 10 % The Si9110/9111 are available in both standard and lead (Pb)-free 14-pin plastic DIP and SOIC packages which are specified to operate over the industrial temperature range of - 40 C to 85 C. FUNCTIONAL BLOCK DIAGRAM FB COMP 14 OSC IN DISCHARGE 13 9 8 Error Amplifier VREF OSC OUT 7 OSC To VCC - 10 Clock (1/2 fOSC) + 4V 2V - Ref Gen Current-Mode Comparator 4 OUTPUT R + Q 5 - VIN S + 1 BIAS VCC +VIN Current Sources To Internal Circuits C/L Comparator 1.2 V 3 VCC 6 2 8.1 V + Undervoltage Comparator S Q R 11 12 SENSE SHUTDOWN RESET + 8.6 V Pre-Regulator/Start-Up Document Number: 70004 S11-0975-Rev. I, 16-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9110, Si9111 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Voltages Referenced to - VIN (Note: VCC < + VIN + 0.3 V) VCC +VIN Logic Inputs (RESET, SHUTDOWN, OSC IN, OSC OUT) Linear Inputs (FEEDBACK, SENSE, BIAS, VREF) HV Pre-Regulator Input Current (continuous) Storage Temperature Operating Temperature Junction Temperature (TJ) Limit 14-Pin Plastic DIP (J Suffix)b 14-Pin SOIC (Y Suffix)c 14-Pin Plastic DIP 14-Pin SOIC Power Dissipation (Package)a Thermal Impedance (JA) Unit 15 120 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 5 - 65 to 150 - 40 to 85 150 750 900 167 140 V mA C mW C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 6 mW/C above 25 C. c. Derate 7.2 mW/C above 25 C. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Voltages Referenced to - VIN VCC + VIN fOSC ROSC Linear Inputs Digital Inputs Limit Unit 9.5 to 13.5 10 to 120 40 kHzto 1 MHz 25 kto 1 M 0 to VCC - 3 0 to VCC V V SPECIFICATIONSa Parameter Symbol Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 k, ROSC = 330 k D Suffix - 40 C to 85 C Temp.b Min.d Typ.c Max.d Si9110 Room 3.92 4.0 4.08 Si9111 Room 3.60 4.0 4.40 Si9110 Full 3.86 Unit Reference Output Voltage Impedancee Output Short Circuit Current Temperature Stabilitye Oscillator Maximum Frequencye VR ZOUT ISREF TREF fMAX Initial Accuracy fOSC Voltage Stability f/f TOSC Temperature Coefficiente www.vishay.com 2 OSC IN = - VIN (OSC Disabled) RL = 10 M Si9111 VREF = - VIN ROSC = 0 ROSC = 330 k, See Note f ROSC = 150 k, See Note f f/f = f(13.5 V) - f(9.5 V)/f(9.5 V) 4.14 Full 3.52 Room Room Full 15 70 30 100 0.5 45 130 1.0 Room Room Room Room Full 1 80 160 3 100 200 10 200 120 240 15 500 V 4.46 k A mV/C MHz kHz % ppm/C Document Number: 70004 S11-0975-Rev. I, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9110, Si9111 Vishay Siliconix SPECIFICATIONSa Parameter Symbol Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 k, ROSC = 330 k D Suffix - 40 C to 85 C Temp.b Min.d Typ.c Max.d Si9110 Room 3.96 4.00 4.04 Si9111 Room 3.60 4.00 4.40 Unit Error Amplifier Feedback Input Voltage VFB Input BIAS Current IFB Input OFFSET Voltage VOS Open Loop Voltage Gaine AVOL Unity Gain Bandwidth e Dynamic Output Impedancee BW Power Supply Rejection OSC IN = - VIN, VFB = 4 V PSRR V Room 25 500 nA Room 15 40 mV OSC IN = - VIN (OSC Disabled) Room 60 80 dB Room 1 1.3 MHz Room 1000 2000 Source (VFB = 3.4 V) Room - 2.0 - 1.4 Sink (VFB = 4.5 V) Room 0.12 0.15 9.5 V VCC 13.5 V Room 50 70 1.0 ZOUT IOUT Output Current FB Tied to COMP OSC IN = - VIN, (OSC Disabled) mA dB Current Limit Threshold Voltage e Delay to Output Pre-Regulator/Start-Up VSOURCE VFB = 0 Room td VSENSE = 1.5 V, See Figure 1 Room 1.2 1.4 V 100 150 ns 10 A Input Voltage + VIN IIN = 10 A Room Input Leakage Current + IIN VCC 9.4 V Room Pre-Regulator Start-Up Current ISTART Pulse Width 300 s, VCC = VULVO Room 8 15 VCC Pre-Regulator Turn-Off Threshold Voltage VREG IPRE-REGULATOR = 10 A Room 7.8 8.6 9.4 Undervoltage Lockout VUVLO Room 7.0 8.1 8.9 VREG - VUVLO VDELTA Room 0.3 0.6 Room 0.45 0.6 1.0 mA Room 10 15 20 A 50 100 120 V mA V Supply Supply Current Bias Current ICC VLOAD 75 pF (Pin 4) IBIAS Logic SHUTDOWN Delaye tSD CL = 500 pF, VSENSE = - VIN, See Figure 2 Room SHUTDOWN Pulse Widthe tSW See Figure 3 Room 50 RESET Pulse Widthe Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage tRW Room 50 Room 25 VIL Room Input High Voltage VIH Room Input Current Input Voltage High IIH VIN = 10 V Room Input Current Input Voltage Low IIL VIN = 0 V Room - 35 Output High Voltage VOH IOUT = - 10 mA 9.7 9.5 Output Low Voltage VOL IOUT = 10 mA Output Resistance ROUT IOUT = 10 mA, Source or Sink Room Full Room Full Room Full Room tLW See Figure 3 ns 2.0 8.0 1 5 - 25 V A Output Rise Timee tr CL = 500 pF tf Room Fall Time Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25 C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = 5 pF. e Document Number: 70004 S11-0975-Rev. I, 16-May-11 20 25 40 0.30 0.50 30 50 75 40 75 V ns www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9110, Si9111 Vishay Siliconix TIMING WAVEFORMS 1.5 V SENSE 0 VCC SHUTDOWN 0 - tr 10 ns 50 % tSD td VCC tf 10 ns 50 % VCC 90 % OUTPUT 90 % OUTPUT 0 0 - - Figure 2. Figure 1. tSW VCC SHUTDOWN 0 50 % 50 % tr, tf 10 ns tLW VCC RESET 0 50 % 50 % 50 % tRW Figure 3. TYPICAL CHARACTERISTICS 1M 140 VCC = - VIN 120 f OUT (Hz) +V IN (V) 100 80 60 100 k 40 20 0 10 k 10 15 +IIN (mA) Figure 4. + VIN vs. + IIN at Start-Up www.vishay.com 4 20 10 k 100 k 1M rOSC () Figure 5. Output Switching Frequency vs. Oscillator Resistance Document Number: 70004 S11-0975-Rev. I, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9110, Si9111 Vishay Siliconix PIN CONFIGURATIONS AND ORDERING INFORMATION Dual-In-Line and SOIC BIAS ORDERING INFORMATION Part Number 1 14 FB +VIN 2 13 COMP SENSE 3 12 RESET Si9110DY-T1-E3 OUTPUT 4 11 SHUTDOWN Si9111DY - VIN 5 10 VREF Si9111DY-T1 VCC 6 9 DISCHARGE Si9111DY-T1-E3 OSC OUT 7 8 OSC IN Si9110DJ Package Si9110DY-T1 Si9110DJ-E3 Top View Temperature Range Si9110DY Si9111DJ SOIC-14 - 40 C to 85 C PDIP-14 Si9111DJ-E3 DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9110/ 9111 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, + VIN (pin 2) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between + VIN and VCC (pin 6). This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 8.6 V. If VCC is not forced to exceed the 8.6 V threshold, then VCC will be regulated to a nominal value of 8.6 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the undervoltage lockout threshold (typically 8.1 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 8.6 V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48 V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 6 gives the typical pre-regulator current at BiC/DMOS as a function of input voltage. BIAS sections and the pull-up current for the SHUDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 A. Reference Section The reference section of the Si9110 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the Si9110 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1 % of 4 V. This compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Applications which use a separate external reference, such as non-isolated converter topologies and circuits employing optical coupling in the feedback loop, do not require a trimmed voltage reference with 1 % accuracy. The Si9111 accommodates the requirements of these applications at a lower cost, by leaving the reference voltage untrimmed. The 10 % accurate reference thus provided is sufficient to establish a dc bias point for the error amplifier. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. To properly set the bias for the Si9110/9111, a 390 k resistor should be tied from BIAS (pin 1) to - VIN (pin 5). This determines the magnitude of bias current in all of the analog Document Number: 70004 S11-0975-Rev. I, 16-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9110, Si9111 Vishay Siliconix DETAILED DESCRIPTION (CONT'D) Oscillator Section Table 1. Truth Table for the SHUTDOWN and RESET Pins The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to - VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50 % by locking the switching frequency to one half of the oscillator frequency. SHUTDOWN H RESET Output H H Normal Operation Normal Operation (No Change) L H L L Off (Not Latched) Off (Latched) L Off (Latched, No Change) Remote synchronization is accomplished by capacitive coupling of a positive SYNC pulse into the OSC IN (pin 8) terminal. For a 5 V pulse amplitude and 0.5 s pulse width, typical values would be 100 pF in series with 3 k to pin 8. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. SHUTDOWN and RESET Output Driver SHUTDOWN (pin 11) and RESET (pin 12) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. The push-pull driver output has a typical on-resistance of 20 . Maximum switching times are specified at 75 ns for a 500 pF load. This is sufficient to directly drive MOSFETs such as the 2N7004, 2N7005, IRFD120 and IRFD220. Larger devices can be driven, but switching times will be longer, resulting in higher switching losses. In order to drive large MOSPOWER devices, it is necessary to use an external driver IC, such as the Vishay Siliconix D469A. The D469A can switch very large devices such as the SMM20N50 (500 V, 0.3 ) in approximately 100 ns. APPLICATIONS 1N5822 +5V at 0.75 A GND OSC SYNC PULSE (If Needed) 220 F 3k 2 0.022 F 0.1 F 20 F 240 k FEEDBACK 47 F 100 pF 8 13 14 1N5819 -5V at 0.25 A 150 k 1N4148 6 VCC 0.1 F 390 k 7 Si9110 10 4 1 3 5 9 To Pin 6 VCC 2N7004 1 F 18 k Feedback To Pin 14 12 k 1 1/ W 2 - 48 V Figure 6. 5 Watt Power Supply for Telecom Applications Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70004. www.vishay.com 6 Document Number: 70004 S11-0975-Rev. I, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOIC (NARROW): 14-LEAD (POWER IC ONLY) MILLIMETERS 14 13 12 11 10 9 Dim A A1 B C D E e H L O 8 E 2 3 4 5 6 7 D A e B Document Number: 72809 28-Jan-04 A1 0.25 (GAGE PLANE) 1 H INCHES Min Max Min Max 1.35 1.75 0.053 0.069 0.10 0.20 0.004 0.008 0.38 0.51 0.015 0.020 0.18 0.23 0.007 0.009 8.55 8.75 0.336 0.344 3.8 4.00 0.149 0.157 1.27 BSC 0.050 BSC 5.80 6.20 0.228 0.244 0.50 0.93 0.020 0.037 0_ 8_ 0_ 8_ ECN: S-40080--Rev. A, 02-Feb-04 DWG: 5914 C ALL LEADS L O 0.101 mm 0.004 www.vishay.com 1 Package Information Vishay Siliconix PDIP: 14-LEAD (POWER IC ONLY) 14 13 12 11 10 9 8 E E1 1 2 3 4 5 6 7 D S Q1 A A1 B1 e1 L B Dim A A1 B B1 C D E E1 e1 eA L Q1 S 15 MAX C eA MILLIMETERS Min Max INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 17.27 19.30 0.680 0.760 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 1.27 2.03 0.050 0.080 1.02 2.03 0.040 0.080 ECN: S-40081--Rev. A, 02-Feb-04 DWG: 5919 Document Number: 72814 28-Jan-04 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000