1999 Microchip Technology Inc. DS21161E-page 1
FEATURES
• Single supply with operation down to 2.5V
• Comp letely implements DDC1/DDC2
interface for monitor identification, including
recovery to DDC1
• Low power CMOS techno logy
- 1 mA typical active cur rent
-10 µA standby current typical at 5.5V
• 2-wire serial interface b us, I2C compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle ( including au to-e rase)
• Hardware write-protect pin
• Page-write buffer for up to eight bytes
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +70°C
DESCRIPTION
The Microchip Technology Inc. 24LCS21A is a 128 x 8-
bit dual-m ode Ele ctrically Er asab le PROM. Th is de v ice
is designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h t o 7F h, c lock e d by the VCL K pin . A valid hig h
to lo w tr ansi tion o n t he SCL pi n wi ll ca use t he de v ice to
enter the transition mode, and look for a valid control
byte on the I2C bus. If it detects a valid control byte from
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LCS21A also enables the user to
write-protect the entire memory array using its write-
protect pin. The 24LCS21A is available in a standard
8-pin PD IP and SO IC pack age in bo th commerc ial an d
industrial temperature ranges.
PACKA GE TYPES
BLOCK DIAG RAM
PDIP
SOIC
24LCS21A
NC
NC
WP
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
24LCS21A
NC
NC
WP
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA SCL
VCC
VSS
VCLK
24LCS21A
1K 2.5V Dual Mode I2C™ Serial EEPROM
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
24LCS21A
DS21161E-page 2 1999 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VCC........................................................................7.0V
All inputs and outputs w.r.t. VSS .....-0.6V to VCC +1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds)..+300°C
ESD protection on all pins ..................................... ≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect dev ice reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
WP Write Protect (active low)
VSS Ground
SDA Serial Add ress/Data I/O
SCL Serial Clock (Bi-dire ct ion al Mo de)
VCLK Serial Clock (Transmit-Only Mode)
VCC +2.5V to 5.5V Power Supply
NC No Conn ect ion
TABLE 1-2: DC CHARACTERISTICS
VCC = +2.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb =-40°C to +85°C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage VIH
VIL 0.7 VCC
——
0.3 VCC V
V
Input levels on VCLK pin:
High level input voltage
Low level input voltage VIH
VIL 2.0
——
0.2 VCC V
VVCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
Hysteresis of Schmitt trigger inputs VHYS .05 VCC —V(Note)
Low level output voltage VOL1—0.4VIOL = 3 mA, VCC = 2.5V (Note)
Low level output voltage VOL2—0.6VIOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 µAVIN = 0.1V to VCC
Output leakage current ILO -10 10 µAVOUT = 0.1V to VCC
Pin capacitance (all inputs/outputs) Cin, Cout — 10 pF VCC = 5.0V (Note)
Tamb = 25°C, FCLK = 1 MHz
Operating curren t ICC Write
ICC Read —
—3
1mA
mA VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —
—30
100 µA
µAVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note: This parameter is periodically sampled and not 100% tested.
1999 Microchip Technology Inc. DS21161E-page 3
24LCS21A
TABLE 1-3: AC CHARACTERISTICS
Parameter Symbol Vcc= 2.5-4.5V
Standard Mode Vcc= 4.5 - 5.5V
Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK —100—400kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF— 300 — 300 ns (Note 1)
START condition hold time THD:STA 400 0 — 600 — ns After this period the first clo ck
pul se is generated
START condition setup
time TSU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition s etup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL ma ximum TOF — 250 20 + 0.1
CB250 ns (Note 1) , CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins) TSP — 50 — 50 ns (Note 3)
Write cycl e time TWR — 10 — 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA — 2000 — 1000 ns
VCLK high time TVHIGH 4000 — 600 — ns
VCLK low time TVLOW 4700 — 1300 — ns
VCLK setup time TVHST 0—0—ns
VCLK hold time TSPVL 4000 — 600 — ns
Mode transition time TVHZ — 1000 — 500 ns
Transmit-Only power up
time TVPU 0—0—ns
Input filter spike suppres-
sion (VCLK pin) TSPV — 100 — 100 ns
Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specific ations are due to Schmitt trigg er inputs whic h provide noise and spike
suppression. This eliminates the need for a TI specificati on for standard oper a tio n.
4: This parameter is not t est ed but guara nte ed by charact erizati on. F or e ndu rance estimates i n a s pec ifi c a ppl i-
cation, please consult the Total Endurance Model which can be obtained on our website.
24LCS21A
DS21161E-page 4 1999 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21A is designed to comply to the DDC Stan-
dard proposed by VESA (Figure 3-3) with the exception
that it is not Access.bus capable. It operates in two
modes, t he Transm it-Onl y Mode an d the Bi -direc tional
Mode. There is a separate 2-wire protocol to support
each mode, each having a separate clock input but
sharing a common data line (SDA). The device enters
the Transmit-Only Mode upon power-up. In this mode,
the device transmits data bits on the SDA pin in
respons e to a c loc k signal on the VCLK pin. The de vic e
will remain in this mode until a valid high to low transi-
tion is placed on the SCL input. When a valid tra ns itio n
on SCL is re cogni ze d, the de vi ce w ill s w itch into t he Bi-
directio nal Mod e and look f or its control b yte to be sent
by the master. If it detects its control byte, it will stay in
the Bi-directional Mode. Otherw ise, it will rever t to the
Transmit-Only Mode after it sees 128 VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
content s of the mem ory arra y. This de vice req uires that
it be initialized prior to valid data being sent in the
Transmit-Only Mode (Section 2.2). In this mode, data
is t ransmi tted on th e SDA pin in 8-bi t bytes, w ith each
by te followed by a ninth, n ul l bi t (Fig ure 2-1). The clock
source for the Transmit-O nly Mode is provided on the
VCLK pi n, and a d ata bit is output o n the risi ng edge o n
this pin. The eight bits in each byte are transmitted
most significant bit first. Each byte within the memory
array will be output in seque nce. After address 7 Fh in
the memory array is transmitted, the internal address
pointers will wrap around to the first memory location
(00h) and continue. The Bi-directional Mode Clock
(SCL) pin mu st be held high fo r the device to rem ain in
the Transmit-Only Mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK
pin m ust be giv en to the device f or it to pe rf orm inte rnal
sych roniza tion . Dur ing th is per iod, the SDA pin w ill be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit w hich wil l be the mos t signi fican t bit in add ress
00h. (Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
Tvaa Tvaa
Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7
TvlowTvhigh
Tvaa Tvaa
Bit 8 Bit 7High Impedance for 9 clock cycles
Tvpu
12 891011
SCL
SDA
VCLK
Vcc
1999 Microchip Technology Inc. DS21161E-page 5
24LCS21A
3.0 BI-DIRECTIONAL MODE
Before the 24LCS21A can be switched into the Bi-
directional Mode (Figure 3-1), it must enter the transi-
tion mo de , which is done b y app lying a val id high to low
transition on the Bi-directional Mode Clock (SCL). As
soon it enters the transition mode, it looks for a control
byte 1010 000X on the I2C bus, and starts to count
pulses on VCLK. Any high to low transition on the SCL
line will reset the count. If it sees a pulse count of 128
on VCLK whil e the SCL line is idle, it will revert back to
the Transmit-Only Mode, and transmit its contents
starting with the most significant bit in address 00h.
However, if it detects the control byte on the I2C bus,
(Figure 3-2) it will switch to the in the Bi-directional
Mode. Onc e the d ev ice has made the transi tion to the
Bi-di rectio nal mode, t he only way to switch t he device
back to the Transmit-Only Mode is to remove power
from the device. The mode transition process is shown
in detail in Figure 3-3.
Once the device has switched into the Bi-directional
Mode, the VCLK input is disregarded, with the excep-
tion that a logic high level is required to enable write
capabil ity. This mode s upports a two-wi re Bi-directiona l
data transmission protocol (I2C). In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defi ned to be the rece iv er. The bus m ust b e con-
trolled by a master device that generates the Bi-direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LCS21A acts as the sla ve. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated. In the Bi-
directional mode, the 24LCS21A only responds to
commands for device 1010 000X.
FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
FIGURE 3-2: SUCCESSFUL MODE TR ANSI TION TO BI-DIRECTIONAL MODE
TVHZ
SCL
SDA
VCLK
Transmit
Only
MODE Bi-directional Recovery to Transmit-Only Mode
Bit8
(MSB of data in 00h)
VCLK count = 1 2 3 4 127 128
Transition Mode with possibility to return to Transmit-Only Mode Bi-directional
permanently
SCL
SDAVCLK count = 1 2 n 0
VCLK
Transmit
Only Mode
MODE
S1 0 1 0 0000 ACK
n < 128
24LCS21A
DS21161E-page 6 1999 Microchip Technology Inc.
FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
Communication
is idle
Is Vsync
present? No
Send EDID continuously
using Vsync as clock
High to low
transition on
SCL? No
Yes
Yes
Stop sending EDID.
Switch to DDC2 mode.
Display has
transition state
?
optional
Set Vsync counter = 0
Change on
VCLK lines?
SCL, SDA or
No
Yes
High - low
transition on SCL
?
Reset Vsync counter = 0
No
Yes
Valid
received?
DDC2 address
No
No VCLK
cycle?
Yes
Increment VCLK counter
Yes
Switch back to DDC1
mode.
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
address
received?
Yes
Receive DDC2B
command
Respond to DDC2B
command
Is display
Access.busTM
Yes
Valid Access.bus
address? No
Yes
See Access.bu s
specification to determine
correct procedure.
Yes
No
Yes
No
No
No
The 24LCS21A was designed to
Display P o wer-on
or
DDC Circuit Powered
from +5 volts
or start timer
Reset counter or timer
(if appropriate)
Counter=128 or
timer expired?
High to low
transition on
SCL?
No
Yes
comply to the portion of flowchart inside dash box
Note 1: Th e base flowch art is co pyright 1993, 19 94, 199 5 Vi deo Ele ctr oni c St and ard Associat ion (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology, Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A.
capable?
1999 Microchip Technology Inc. DS21161E-page 7
24LCS21A
3.1 Bi-directional Mode Bus
Characteristics
The follow ing bus protocol has been defined:
• Data transfer may be initiated only when the bus
is no t busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in th e d ata line while the clock li ne is H IG H will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Fi gure 3-4).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
cloc k (SCL) is HIGH d etermines a START condi tion. All
commands must be preceded by a START condition.
3.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (S CL) i s HI GH de termines a STOP con d iti on . A ll
operations must be ended with a STOP condition.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the cl oc k si gna l. Ther e is on e clo c k pu lse p er
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight w ill be store d when doing a write operati on. When
an overwri te doe s occur it will r eplac e data in a first in
first out fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way tha t the SDA lin e is sta ble LOW du ring t he HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note: Once s witched into Bi-directional Mode, the
24LCS21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LCS21A into the
Transmit-only mode.
Note: The 24LCS21A does not generate any
acknowledge bits if an internal
programming cycle is in progress.
FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (A)(C)
START
CONDITION ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
24LCS21A
DS21161E-page 8 1999 Microchip Technology Inc.
FIGURE 3-5: BUS TIMING START/STOP
FIGURE 3-6: BUS TIMING DATA
SCL
SDA
START STOP
VHYS TSU:STO
THD:STA
TSU:STA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TR
3.1.6 SLAVE ADDR ESS
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21A.
The eigh th bit of sla v e address d etermines whether th e
master device wants to read or write to the 24LCS21A
(Figure 3-7).
The 24LCS21A monitors the bus for its corresponding
slave address continuously. It generates an
acknowled ge b it i f the s lave addre ss was tr ue an d it is
not in a programming mode.
FIGURE 3-7: CONTROL BYTE
ALLOCATION
Operation Slave Address R/W
Read 1010000 1
Write 1010000 0
R/W A
1010000
READ/WRITE
START
SLAVE ADDRESS
1999 Microchip Technology Inc. DS21161E-page 9
24LCS21A
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the slave
address (f our bits), three z ero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiv er that a byte with a word address will f ollow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the add ress pointer of the 24LCS21A. After rec eiv-
ing another acknowledge signal from the 24LCS21A
the maste r dev ice will tr ansmit the data word to be writ-
ten into the addressed memory location. The
24LCS21A acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LCS21A will not
generate acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
dur ing command and dat a transfer in order t o program
the device. This applies to both byte write and page
write operation. Note, howe ver, that the VCLK is ignored
during the self-timed program operation. Changing
VCLK from high to low during the self-timed program
operation will not halt programming of the device.
4.2 Page Write
The write control byte, word address and the first data
by te a r e t ra ns mi tted to the 24L CS21 A in the same w ay
as in a byte write. But instead of generating a stop
conditi on the m aste r trans mits up t o eigh t data b yt es to
the 24LCS21A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the recei pt of ea ch wor d, the th ree lo w er order a ddres s
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constan t. If the master s ho uld transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 5-2).
It is required that VCLK be held at a logic high level
dur ing command and dat a transfer in order to pr ogram
the device. This applies to both byte write and page
write operation. Note, howe ver, that the VCLK is ignored
during the self-timed program operation. Changing
VCLK from high to low during the self-timed program
operation will not halt progra m m i ng of the d evice.
Note: Page wr i te operatio ns are limit ed to wr i ting
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses t hat are in teger multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundar y, the result is th at the da ta wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the ne xt page as
might be expected. It is therefore neces-
sar y for the app licat ion sof tware to pr event
page write operations that would attempt to
cross a page boundary.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE WORD
ADDRESS DATA S
T
O
P
S
T
A
R
T
A
C
K
SP
A
C
K
A
C
K
VCLK
SCL
SDA
IN
VCLK
THD:STA TSU:STO
TVHST TSPVL
24LCS21A
DS21161E-page 10 1999 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to deter mine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write
comma nd has been iss ued fro m the ma ste r, the de v ice
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a start condition f ollowed by the control byte f or
a write command (R/W = 0). If the device is still busy
with th e write cycle , then no A C K will be returned. If th e
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Did Device
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
FIGURE 5-2: PAGE WRITE
SDA LINE
CONTROL
BYTE WORD
ADDRESS
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1 DATA n + 7
DATA (n)
P
S
VCLK
BUS ACTIVITY
MASTER
BUS ACTIVITY
1999 Microchip Technology Inc. DS21161E-page 11
24LCS21A
6.0 WRITE PROTECTION
When us ing the 24LCS21A in the Bi-directional Mode,
the VCLK pin can be used as a write prote ct control pin.
Setting VCLK high allows normal write operations,
while set ting VC LK low pre vents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LCS21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmi t-Only Mode.
Addi tion ally, Pin t hree perfor ms a flexible w ri te pro tect
function. The 24LCS21A contains a write-protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP pin. Until this fuse is set, the
24LCS21A is always write enabled (if VCLK = 1). After
the fuse is set, the write capability of the 24LCS21A is
deter mined by bot h VCLK and WP pins (Table 6- 1).
TABLE 6-1: WRITE PROTECT TRUTH
TABLE
VCLK WP Address
7Fh Written
Mode
for
00h - 7Fh
0 X X Read Only
1 X No R/W
11/open X R/W
1 0 Yes Read Only
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
sla ve addr ess is set to one . There are th ree basic type s
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LCS21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
wou ld ac ces s data from address n + 1. Upon rec ei pt of
the slave address with R/W bit set to one, the
24LCS21A issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the tr ansf e r but does gene rate a s top con dition and the
24LCS21A discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS READ
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perfor m
this type of read operation, first the word address must
be set. This is don e by sending the word address t o the
24LCS21A as part of a wr ite operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
oper ation , b ut not bef ore the i nternal addres s pointe r is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24 LCS 21A w ill th en
issue an acknowledge and transmits the 8-bit data
word . The ma st er w ill no t acknowled ge the transf e r but
does generate a stop condition and the 24LCS21A
discontinues transmission (Figure 7-2).
CONTROL
A
C
K
SP
BYTE DATA n
BUS ACTIVITY
SDA LINE
BUS ACTIVITY A
C
K
N
O
MASTER
10100001
S
T
O
P
S
T
A
R
T
24LCS21A
DS21161E-page 12 1999 Microchip Technology Inc.
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE WORD
ADDRESS DATA n
A
C
K
S
T
A
R
T
N
O
S
T
A
RCONTROL
BYTE
A
C
K
A
C
K
SS
T
P
S
T
O
P
10100000 00000111
A
C
K
A
C
K
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE DATA n DATA n+1 DATA n+2 DATA n+X
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read e x cept th at after the 24LCS 21A tra nsmit s
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LCS21A to transmit the next sequentially
addressed 8-bit word (Figure 7 -3).
To pro vide sequent ial reads the 24 LCS21A contai ns an
internal ad dress pointer which is inc remented b y one at
the com ple tio n of each operat ion . This address poin ter
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LCS21A employs a VCC th reshold de tector ci r-
cuit which disables the inter nal eras e/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt trigger
and filte r circuits which suppress noise spikes t o assure
proper device operation even on a noisy bus.
8.0 PIN DESCRIPTIONS
8.1 SDA
This pi n is used t o trans fer add resses and data into an d
out of the device, when the device is in the Bi-direc-
tional Mode. In the Transmit-Only Mode, which only
allows data to be read from the device, data is also
transferred on the SDA pin. This pin is an open drain
terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10 KΩ for 100 kHz, 1 KΩ for
400 kHz).
For normal data transfer in the Bi-directional Mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for indicating
the START and STOP conditions.
8.2 SCL
This pin is the clock input for the Bi-directional Mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the de vice fro m the Transmi t-Only Mode to the Bi-direc-
tional Mode. It must remain high for the chip to continue
operation in the Transmit-Only Mode.
1999 Microchip Technology Inc. DS21161E-page 13
24LCS21A
8.3 VCLK
This pin is the clock input for the Transmit-Only Mode
(DDC1). In the Transmit-Only Mode, each bit is clocke d
out on t he rising edge of this sign al. In the Bi-dire ctional
Mode, a high logic lev el is required on this pin to enable
write capability.
8.4 WP
This pin is used for flexible write protection of the
24LCS21A. When the last memory location (7Fh) is
written with any data, this pin is enabled and
determines the write capability of the 24LCS21A
(Table 6-1).
The WP pin has an internal pull up resistor which will
allow write capability (assuming VCLK = 1) at all times
if this pin is f loated.
24LCS21A
DS21161E-page 14 1999 Microchip Technology Inc.
NOTES:
24LCS21A
24LCS21A Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
Sales and Support
Data Sheets
Products suppor ted by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determ ine if an errata sheet exists fo r a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U. S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature Blank = 0°C to +70°C
Range: I=-40°C to +85°C
Device: 24LCS21A Dual Mode I2C Serial EEPR OM
24LCS21AT Dual Mode I2C Serial EEPROM (Tape and Reel)
24LCS21A -/P
1999 Microchip Technology Inc. DS21161E-page 15
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorpora ted in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter , please contact the local sales office nearest to you.
2002 Microchip Technology Inc.
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