3.0 kV RMS 5-Channel Digital Isolators
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition: 3000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
CQC certification per GB4943.1-2011
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, narrow-body SOIC package
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM150N/ADuM151N/ADuM152N1 are 5-channel
digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed, complementary metal-oxide
semiconductor (CMOS) and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as
optocoupler devices and other integrated couplers. The
maximum propagation delay is 13 ns with a pulse width
distortion of less than 4.5 ns at 5 V operation. Channel to
channel matching of propagation delay is tight at 4.0 ns
maximum.
The ADuM150N/ADuM151N/ADuM152N data channels are
independent and are available in a variety of configurations
with a withstand voltage rating of 3.0 kV rms (see the Ordering
Guide). The devices operate with the supply voltage on either
side ranging from 1.7 V to 5.5 V, providing compatibility with
lower voltage systems as well as enabling voltage translation
functionality across the isolation barrier.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADuM150N Functional Block Diagram
Figure 2. ADuM151N Functional Block Diagram
Figure 3. ADuM152N Functional Block Diagram
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available by which the outputs transition to a predeter-
mined state when the input power supply is not applied.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
ID
V
IE
NIC
V
OA
V
OB
V
OC
V
OD
V
OE
NIC
GND
1
V
DD2
ADuM150N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14531-001
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
ID
V
OE
NIC
V
OA
V
OB
V
OC
V
OD
V
IE
NIC
GND
1
V
DD2
ADuM151N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DECODE ENCODE
14531-002
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
OD
V
OE
NIC
V
OA
V
OB
V
OC
V
ID
V
IE
NIC
GND
1
V
DD2
ADuM152N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DECODE ENCODE
DECODE ENCODE
14531-003
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—2.5 V Operation ............................ 7
Electrical Characteristics—1.8 V Operation ............................ 9
Insulation and Safety Related Specifications .......................... 11
Package Characteristics ............................................................. 11
Regulatory Information ............................................................. 11
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 12
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 19
Applications Information .............................................................. 20
PCB Layout ................................................................................. 20
Propagation Delay Related Parameters ................................... 20
Jitter Measurement ..................................................................... 20
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/2016—Revision 0: Initial Version
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 3 of 22
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, an d − 40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
ns
Within pulse width distortion (PWD) limit
Data Rate
1
150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
4.8 7.2 13 ns 50% input to 50% output
Pulse Width Distortion PWD 0.5 4.5 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.1 ns Between any two units at the
same temperature, voltage, and load
Channel Matching
Codirectional t
PSKCD
0.5 4.0 ns
Opposing Direction t
PSKOD
0.5 4.5 ns
Jitter 490 ps p-p See the Jitter Measurement section
70
ps rms
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 ×
V
DDx
V
Logic Low VIL 0.3 ×
V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
2 = −20 µA, V
Ix
= V
IxH
3
VDDx − 0.4 VDDx −
0.2
V IOx
2
= −4 mA, VIx = VIxH
3
Logic Low V
OL
0.0 0.1 V I
Ox2
= 20 µA, V
Ix
= V
IxL4
0.2 0.4 V I
Ox
2 = 4 mA, V
Ix
= V
IxL
4
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
Quiescent Supply Current
ADuM150N
I
DD1 (Q)
2.54 3.70 mA V
I
5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.34 4.56 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
16.8 27.5 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
3.57 4.90 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM151N
I
DD1 (Q)
2.79 4.09 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.20 4.22 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
14.2 23 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
7.08 11.1 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM152N
I
DD1 (Q)
2.91 4.11 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.95 4.15 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
11.1 19.5 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
10.5 16.7 mA V
I
5 = 1 (N0), 0 (N1)6
Dynamic Supply Current
Inputs switching, 50% duty cycle
Dynamic Input
IDDI (D)
0.01
mA/Mbps
Dynamic Output I
DDO (D)
0.02 mA/Mbps
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 4 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout UVLO
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
V
DDx
Hysteresis V
DDxUVH
0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, or E.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM150N
Supply Current Side 1 I
9.63 14.6 10.9 17.1 16.0 24.0 mA
Supply Current Side 2 I
3.61 5.61 5.36 8.50 11.1 19.0 mA
ADuM151N
Supply Current Side 1 I
8.51 13.7 9.85 16.1 15.0 23.3 mA
Supply Current Side 2 I
5.28 8.95 6.89 11.5 12.3 20.0 mA
ADuM152N
Supply Current Side 1 I
7.08 11.6 8.56 13.9 13.7 20.4 mA
Supply Current Side 2 I
6.83 10.5 8.35 12.8 13.4 20.6 mA
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 5 of 22
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
4.8 6.8 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 4.5 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional t
PSKCD
0.7 4.0 ns
Opposing Direction t
PSKOD
0.7 4.5 ns
Jitter 580 ps p-p See the Jitter Measurement section
120 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox2
= −20 µA, V
Ix
= V
IxH3
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox2
= −2 mA, V
Ix
= V
IxH3
Logic Low V
OL
0.0 0.1 V I
Ox
2 = 20 µA, V
Ix
= V
IxL
4
0.2 0.4 V I
Ox
2 = 2 mA, V
Ix
= V
IxL
4
Input Current per Channel
II
−10
+0.01
+10
µA
0 V ≤ VIx ≤ VDDx
Quiescent Supply Current
ADuM150N
I
DD1 (Q)
2.36 3.52 mA V
I
5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.20 4.42 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
16.5 27.2 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
3.43 4.76 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM151N
I
DD1 (Q)
2.61 3.91 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.05 4.07 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
14.0 22.8 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
6.91 10.9 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM152N
I
DD1 (Q)
2.74 3.94 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.79 3.99 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
10.9 19.3 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
10.3 16.5 mA V
I
5 = 1 (N0), 0 (N1)6
Dynamic Supply Current Inputs switching, 50% duty cycle
Dynamic Input I
DDI (D)
0.01 mA/Mbps
Dynamic Output I
DDO (D)
0.01 mA/Mbps
Undervoltage Lockout UVLO
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
V
DDx
Hysteresis V
DDxUVH
0.1 V
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 6 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, or E.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM150N
Supply Current Side 1 I
9.36 14.3 10.4 16.6 14.6 22.6 mA
Supply Current Side 2 I
3.45 5.45 5.03 8.23 10.2 18.1 mA
ADuM151N
Supply Current Side 1 I
8.26 13.5 9.41 15.7 13.9 22.2 mA
Supply Current Side 2 I
5.09 8.76 6.55 11.2 11.4 19.1 mA
ADuM152N
Supply Current Side 1
6.84
11.3
8.12
13.5
12.7
19.4
mA
Supply Current Side 2 I
6.60 10.3 7.94 12.4 12.6 19.8 mA
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 7 of 22
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay
tPHL, tPLH
5.0
7.0
14
ns
50% input to 50% output
Pulse Width Distortion PWD 0.7 5.0 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.8 ns Between any two units at the
same temperature, voltage, load
Channel Matching
Codirectional
tPSKCD
0.7
5.0
ns
Opposing Direction t
PSKOD
0.7 5.0 ns
Jitter 800 ps p-p See the Jitter Measurement section
190 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
2
= −20 µA, V
Ix
= V
IxH
3
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox2
= −2 mA, V
Ix
= V
IxH3
Logic Low V
OL
0.0 0.1 V I
Ox2
= 20 µA, V
Ix
= V
IxL4
0.2 0.4 V I
Ox
2 = 2 mA, V
Ix
= V
IxL
4
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
Quiescent Supply Current
ADuM150N
I
DD1 (Q)
2.28 3.44 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.13 4.35 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
16.4 27.1 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
3.34 4.67 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM151N
I
DD1 (Q)
2.52 3.82 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.97 3.99 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
13.9 22.7 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
6.83 10.8 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM152N
I
DD1 (Q)
2.66 3.86 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.71 3.91 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
10.8 19.2 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
10.2 16.4 mA V
I
5 = 1 (N0), 0 (N1)6
Dynamic Supply Current Inputs switching, 50% duty cycle
Dynamic Input
IDDI (D)
0.01
mA/Mbps
Dynamic Output I
DDO (D)
0.01 mA/Mbps
Undervoltage Lockout
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
VDDx Hysteresis
VDDxUVH
0.1
V
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 8 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, or E.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM150N
Supply Current Side 1 I
9.25 14.2 10.2 16.4 14.0 22.0 mA
Supply Current Side 2 I
3.35 5.35 4.58 7.78 8.61 16.5 mA
ADuM151N
Supply Current Side 1 I
8.14 13.4 9.14 15.4 13.1 21.4 mA
Supply Current Side 2 I
4.98 8.65 6.14 10.8 10.1 17.8 mA
ADuM152N
Supply Current Side 1
6.74
11.2
7.80
13.2
11.8
18.5
mA
Supply Current Side 2 I
6.48 10.2 7.56 12.0 11.5 18.7 mA
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 9 of 22
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 5.0 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.0 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional
tPSKCD
0.7
5.0
ns
Opposing Direction t
PSKOD
0.7 5.0 ns
Jitter 470 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
2
= −20 µA, V
Ix
= V
IxH
3
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox2
= −2 mA, V
Ix
= V
IxH3
Logic Low V
OL
0.0 0.1 V I
Ox2
= 20 µA, V
Ix
= V
IxL4
0.2 0.4 V I
Ox
2 = 2 mA, V
Ix
= V
IxL
4
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
Quiescent Supply Current
ADuM150N
I
DD1 (Q)
2.19 3.35 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
3.07 4.29 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
16.3 27.0 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
3.28 4.61 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM151N
I
DD1 (Q)
2.44 3.74 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.91 3.93 mA V
I
5 = 0 (N0), 1 (N1)6
I
DD1 (Q)
13.7 22.5 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
6.75 10.7 mA V
I
5 = 1 (N0), 0 (N1)6
ADuM152N
I
DD1 (Q)
2.58 3.78 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD2 (Q)
2.64 3.84 mA V
I5
= 0 (N0), 1 (N1)
6
I
DD1 (Q)
10.7 19.1 mA V
I
5 = 1 (N0), 0 (N1)6
I
DD2 (Q)
10.1 16.3 mA V
I
5 = 1 (N0), 0 (N1)6
Dynamic Supply Current Inputs switching, 50% duty cycle
Dynamic Input
IDDI (D)
0.01
mA/Mbps
Dynamic Output I
DDO (D)
0.01 mA/Mbps
Undervoltage Lockout UVLO
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
VDDx Hysteresis
VDDxUVH
0.1
V
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 10 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, or E.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 8. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM150N
Supply Current Side 1 I
9.07 14.0 10.0 16.2 13.8 21.8 mA
Supply Current Side 2 I
3.30 5.30 4.55 7.75 8.71 16.4 mA
ADuM151N
Supply Current Side 1 I
7.99 13.3 8.98 15.3 12.8 21.1 mA
Supply Current Side 2
4.89
8.56
6.06
10.7
10.1
17.8
mA
ADuM152N
Supply Current Side 1 I
6.62 11.1 7.68 13.1 11.6 18.3 mA
Supply Current Side 2 I
6.38 10.1 7.45 11.9 11.5 18.7 mA
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 11 of 22
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see http://www.analog.com/icouplersafety.
Table 9.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 4.0 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 4.0 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
4.5
mm min
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 10.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 R
I-O
1013 Ω
Capacitance (Input to Output)1 C
I-O
2.2 pF f = 1 MHz
Input Capacitance2
CI
4.0
pF
IC Junction to Ambient Thermal Resistance θ
JA
75 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 11.
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012,
GB4943.1-2011:
Single Protection, 3000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition, +A1+A2:
Reinforced insulation, VIORM =
565 V peak, V
IOSM
= 6000 V peak
Basic insulation at
770 V rms (1089 V peak)
Double Protection, 3000 V rms
Isolation Voltage
Basic insulation at 400 V rms
(565 V peak)
Basic insulation, VIORM = 565 V peak,
V
IOSM
= 10 kV peak
Reinforced insulation at
385 V rms (545 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
IEC 60601-1 Edition 3.1: basic
insulation (one means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains,
400 V rms secondary (565 V peak)
Reinforced insulation at 300 V rms
mains, 200 V secondary (282 V peak)
File E214100 File 205078 File 2471900-4880-0001 File (pending)
1 In accordance with UL 1577, each ADuM150N/ADuM151N/ADuM152N in the R-16 narrow-body (SOIC_N) package is proof tested by applying an insulation test voltage ≥
3600 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM150N/ADuM151N/ADuM152N in the R-16 narrow-body (SOIC_N) package is proof tested by applying an insulation
test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 12 of 22
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 12.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
IORM
565 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
t
ini
= t
m
= 1 sec, partial discharge < 5 pC
Vpd (m) 1059 V peak
Input to Output Test Voltage, Method A V
pd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
848 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
678 V peak
Highest Allowable Overvoltage V
IOTM
4200 V peak
Surge Isolation Voltage Basic
V
PEAK
= 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
V
IOSM
10,000
V peak
Surge Isolation Voltage Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a
failure (see Figure 4)
Maximum Junction Temperature T
S
150 °C
Total Power Dissipation at 25°C P
S
1.64 W
Insulation Resistance at T
S
R
S
>10
9
Ω
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 13.
Parameter Symbol Rating
Operating Temperature T
A
−40°C to +125°C
Supply Voltages V
DD1
, V
DD2
1.7 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00200150100
50
SAFE LIMITING POWER (W)
AMBI E NT TE M P E RATURE ( °C)
14531-004
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 13 of 22
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 14.
Parameter Rating
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VIE) −0.5 V to VDDI1 + 0.5 V
Output Voltages (VOA, VOB, VOC, VOD,
VOE)
−0.5 V to VDDO2 + 0.5 V
Average Output Current per Pin3
Side 1 Output Current (IO1) −10 mA to +10 mA
Side 2 Output Current (IO2) −10 mA to +10 mA
Common-Mode Transients4 −150 kV/μs to +150 kV/μs
1 VDDI is the input side supply voltage.
2 VDDO is the output side supply voltage.
3 See Figure 4 for the maximum rated current values for various temperatures.
4 Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 15. Maximum Continuous Working Voltage1
Parameter Rating Constraint
AC Voltage
Bipolar Waveform
Basic Insulation 789 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 403 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 909 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 469 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 558 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 285 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Truth Table
Table 16. ADuM150N/ADuM151N/ADuM152N Truth Table (Positive Logic)
VIx Input1, 2 VDDI State2 V
DDO State2
Default Low (N0),
VOx Output1, 2, 3
Default High (N1),
VOx Output1, 2, 3 Test Conditions/Comments
L Powered Powered L L Normal operation
H Powered Powered H H Normal operation
L Unpowered Powered L H Fail-safe output
X4 Powered Unpowered Indeterminate Indeterminate Output unpowered
1 L means low, H means high, and X means don’t care.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, or E). VDDI and VDDO refer to the supply voltages on the input and output sides of the given
channel, respectively.
3 N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models, N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
4 Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 14 of 22
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. ADuM150N Pin Configuration
Table 17. ADuM150N Pin Function Descriptions
Pin No.1 Mnemonic Description
1 V
DD1
Supply Voltage for Isolator Side 1.
2 V
IA
Logic Input A.
3 V
IB
Logic Input B.
4
VIC
Logic Input C.
5 V
ID
Logic Input D.
6 V
IE
Logic Input E.
7 NIC No Internal Connection. Leave this pin floating.
8 GND
1
Ground 1. Ground reference for Isolator Side 1.
9 GND
2
Ground 2. Ground reference for Isolator Side 2.
10 NIC No Internal Connection. Leave this pin floating.
11 V
OE
Logic Output E.
12 V
OD
Logic Output D.
13 V
OC
Logic Output C.
14 V
OB
Logic Output B.
15 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
VDD1
VIA
VIB
VIC
VID
VIE
NIC
VOA
VOB
VOC
VOD
VOE
NIC
GND1
VDD2
GND2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM150N
TOP VIEW
(No t t o Scal e)
14531-005
NOTES
1. NI C = NO I NTERNAL CONNE CTI ON.
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 15 of 22
Figure 6. ADuM151N Pin Configuration
Table 18. ADuM151N Pin Function Descriptions
Pin No.
1
Mnemonic Description
1 V
DD1
Supply Voltage for Isolator Side 1.
2 V
IA
Logic Input A.
3 V
IB
Logic Input B.
4 V
IC
Logic Input C.
5 V
ID
Logic Input D.
6 V
OE
Logic Output E.
7 NIC No Internal Connection. Leave this pin floating.
8 GND
1
Ground 1. Ground reference for Isolator Side 1.
9 GND
2
Ground 2. Ground reference for Isolator Side 2.
10 NIC No Internal Connection. Leave this pin floating.
11 V
IE
Logic Input E.
12
VOD
Logic Output D.
13 V
OC
Logic Output C.
14 V
OB
Logic Output B.
15 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
V
DD1
V
IA
V
IB
V
IC
V
ID
V
OE
NIC
V
OA
V
OB
V
OC
V
OD
V
IE
NIC
GND
1
V
DD2
GND
2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM151N
TOP VIEW
(No t t o Scal e)
14531-006
NOTES
1. NI C = NO I NTERNAL CONNE CTI ON.
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 16 of 22
Figure 7. ADuM152N Pin Configuration
Table 19. ADuM152N Pin Function Descriptions
Pin No.
1
Mnemonic Description
1 V
DD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
3 V
IB
Logic Input B.
4 V
IC
Logic Input C.
5 V
OD
Logic Output D.
6 V
OE
Logic Output E.
7
NIC
No Internal Connection. Leave this pin floating.
8 GND
1
Ground 1. Ground reference for Isolator Side 1.
9 GND
2
Ground 2. Ground reference for Isolator Side 2.
10 NIC No Internal Connection. Leave this pin floating.
11 V
IE
Logic Input E.
12 V
ID
Logic Input D.
13 V
OC
Logic Output C.
14 V
OB
Logic Output B.
15 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
VDD1
VIA
VIB
VIC
VOD
VOE
NIC
VOA
VOB
VOC
VID
VIE
NIC
GND1
VDD2
GND2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM152N
TOP VIEW
(No t t o Scal e)
14531-007
NOTES
1. NI C = NO I NTERNAL CONNE CTI ON.
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 17 of 22
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. ADuM150N IDD1 Supply Current vs. Data Rate at Various Voltages
Figure 9. ADuM150N IDD2 Supply Current vs. Data Rate at Various Voltages
Figure 10. ADuM151N IDD1 Supply Current vs. Data Rate at Various Voltages
Figure 11. ADuM151N IDD2 Supply Current vs. Data Rate at Various Voltages
Figure 12. ADuM152N IDD1 Supply Current vs. Data Rate at Various Voltages
Figure 13. ADuM152N IDD2 Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-008
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-009
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-010
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-011
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-012
25
20
15
10
5
0020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
5V
3.3V
2.5V
1.8V
14531-013
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 18 of 22
Figure 14. Propagation Delay, tPLH vs. Temperature at Various Voltages
Figure 15. Propagation Delay, tPHL vs. Temperature at Various Voltages
14
12
10
8
6
4
2
0
–40 –20 020 40 60 80 120100 140
PROP AGAT IO N DE LAY,
tPLH
(n s)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14531-014
14
12
10
8
6
4
2
0
–40 –20 020 40 60 80 120100 140
PROP AGAT IO N DE LAY,
tPHL
(n s)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14531-015
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 19 of 22
THEORY OF OPERATION
The ADuM150N/ADuM151N/ADuM152N use a high frequency
carrier to transmit data across the isolation barrier using iCoupler
chip scale transformer coils separated by layers of polyimide
isolation. Using an on/off keying (OOK) technique and the
differential architecture shown in Figure 16 and Figure 17, the
ADuM150N/ADuM151N/ADuM152N have very low propaga-
tion delay and high speed. Internal regulators and input/output
design techniques allow logic and supply voltages over a wide
range from 1.7 V to 5.5 V, offering voltage translation of 1.8 V,
2.5 V, 3.3 V, and 5 V logic. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques.
Figure 16 shows the waveforms for models of the ADuM150N0/
ADuM151N0/ADuM152N0 that have the condition of the fail-
safe output state equal to low, where the carrier waveform is off
when the input state is low. If the input side is off or not operating,
the fail-safe output state of low sets the output to low. For the
ADuM150N1/ADuM151N1/ADuM152N1 that have a fail-safe
output state of high, Figure 17 illustrates the conditions where the
carrier waveform is off when the input state is high. When the
input side is off or not operating, the fail-safe output state of
high sets the output to high. See the Ordering Guide for the
model numbers that have the fail-safe output state of low or the
fail-safe output state of high.
Figure 16. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
Figure 17. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14531-016
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14531-017
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 20 of 22
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM150N/ADuM151N/ADuM152N digital isolators
require no external interface circuitry for the logic interfaces. Power
supply bypassing is strongly recommended at the input and
output supply pins (see Figure 18). Bypass capacitors are connected
between Pin 1 and Pin 8 for VDD1 and between Pin 9 and Pin 16 for
VDD2. The recommended bypass capacitor value is between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm.
Figure 18. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
Figure 19. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM150N/
ADuM151N/ADuM152N component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM150N/ADuM151N/
ADuM152N components operating under the same conditions.
JITTER MEASUREMENT
Figure 20 shows the eye diagram for the ADuM150N/
ADuM151N/ADuM152N. The measurement was taken using
an Agilent 81110A pulse pattern generator at 150 Mbps with
pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V
supplies. Jitter was measured with the Tektronix Model 5104B
oscilloscope, 1 GHz, 10 GSPS with the DPOJET jitter and eye dia-
gram analysis tools. The result shows a typical measurement on
the ADuM150N/ADuM151N/ADuM152N with 490 ps p-p jitter.
Figure 20. ADuM150N/ADuM151N/ADuM152N Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking,
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM150N/ADuM151N/ADuM152N
isolators are presented in Table 9.
V
DD1
V
IA
V
IB
V
IC
V
ID
/V
OD
V
IE
/V
OE
NIC
GND
1
V
DD2
V
OA
V
OB
V
OC
V
ID
/V
OD
V
IE
/V
OE
NIC
GND
2
14531-018
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
14531-019
105
0
1
2
3
4
VOLTAGE (V)
5
0
TIME (ns)
–5–10
14531-020
Data Sheet ADuM150N/ADuM151N/ADuM152N
Rev. 0 | Page 21 of 22
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Testing and modeling have shown that the primary driver of long-
term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the
polyimide materials used in these products, the ac rms voltage
determines the product lifetime.
22
DCRMS
ACRMS
V
V
V+
=
(1)
or
22
DCRMSRMSAC
VVV −=
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 21 and
the following equations.
Figure 21. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
2
2
DCRMS
ACRMS
V
V
V+
=
22
400240 +=
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
DCRMSRMS
AC VV
V−=
22
400
466 −
=
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
14531-021
ADuM150N/ADuM151N/ADuM152N Data Sheet
Rev. 0 | Page 22 of 22
OUTLINE DIMENSIONS
Figure 22. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating
(kV rms)
Fail-Safe
Output
State Package Description
Package
Option
ADuM150N1BRZ
−40°C to +125°C
5
0
3.0
High
16-Lead SOIC_N
R-16
ADuM150N1BRZ-RL7 −40°C to +125°C 5 0 3.0 High 16-Lead SOIC_N, 7” Reel R-16
ADuM150N0BRZ −40°C to +125°C 5 0 3.0 Low 16-Lead SOIC_N R-16
ADuM150N0BRZ-RL7 −40°C to +125°C 5 0 3.0 Low 16-Lead SOIC_N, 7” Reel R-16
ADuM151N1BRZ −40°C to +125°C 4 1 3.0 High 16-Lead SOIC_N R-16
ADuM151N1BRZ-RL7 −40°C to +125°C 4 1 3.0 High 16-Lead SOIC_N, 7” Reel R-16
ADuM151N0BRZ −40°C to +125°C 4 1 3.0 Low 16-Lead SOIC_N R-16
ADuM151N0BRZ-RL7 −40°C to +125°C 4 1 3.0 Low 16-Lead SOIC_N, 7” Reel R-16
ADuM152N1BRZ −40°C to +125°C 3 2 3.0 High 16-Lead SOIC_N R-16
ADuM152N1BRZ-RL7 −40°C to +125°C 3 2 3.0 High 16-Lead SOIC_N, 7” Reel R-16
ADuM152N0BRZ −40°C to +125°C 3 2 3.0 Low 16-Lead SOIC_N R-16
ADuM152N0BRZ-RL7 −40°C to +125°C 3 2 3.0 Low 16-Lead SOIC_N, 7” Reel R-16
1 Z = RoHS Compliant Part.
CONTROLLING DIMENSIONSARE I N M ILLI M E TERS; INCH DI M E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF ERE NCE ON LY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDE C S TANDARDS MS-012-AC
10.00 ( 0.3937)
9.80 ( 0.3858)
16 9
8
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14531-0-8/16(0)