LM5068
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SNVS254C –JANUARY 2004–REVISED MARCH 2013
LM5068 Negative Voltage Hot Swap Controller
Check for Samples: LM5068
1FEATURES DESCRIPTION
The LM5068 hot-swap controller provides intelligent
2• Safe Module Insertion and Removal from Live control of power supply connections during the
Backplanes insertion and removal of circuit cards powered by live
• In-Rush Current Limiting for Safe Board system backplanes.
Insertion into Live Backplanes The LM5068 provides both in-rush current control and
• Fast Response to Over-Current Fault short-circuit protection functions, and limits power
Conditions with Active Current Limiting supply transients in the backplane caused by the
• -10V to -90V Input Range insertion of additional circuit cards. The LM5068
controls the external N-Channel MOSFET to provide
• Programmable Under-Voltage/Over-Voltage programmable load current limiting and circuit
Shutdown Protection with Adjustable breaker functions using a single external current
Hysteresis sense resistor. The LM5068 issues a power good
• Programmable Multi-Function Timer for Board (PWRGD) signal at the conclusion of a successful
Insertion De-Bounce Delay power-on sequence. Input over-voltage or under -
voltage fault conditions will cancel the PWRGD
• Fault Timer Avoids Nuisance Trips Caused by indication.
Short Duration Load Transients
• Active Gate Clamping During Initial Power The LM5068-1 and -2 indicate power-good as an
open-drain active HIGH PWRGD state. The LM5068-
Application 3 and -4 indicate power-good as an open-drain active
• Available in both Latched Fault and Automatic LOW PWRGD state. The LM5068-1 and -3 latch off
Re-Try Versions after a fault condition is detected while the LM5068-2
• Available with either Active HIGH or Active and -4 continuously re-try at intervals set by a
LOW Power Good Flag programmable timer.
The LM5068 is available in a VSSOP-8 package.
APPLICATIONS
• - 48V Power Modules
• Central Office Switching
• Distributed Power Systems
• Electronic Circuit Breaker
• PBX Systems
• Negative Power Supply Control
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
2
1
3
45
6
7
8
PWRGD
OV
UV
VEE
TIMER
VDD
SENSE
LM5068
GATE
VDD (GND)
VEE (-48V)
CL
100 PF
VDD
VEE SENSETIMER
UV
GATE
OV
PWRGD
Cc
22 nF
CT
0.22 PF
R3
4.5 k:
1%
R2
5.5 k:
1%
R1
100 k:
1%
Rs
12 m:
LOAD
LM5068
Q1
SUB85N10-10
+
+
ENABLE
+
RF
499:
CF
0.1 PF
+
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
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Typical Application
Figure 1. Negative Power Supply Control
Connection Diagram
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PIN DESCRIPTION
PIN NAME DESCRIPTION APPLICATION INFORMATION
1 PWRGD Open Drain Power Good indicator Following a successful power-up sequence the PWRGD
signal will be active. The LM5068-1 and -2 are configured
for an active power-good state as HIGH, while the
LM5068-3 and –4 are configured for an active power-good
state as LOW.
2 OV Line Over-Voltage Shutdown An external resistor divider from the power source sets the
over-voltage shutdown level. Hysteresis is generated by an
internal current source which sources 20 µA into the
external divider when the OV pin exceeds 2.5V.
3 UV Line Under-Voltage Shutdown An external resistor divider from the power source sets the
under-voltage shutdown level. Hysteresis is set by an
internal current source which sinks 20 µA from the external
divider when the UV pin falls below 2.5V.
4 VEE Negative Supply Voltage Input
5 SENSE Current Sense Input Load current is monitored via an external current sense
resistor (Rs). If the voltage across Rsexceeds 50mV the
fault timer is initiated. Load current is actively limited to
100mV/Rs. If the sense voltage exceeds 200mV due to a
catastrophic fault, the fast gate pull down circuit will reduce
the MOSFET gate voltage and initiate active current
limiting.
6 GATE N-Channel MOSFET Gate Drive Output This output is pulled high by a 60 µA current source to turn
on the MOSFET.
7 TIMER Timer Input An external capacitor connected to this pin sets the initial
start-up delay and the delay to shutdown in the event of an
over-current condition. This pin is also used for the
automatic re-try timing sequence, following fault shutdown
(-2 and –4 versions).
8 VDD Positive Supply Voltage Input
Configuration Table
Part Number Latch Off /Successive Re-try Power Good Polarity Package
LM5068MM-1/MMX-1 Latch Off Active HIGH VSSOP- 8
LM5068MM-2/MMX-2 Auto Re-try Active HIGH
LM5068MM-3/MMX-3 Latch Off Active LOW
LM5068MM-4/MMX-4 Auto Re-try Active LOW
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)(2)
VDD (VDD to VEE) 100V
PWRGD (PWRGD to VEE) 100V
SENSE (SENSE to VEE) 8V
UV/OV (Clamped) (UV/OV to VEE) 8V
All Other Inputs to VEE 16V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -55°C to +150°C
Soldering Information
ESD Rating (3) 2kV
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The ESD rating of Pin 7 is 1.5kV. It is recommended that proper ESD precautions are taken to avoid performance degradation or loss of
functionality.
Operating Ratings
Supply Voltage Range (VDD) 10V to 90V
Junction Temp. Range −40°C to +105°C
Electrical Characteristics
Specifications in standard typeface are for TJ= +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise noted VDD −VEE = 48V.
Symbol Parameter Conditions Min Typ Max Units
VDD Supply
IIN Supply Current 0.82 1.3 mA
ISD Shutdown Current UV/OV = 0V 580 1000 µA
VDD −VEE Operating Supply Range 10 90 V
UV/OV Shutdown
VUVS VDD Under-voltage Shutdown 8.5 V
VUVSH VDD Under-voltage Shutdown 0.6 V
Hysteresis
VUV Under-voltage Comparator 2.45 2.5 2.55 V
Threshold
IUVHCS Under-voltage Hysteresis Current 18 20 22 µA
Source
VOV Over-voltage Comparator 2.45 2.5 2.55 V
Threshold
IOVHCS Over-voltage Hysteresis Current 18 20 22 µA
Sink
tUVCD UV Comparator Delay UV Low to Gate Low 1100 ns
tOVCD OV Comparator Delay OV High to Gate Low 500 ns
Current Limit Voltage
VCB Circuit Breaker Current Limit 40 50 60 mV
Voltage
VAC Analog Current Limit Voltage 80 100 120 mV
VFDC Fast Discharge Current Limit 150 200 250 mV
Voltage (Fast Gate Pull Down
Threshold)
Sense Input
ISENSE Sense Input Current VSENSE = 50mV -30 -15 µA
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Electrical Characteristics (continued)
Specifications in standard typeface are for TJ= +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise noted VDD −VEE = 48V.
Symbol Parameter Conditions Min Typ Max Units
Timer
VTHVT Timer High Voltage Threshold 4 V
VTLVT Timer Low Voltage Threshold 1V
ITIMER Timer On (Initial Cycle, Sourcing) VTIMER = 2V 468µA
Timer Off (Initial Cycle, Sinking) VTIMER = 2V 27 mA
Timer On (Circuit Breaker, VTIMER = 2V 200 240 280 µA
Sourcing)
Timer Off (Cooling Cycle, Sinking) VTIMER = 2V 468µA
Gate Drive
VGSaturation Gate Drive Voltage VDD- VEE = 48V 910.6 12 V
VDD- VEE = 10V 7.8 V
VGLT Gate Low Threshold Before Gate ramp-up 0.5 V
IGATE Gate Pin Current (Sourcing) VSENSE = 0V 40 60 80 µA
Gate Pin Current (Sinking) VSENSE = 150mV 2.7 mA
VGATE = 3V
Gate Pin Current (Sinking) VSENSE = 300mV 300 mA
VGATE = 1V
PWRGD
VPGLV PWRGD Low Voltage ISINK = 1mA 0.2 0.6 V
IPGLC PWRGD High Leakage Current VPWRGD = 90V 1 µA
VPGV GATE Voltage at onset of PWRGD 8 V
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SERIES
REGULATOR
OV HYSTERESIS CS
2.5V
2.5V
UV HYSTERESIS CS
1V
4V
VREG
VEE
VREG
60PA
UV/OV
or
FAULT VEE
200mV
100mV
50mV
SENSE
VEE
PWRGD / PWRGD
6PA 240PA
6PA
20PA
20PA
0.5V
GATE
TIMER
UV
OV
CONTROL
LOGIC
200Ps
SOFTSTART
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
VDD
VEE
VREG
VEE
VEE
VEE VEE
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
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Block Diagram
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-40 -25 0 25 50 75 105
TEMPERATURE (oC)
2.46
2.47
2.48
2.49
2.50
2.51
2.52
VUV(V) / VOV(V)
VUV
VOV
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
18.5
19
19.5
20
20.5
21
21.5
IUVHCS (PA)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
8.2
8.25
8.3
8.35
8.4
8.45
8.5
8.55
8.6
VUVS (V)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
VUVSH (V)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
0.6
0.7
0.8
0.9
1
1.1
1.2
IIN (mA)
VDD = 90V
VDD = 48V
0.001
0.101
0.201
0.301
0.401
0.501
0.601
0.701
0.801
0 2 4 6 8 10 12 14 16 18 20 22
VDD (V)
IIN (mA)
-40oC
-25oC125oC
LM5068
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Typical Performance Characteristics
IIN IIN
vs vs
Temperature VDD
Figure 2. Figure 3.
VDD Under-Voltage Shutdown (VUVS) VDD Under-Voltage Shutdown Hysteresis (VUVSH)
vs vs
Temperature Temperature
Figure 4. Figure 5.
Under-Voltage Comparator Threshold (VUV) and Over- Under-Voltage Comparator Threshold Hysteresis Current
Voltage Comparator Threshold (VOV) Source (IUVHCS)
vs vs
Temperature Temperature
Figure 6. Figure 7.
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-40 -25 0 25 50 75 105
TEMPERATURE (oC)
185
190
195
200
205
210
215
VFDC (mV)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
3.7
3.8
3.9
4.0
4.1
4.2
4.3
VTHVT (V)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
47
49
51
53
55
VCB (mV)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
94
96
98
100
102
104
106
VAC (mV)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
18.5
19
19.5
20
20.5
21
21.5
IOVHCS (PA)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
200
400
600
800
1000
1200
1400
tUVCD (ns) / tOVCD(ns)
tUVCD
tOVCD
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Over-Voltage Comparator Threshold Hysteresis Current UV Comparator Delay (tUVCD) and OV Comparator Delay
Sink (IOVHCS) (tOVCD)
vs vs
Temperature Temperature
Figure 8. Figure 9.
Circuit Breaker Current Limit Voltage (VCB) Analog Current Limit Voltage (VAC)
vs vs
Temperature Temperature
Figure 10. Figure 11.
Fast Discharge Current Limit Voltage (VFDC) Timer High Voltage Threshold (VTHVT)
vs vs
Temperature Temperature
Figure 12. Figure 13.
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-40 -25 0 25 50 75 105
TEMPERATURE (oC)
9
9.5
10
10.5
11
11.5
12
VG (V)
VDD - VEE = 48V
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
VG (V)
VDD - VEE = 10V
7.6
7.65
7.7
7.75
7.8
7.85
7.9
7.95
8
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
200
210
220
230
240
250
260
ITIMER (PA)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
4.5
5
5.5
6
6.5
7
7.5
ITIMER (PA)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
0.96
1.0
1.04
1.08
1.12
1.16
1.2
VTLVT (V)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
4.5
5.0
5.5
6.0
6.5
7.0
7.5
ITIMER (PA)
LM5068
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SNVS254C –JANUARY 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Timer Low Voltage Threshold (VTLVT) Timer On (Initial Cycle, Sourcing)
vs vs
Temperature Temperature
Figure 14. Figure 15.
Timer On (Circuit Breaker, Sourcing) Timer Off (Cooling Cycle, Sinking)
vs vs
Temperature Temperature
Figure 16. Figure 17.
Saturation Gate Drive Voltage (VG) Saturation Gate Drive Voltage (VG)
vs vs
Temperature (48V) Temperature
Figure 18. Figure 19.
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-40 -25 0 25 50 75 105
TEMPERATURE (oC)
7.7
7.75
7.8
7.85
7.9
7.95
8.0
8.05
8.1
VPGV (V)
-40 -25 0 25 50 75 105
TEMPERATURE (oC)
45
50
55
60
65
70
75
IGATE (PA)
-40 25 0 25 50 75 105
TEMPERATURE (oC)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
VPGLV (V)
ISINK = 1mA
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Gate Pin Current (Sourcing) (IGATE) PWRGD Low Voltage (VPGLV)
vs vs
Temperature Temperature
Figure 20. Figure 21.
Gate Voltage at onset of PWRGD (VPGV)
vs
Temperature
Figure 22.
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CL
VDD
VEE SENSE
TIMER
UV
GATE
OV
PWRGD
CC
CT
R3
R2
R1
RS
LM5068
Q1
VDD
(GND)
VEE
(-48V)
+
+
+
+CF
RF
LM5068
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SNVS254C –JANUARY 2004–REVISED MARCH 2013
FUNCTION DESCRIPTION
The LM5068 is designed to facilitate the insertion and removal of circuit cards into live backplanes in a controlled
manner. Because the supply bypass capacitors on the circuit card can draw large transient currents, it is critical
to control the supply current during insertion to limit system power glitches and connector damage. Controlling in-
rush current prevents other boards in the system from resetting during board insertion. Load short-circuit
protection is accomplished by active current limiting of the load current. The topology of the LM5068 is illustrated
in the simplified application circuit shown in Figure 23.
Figure 23. LM5068 Topology
Start-Up Operation
The LM5068 resides on a removable circuit card. Power is applied to the load or power conversion circuitry
through an external N-Channel MOSFET switch and current sense resistor.
When power is initially applied to the card, the gate of the external MOSFET is held low. When certain interlock
conditions are met, a turn-on sequence begins and an internal 60 µA current source charges the gate of the
MOSFET. To initiate the start-up sequence, all of the following interlock conditions must be satisfied:
• The input voltage VDD - VEE exceeds 9V(VUVS)
• The voltage at UV is above 2.5V (VUV)
• The voltage at OV falls below 2.5V (VOV)
• The voltage on the Timer capacitor (CT) is less than 1V (VTLVT)
• The GATE pin is below 0.5V (VGLT)
When all of the interlock conditions are met, a 6 µA TIMER current source is enabled to charge the timer
capacitor CT. During this initial timer sequence the GATE output is held low. When the CTcapacitor successfully
charges up to 4V, the TIMER circuit resets the timer capacitor to 1V and activates a 60 µA current source (IGATE)
into the MOSFET gate.
Figure 24. Hot Swap Controller
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Over and Under-Voltage Lockout
The line Under-voltage lockout (UVLO) circuitry of the LM5068 monitors VDD for under-voltage conditions, where
VUVS is the negative going threshold and the hysteresis is VUVSH (see Electrical Characteristics). A VDD - VEE
voltage less than 8.5V (VUVS) keeps the controller in a disabled mode. Raising the VDD voltage above 9.1V (VUVS
+ VUVSH) releases the VDD UVLO and enables the controller.
In addition to the internal UVLO circuit, the UV and OV comparators monitor the input line voltage through an
external resistor divider. Programmable UV and OV comparator hysteresis is implemented with switched 20µA
current sources that raise or lower the OV and UV pins when the comparators reach their threshold. Either UV or
OV fault conditions will switch the GATE pin low and disconnect the power to the load. To restart the GATE pin,
the supply voltage must return to a level which is greater than the UV fault and less than the OV fault threshold
and all of the interlock conditions (with the exception of the TIMER) must be met.
Removal of the circuit card from the backplane initiates an under-voltage condition. The series MOSFET is then
disabled to disconnect the source of power to the load. The under-voltage threshold and hysteresis are
programmed by the external resistor divider connected to the UV pin.
Timer
The value of the CTcapacitor sets the duration of the LM5068’s timer delay and filter functions. There are four
charging and discharging modes:
1. 6µA slow charge for initial timing delay and post-fault re-try timer (LM5068-2 and -4)
2. 240µA fast charge for circuit breaker delay.
3. 6µA slow discharge for circuit breaker "cool-off".
4. Low impedance switch to reset capacitor after initial timing delay, input under-voltage lockout, and during
over-voltage and under-voltage initial timing.
Current Control
The LM5068 has three current sense thresholds which protect the backplane supply and circuit card from
overload conditions. The voltage drop across the sense resistor (RS) is monitored at the SENSE pin. The over-
current protection functions are determined through the following three distinct thresholds at the SENSE pin:
1. Circuit Breaker (CB) threshold (typically 50mV)
2. Analog Current Limit (ACL) loop threshold (typically 100mV)
3. Fast Discharge Current (FDC) threshold (typically 200mV)
When the voltage drop across RSexceeds 50mV the Circuit Breaker comparator indicates an over-load
condition. The TIMER sources 240µA into CTwhen SENSE exceeds 50mV and sinks 6µA from CTwhen SENSE
falls below 50mV. If the CTcapacitor ramps to a 4V threshold, a fault condition is declared and the gate of the
MOSFET is forced low, disconnecting the power to the load.
Active Current Limiting (ACL) is activated when the voltage across sense resistor RSreaches 100mV. The
LM5068 controls the gate of the MOSFET and maintains a constant output load current equal to 100mV/ RS. In
the ACL mode the SENSE pin is greater than 50mV and the TIMER charges CTwith 240µA. A fault will be
declared if the LM5068 remains in the ACL mode longer than the circuit breaker timer period.
Fast Discharge Current (FDC) responds to fast rising over-loads such as short circuit faults. During a short circuit
event the fast rising current may overshoot past the ACL threshold due to the finite response time of the ACL
loop. If the SENSE voltage reaches 200mV a fast discharge comparator quickly pulls GATE pin low. The rapid
response of the FDC circuit assures a fast and safe transition to the ACL mode.
The LM5068 circuit breaker action filters low duty cycle over-load conditions to avoid declaring a fault during
short duration load transients. The timer charges capacitor CTwith 240µA when the SENSE voltage is greater
than 50mV. When the SENSE pin voltage falls below 50mV, a 6µA current discharges the TIMER capacitor.
Repetitive over-current faults with duty cycle greater than 2.5% will eventually charge CTand trip the fault timer.
This feature protects the pass MOSFET which has a fast heating and slow cooling characteristic.
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Latch-Off and Auto-Retry
If the fault conditions persist long enough for TIMER to charge CTto 4V, the LM5068 latches off (LM5068-1, -3)
or switches off and initiates the re-try timer (LM5068-2, -4).
At the fault condition, after reaching the 4V, the TIMER pin will continue to ramp-up with 6µA current source until
it reaches the internal regulated voltage, which is equivalent to the saturation GATE drive voltage. The LM5068-1
and LM5068-3 remains off until the controller is reset by either temporarily pulling the UV pin low, pulling the
TIMER pin below 1 volt, or decreasing the input voltage below the internal VDD under-voltage lockout (UVLO)
threshold.
The LM5068-2 and LM5068-4 respond to a fault condition by pulling the GATE and TIMER pins low and then
initiating a timer sequence for automatic re-try. The re-try timer sequence begins with CTcapacitor being charged
slowly to 4V with a 6µA current source and then discharged quickly to 1V with a 30mA discharge current. After 8
charge/discharge cycles the GATE pin is released and charged with a 60µA current source. If the fault condition
persists, the LM5068 will again turn off the MOSFET and another 8-cycle fault timer sequence will begin.
Power Good Flag
The power good flag (PWRGD) is activated when the MOSFET GATE is fully enhanced (>8V) and the voltage
input UV and OV comparators are satisfied. The power good output is a 90V capable open drain N-Channel
MOSFET. The LM5068-1 and LM5068-2 provide an active HIGH power-good state, while the LM5068-3 and
LM5068–4 are configured for an active LOW power-good state. The UV comparator, OV comparator, VDD UVLO,
or a circuit breaker time-out will reset the power good flag.
Internal Soft-Start
An internal soft-start feature ramps the (positive) input of the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200µs. This feature reduces the load current slew rate (di/dt) at start-up.
Design Information
The LM5068 contains an internal regulator enabling the VDD pin to be connected directly to the line voltage from
10 to 90V. A local RC filter (0.1µF ceramic capacitor and 499Ωresistor) connected between VDD and VEE is
recommended to filter supply transients that exceed the 100V Absolute Maximum Rating.
UV and OV Thresholds and Voltage Divider Selection for R1, R2, and R3
Two comparators detect under-voltage and over-voltage conditions at the UV and OV pins. The threshold
voltages (VUV , VOV) of the UV and OV comparators are nominally 2.5V. Hysteresis is accomplished by 20µA
current sources (IUVHCS), into the external resistor divider connected to the UV and OV pins as shown in
Figure 25
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OV turn-on = VOV
R3- IUVHCS (R1 + R2)+ VOV
OV turn-off = R1 + R2 + R3
R3 VOV
UV turn-off = R1 + R2 + R3
R2 + R3 VUV
UV turn-on = R1
R2 + R3VUV + VUV + IUVHCSR1
UV
OV
LM5068
VEE
VDD
OV HYSTERESIS CS
2.5V
2.5V
UV HYSTERESIS CS
20PA
20PA
+
-
+
-
R1
R2
R3
Vsupply
+
CF
RF
LM5068
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Figure 25. UV/OV Setting
Hysteresis is necessary to prevent a possible “chattering” condition when the controller enables or disables the
external MOSFET. The change in line current interacts with the line impedance. This interaction can cause
several rapid on/off cycles on the MOSFET. A hysteresis window larger than the line impedance voltage drop
prevents this condition.
The impedance seen looking into the resistor divider from the UV and OV pin determines the hysteresis level.
UV/OV ON and OFF thresholds are calculated as follow:
(1)
(2)
(3)
(4)
The independent UV and OV pins provide complete flexibility for the user to select the operational voltage range
of the system. However, due to the UV Abs Max rating, the UV and OV thresholds can't be simultaneously set to
extremes in one resistor string. For the wide ranges of input voltages (i.e. UV threshold to12V and OV threshold
to 90V) it is recommended to use two separate voltage dividers to set the UV and OV thresholds independently.
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tRT = 8 x 3V x CT
6PA
tCBT =4V x CT
240PA
tIDT = 4V x CT
6 PA
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
The typical operating ranges of under-voltage and over-voltage thresholds are calculated from the above
equations with known resistors. For example, for resistor values: R1=130KΩ, R2=5.5KΩ, and R3=4.5KΩ, the
computed thresholds are:
• UV turn-on = 37.60V
• UV turn-off = 35.0V
• OV turn-off = 77.78V
• OV turn-on = 75.07V
To maintain the threshold's accuracy, a resistor tolerance of 1% or better is recommended.
Calculation of Normal, Circuit Breaker, and Retry Timing
The CTcapacitor at the TIMER pin controls the timing functions of the LM5068. When the interlock conditions are
met the timer capacitor is charged to 4V in a slow initial delay time period tIDT calculated from:
(5)
If the SENSE pin detects more than 50mV across RS, the TIMER pin charges CTwith 240µA. The Circuit
Breaker timeout period tCBT is calculated from:
(6)
When the LM5068-2 or LM5068-4 is latched, it pulls down the GATE pin and initiates eight, 6µA charging cycles
between 1V and 4V on CT. The total re-try time period tRT is given by:
(7)
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5068
tCBT = 4V x CT4V x 450nF
240PA= 7.5ms
=240PA
ISHORT-CIRCUIT(MAX) = 120mV
40m:
= 3A
100PF x 100V x 40m: x 240PA
4V x 80mV
CT = = 300nF
RS = 40mV
1A = 40m:
CL x VIN(MAX) x RS x 240PA
4V x 80mV
CT =
CL x VIN(MAX)
IINRUSH(MIN)
tCL CHARGE =
ISHORT-CIRCUIT(MAX) = 120mV
RS
80mV
IINRUSH(MIN) = RS
RS =VCB(MIN)
IL(MAX)
40mV
=IL(MAX)
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
Sense Resistor (Rs), Timer Capacitor (CT) and N-Channel Mosfet (Q1) Selection
To select the proper MOSFET, the following safe operating area (SOA) parameters are needed: maximum input
voltage, maximum current and the maximum current conduction time.
First, RSis calculated for the maximum operating load current (IL(MAX)) and the minimum circuit breaker trip point
(VCB(MIN)):
(8)
During the initial charging process, the LM5068 may operate the MOSFET in current limit, forcing VAC(MIN) (80mV)
to VAC(MAX) (120mV) across RS.
The minimum in-rush current and maximum short-circuit limit are calculated from:
(9)
(10)
The value of TIMER capacitor (CT) is calculated in order to prevent CTfrom timing out before the load capacitor
is fully charged using the slowest expected charging rate of the load capacitor. Assuming there is no initial
resistive loading, the time necessary to charge the load capacitor CLis calculated from:
(11)
Applying Equation 9 and Equation 11 to Equation 6 gives the TIMER capacitor value of:
(12)
Finally, the SOA curves of a prospective MOSFET are checked using VIN (MAX), and ISHORT-CIRCUIT (MAX) calculated
from equation Equation 10 and time of the current flow from Equation 6.
Example: For: IL=1A, VDD = 48V, VDD (MAX) = 100V and CL=100µF,
(13)
(14)
To account for tolerances of RS, CL, TIMER current and TIMER threshold voltage, the computed CTvalue should
be increased, for this example 50% was selected, therefore:
CT= 300nF • 1.5 = 450nF
The maximum active current limiting value and duration are:
(15)
(16)
16 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
TIMER
GATE
DRAIN
SENSE
PWRGD
Gate Ramp-up
Initial Timing 1 3 4 5 6
VTHVT
VTLVT
VCB
VAC
6PA
60PA
Normal Mode
Current Limit
27
6PA
VEE PIN SENSE PIN
TO SOURCE
OF MOSFET
TO NEGATIVE
TERMINAL
OF
POWER
SOURCE
SENSE
RESISTOR
HIGH CURRENT PATH
LM5068
UV PIN GATE PIN
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
The N-channel MOSFET selection for use with the LM5068 controller in this example must be capable of
sustaining VDD=100V and I(MAX)=3A for 7.5ms in the worst case fault condition. A device that meets the
established criteria is the Vishay - 5UB85N10-10.
External Sense Resistor
Precise current measurement depends on the accuracy of the sense resistor (RS). For the optimal results, Kelvin
connection and close location of RSto the LM5068 should be considered. Figure 26 demonstrates PCB layout for
the Kelvin sensing.
The RSpower rating should be greater than I2L*R, where ILis the normal maximum operating load.
Figure 26. Sense Resistor Connections
Timing Diagrams
Figure 27. System Power-Up Timing Behavior
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5068
UV
UV LOW
UV HIGH
TIMER
6 PA
GATE
SENSE
PWRGD
DRAIN
VTHVT
VTLVT
VCB
VAC
6 PA
410
INITIAL TIMING
GATE
RAMP-UP
60 PA
5 6 7 8 9 11
123
240 PA
60 PA
UV DROPS BELOW UV HIGH, GATE
AND TIMER ARE PULLED DOWN
UV CLEARS UV LOW, TIMER RAMPS
UP PROVIDED ALL INTERLOCK
CONDITIONS ARE MET
TIMER CLEARS VTLVT. GATE
VOLTAGE RAMPS UP
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
Assuming all of the initial conditions are met, the power-up sequence starts with Timer capacitor (CT) getting
charged. CTis charged with 6µA current source up to VTHVT (4V) then quickly discharge to VTLVT (1V). At time
point (2) the 60µA GATE current source is enabled. The GATE voltage increases until the MOSFET starts
conducting causing the SENSE voltage to increase until Active Current Limiting is activated (3). During the
current limiting period (3-4), CTis charged again, but there is not enough time to reach the 4V threshold before
the load capacitor is fully charged and the SENSE voltage falls below VCB. The GATE continues to fully enhance
the MOSFET and activating the PWRGD when the GATE voltage exceeds 8V (see Figure 27).
Figure 28. Under-Voltage Timing Behavior
UV drops below UV HIGH (time point 1) puts the controller into a disabled mode. Later, UV increases over the
UV LOW threshold (time point 3), which initiates a system power-up sequence.
18 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
SENSE
GATE
TIMER
OV
6 PA
VCB
VAC
PWRGD
VTHVT
VG
OV LOW
OV HIGH
4 5 6 7
1 2 3
60 PA
60 PA
230 PA
OV PIN OVERSHOOTS OV HIGH, GATE IS
PULLED DOWN. PGOOD IS PULLED
LOW AND TIMER IS UNAFFECTED
OV DROPS BELOW OV LOW, GATE STARTS
RAMPING UP AND PGOOD BECOMES HIGH
WHEN GATE VOLTAGE REACHES VG
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
Figure 29. Over-Voltage Timing Behavior
During normal operation, if the OV pin exceeds OV HIGH, as shown at time point 1 in the above diagram, the
TIMER status is unaffected. The GATE and PWRGD ( for LM5068-1 & -2) pins are pulled low and the load is
disconnected. At time point 2, OV recovers and drops below the OV LOW threshold, the GATE start-up cycle
begins. If the load capacitor is completely depleted during OV conditions, a full start-up cycle is initiated.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5068
TIMER
GATE
DRAIN
SENSE
PWRGD
HIGH
Analog
Circuit
Limit
Normal Mode 16
VTHVT
VTLVT
VCB
VAC
6PA
4
Gate
Ramp-up
Normal Mode
32 5
60PA
240PA
TIMER
GATE
DRAIN
SENSE
PGOOD
Circuit Breaker
Limit
Normal Mode 1
VTHVT
VTLVT
VCB
VAC
240PA
2
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
Figure 30. Circuit Breaker Current Limit Fault
The above timing waveform shows the circuit breaker current limit fault behavior. The timer capacitor is charged
with 240µA when the SENSE pin exceeds VCB. If the SENSE pin drops below VCB before the TIMER reaches
VTHVT, the timer capacitor will be discharged with 6µA. In the above figure when TIMER exceeds VTHVT, GATE is
pulled low immediately to disconnect power to the load.
Figure 31. Analog Current Limit Fault
20 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
TIMER
GATE
DRAIN
SENSE
PWRGD
Normal Mode
Fast Gate
Pull Down
1 2
VCB
VAC
VFDC
VTHVT
VTLVT
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
Figure 31 shows analog current limit behavior when the SENSE pin voltage exceeds VAC for a period of time,
which activates the Analog Current Limit but never reaches the fault timer threshold. At that time the GATE is
regulated by the analog current limit amplifier loop. When the SENSE voltage falls below VAC, GATE is allowed
to charge with a 60µA current source. A compensation circuit consisting of a resistor and a capacitor in series,
connected between GATE and VEE stabilizes the current limit loop.
Figure 32. Fast Current Limit Fault
In case of a severe fault (for example sudden short-circuit of the output load) the SENSE pin exceeds the VFDC
threshold and GATE immediately pulls down until the Active Current Limit loop establishes control of the current
in the MOSFET. Careful selection of TIMER capacitor and MOSFET with adequate current and voltage ratings
will prevent damage to MOSFET low impedance faults.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM5068
TIMER
GATE
DRAIN
SENSE
PWRGD
Gate Ramp-up
Normal Mode
Circuit
Breaker
Limit
Circuit Breaker
Timeout Mode
1 2 3 4 5 6 7
VTHVT
VTLVT
VCB
VAC
240PA
6PA30mA
6PA
60PA
Normal Mode
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
Figure 33. Shutdown Cooling Timing Behavior
Figure 33 shows the timer behavior for LM5068-2, -4 during fault re-try time. During normal operation, whenever
the SENSE pin exceeds the 50mV, circuit breaker fault limit, the timer capacitor begins to charge. If the TIMER
pin voltage exceeds 4V, the GATE is pulled down immediately, and LM5068-2, -4 disconnects power to the load.
The TIMER starts the fault re-try cycle by discharging CTwith 30mA to the VTLVT threshold. The TIMER then
charges CTwith 6µA to the VTHVT threshold. After eight charging phases and nine discharging phases, LM5068-
2, -4 initiates an automatic retry start-up cycle.
22 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
+
+
PWRGD
UV
OV
VEE
VDD
TIMER
GATE
SENSE
LM5068
1
2
3
45
6
7
8
+
+
+
+
J1
TP8
UV/OV R1
0:
R2
100k:
R3
4.02k:
R4
3.40k:
R7
50m::
R6
0:
R5
100k:
C1
NOT USED
C3
22nF
C2
NOT USED
C4
0.33PF
C6
0.1PF
C5
100PF
R10
499:
R9
0:
R8
0:
Q1
SUB85N10-10
TP3
SENSE
TP4
UV
TP5
OV
TP1
VDD
TP6
TIMER
VEE
VEE
J2
TP7
GATE
F1
10A
TP2
VEE
U1
GND
-48V
GND
-48V
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
Evaluation Board Schematic
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM5068
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
PART VALUE PACKAGE DESCRIPTION PART NUMBER
C1 NOT USED
C2 NOT USED
C3 0.022uF/ 50V C0805 CAPACITOR, CERAMIC,KEMET C0805C223K5RAC
C4 0.33uF / 50V C0805 CAPACITOR,CERAMIC,KEMET C0805C334K5RAC
C5 100uF / 100V CAPACITOR, ALUMINIUM EEV-FK2A101M
ELECTROLYTIC, SURFACE
MOUNT,PANASONIC
C6 0.1uF / 100V C1206 CAPACITOR, CERAMIC, TDK C3216X7R2A104KT
F1 10A FUSE SMD_FUSE COOPER BUSSMAN FAST ACTING TR/SFT-10
FUSE TRON (Digikey # 283-2439-2-ND)
J1 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010
J2 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010
Q1 100V / 60A N-Channel Power VISHAY SUB85N10-10
MOSFET,TO263
R1 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R2 100K R1206 SMD RESISTOR, 1% TOL CRCW12061003F
R3 4.02K R0805 SMD RESISTOR, 1% TOL CRCW08053401F
R4 3.04K R0805 SMD RESISTOR, 1% TOL CRCW08053040F
R5 100K R0805 SMD RESISTOR, 1% TOL CRCW08051003F
R6 0 R0805 SMD RESISTOR, 1% TOL CRCW08050000F
R7 50m R2512 SMD RESISTOR, 1% TOL WSL-2512 .050F
R8 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R9 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R10 499 R1206 SMD RESISTOR, 1% TOL CRCW1206499RF
U1 LM5068 VSSOP-8 Texas Instruments LM5068
24 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM5068
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013
www.ti.com
26 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5068
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 26
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM5068
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5068MM-2/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S67B
LM5068MM-4/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S69B
LM5068MMX-2/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S67B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5068MM-2/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5068MM-4/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5068MMX-2/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Oct-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5068MM-2/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM5068MM-4/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM5068MMX-2/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Oct-2016
Pack Materials-Page 2
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