LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 LM5068 Negative Voltage Hot Swap Controller Check for Samples: LM5068 FEATURES DESCRIPTION * The LM5068 hot-swap controller provides intelligent control of power supply connections during the insertion and removal of circuit cards powered by live system backplanes. 1 2 * * * * * * * * * Safe Module Insertion and Removal from Live Backplanes In-Rush Current Limiting for Safe Board Insertion into Live Backplanes Fast Response to Over-Current Fault Conditions with Active Current Limiting -10V to -90V Input Range Programmable Under-Voltage/Over-Voltage Shutdown Protection with Adjustable Hysteresis Programmable Multi-Function Timer for Board Insertion De-Bounce Delay Fault Timer Avoids Nuisance Trips Caused by Short Duration Load Transients Active Gate Clamping During Initial Power Application Available in both Latched Fault and Automatic Re-Try Versions Available with either Active HIGH or Active LOW Power Good Flag APPLICATIONS * * * * * * The LM5068 provides both in-rush current control and short-circuit protection functions, and limits power supply transients in the backplane caused by the insertion of additional circuit cards. The LM5068 controls the external N-Channel MOSFET to provide programmable load current limiting and circuit breaker functions using a single external current sense resistor. The LM5068 issues a power good (PWRGD) signal at the conclusion of a successful power-on sequence. Input over-voltage or under voltage fault conditions will cancel the PWRGD indication. The LM5068-1 and -2 indicate power-good as an open-drain active HIGH PWRGD state. The LM50683 and -4 indicate power-good as an open-drain active LOW PWRGD state. The LM5068-1 and -3 latch off after a fault condition is detected while the LM5068-2 and -4 continuously re-try at intervals set by a programmable timer. The LM5068 is available in a VSSOP-8 package. - 48V Power Modules Central Office Switching Distributed Power Systems Electronic Circuit Breaker PBX Systems Negative Power Supply Control 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Typical Application VDD (GND) RF 499: ENABLE R1 100 k: 1% CF + 0.1 PF + PWRGD VDD CL 100 PF UV R2 5.5 k: 1% LOAD LM5068 OV VEE TIMER R3 4.5 k: 1% CT 0.22 PF Cc 22 nF Rs 12 m: VEE (-48V) GATE + + SENSE Q1 SUB85N10-10 Figure 1. Negative Power Supply Control Connection Diagram 1 8 VDD PWRGD 2 7 TIMER OV LM5068 3 6 UV GATE VEE SENSE 4 2 5 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 PIN DESCRIPTION PIN NAME 1 PWRGD 2 3 DESCRIPTION APPLICATION INFORMATION Open Drain Power Good indicator Following a successful power-up sequence the PWRGD signal will be active. The LM5068-1 and -2 are configured for an active power-good state as HIGH, while the LM5068-3 and -4 are configured for an active power-good state as LOW. OV Line Over-Voltage Shutdown An external resistor divider from the power source sets the over-voltage shutdown level. Hysteresis is generated by an internal current source which sources 20 A into the external divider when the OV pin exceeds 2.5V. UV Line Under-Voltage Shutdown An external resistor divider from the power source sets the under-voltage shutdown level. Hysteresis is set by an internal current source which sinks 20 A from the external divider when the UV pin falls below 2.5V. 4 VEE Negative Supply Voltage Input 5 SENSE 6 Current Sense Input Load current is monitored via an external current sense resistor (Rs). If the voltage across Rs exceeds 50mV the fault timer is initiated. Load current is actively limited to 100mV/Rs. If the sense voltage exceeds 200mV due to a catastrophic fault, the fast gate pull down circuit will reduce the MOSFET gate voltage and initiate active current limiting. GATE N-Channel MOSFET Gate Drive Output This output is pulled high by a 60 A current source to turn on the MOSFET. 7 TIMER Timer Input An external capacitor connected to this pin sets the initial start-up delay and the delay to shutdown in the event of an over-current condition. This pin is also used for the automatic re-try timing sequence, following fault shutdown (-2 and -4 versions). 8 VDD Positive Supply Voltage Input Configuration Table Part Number Latch Off /Successive Re-try Power Good Polarity LM5068MM-1/MMX-1 Latch Off Active HIGH LM5068MM-2/MMX-2 Auto Re-try Active HIGH LM5068MM-3/MMX-3 Latch Off Active LOW LM5068MM-4/MMX-4 Auto Re-try Active LOW Package VSSOP- 8 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 3 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) VDD (VDD to VEE) 100V PWRGD (PWRGD to VEE) 100V SENSE (SENSE to VEE) 8V UV/OV (Clamped) (UV/OV to VEE) 8V All Other Inputs to VEE 16V Junction Temperature (TJ) +150C Storage Temperature (TS) -55C to +150C Soldering Information ESD Rating (1) (2) (3) (3) 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The ESD rating of Pin 7 is 1.5kV. It is recommended that proper ESD precautions are taken to avoid performance degradation or loss of functionality. Operating Ratings Supply Voltage Range (VDD) 10V to 90V Junction Temp. Range -40C to +105C Electrical Characteristics Specifications in standard typeface are for TJ = +25C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise noted VDD - VEE = 48V. Symbol Parameter Conditions Min Typ Max Units 0.82 1.3 mA 580 1000 A 90 V VDD Supply IIN Supply Current ISD Shutdown Current VDD - VEE Operating Supply Range UV/OV = 0V 10 UV/OV Shutdown VUVS VDD Under-voltage Shutdown 8.5 V VUVSH VDD Under-voltage Shutdown Hysteresis 0.6 V VUV Under-voltage Comparator Threshold IUVHCS Under-voltage Hysteresis Current Source VOV Over-voltage Comparator Threshold IOVHCS Over-voltage Hysteresis Current Sink tUVCD UV Comparator Delay UV Low to Gate Low 1100 ns tOVCD OV Comparator Delay OV High to Gate Low 500 ns 2.45 2.5 2.55 V 18 20 22 A 2.45 2.5 2.55 V 18 20 22 A Current Limit Voltage VCB Circuit Breaker Current Limit Voltage 40 50 60 mV VAC Analog Current Limit Voltage 80 100 120 mV VFDC Fast Discharge Current Limit Voltage (Fast Gate Pull Down Threshold) 150 200 250 mV -30 -15 Sense Input ISENSE 4 Sense Input Current VSENSE = 50mV Submit Documentation Feedback A Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Electrical Characteristics (continued) Specifications in standard typeface are for TJ = +25C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise noted VDD - VEE = 48V. Symbol Parameter Conditions Min Typ Max Units Timer VTHVT Timer High Voltage Threshold 4 VTLVT Timer Low Voltage Threshold 1 ITIMER Timer On (Initial Cycle, Sourcing) VTIMER = 2V Timer Off (Initial Cycle, Sinking) VTIMER = 2V Timer On (Circuit Breaker, Sourcing) VTIMER = 2V 200 240 280 A Timer Off (Cooling Cycle, Sinking) VTIMER = 2V 4 6 8 A Saturation Gate Drive Voltage VDD- VEE = 48V 9 10.6 12 V 4 6 V V 8 27 A mA Gate Drive VG VDD- VEE = 10V 7.8 V VGLT Gate Low Threshold Before Gate ramp-up IGATE Gate Pin Current (Sourcing) VSENSE = 0V 0.5 Gate Pin Current (Sinking) VSENSE = 150mV VGATE = 3V 2.7 mA Gate Pin Current (Sinking) VSENSE = 300mV VGATE = 1V 300 mA VPGLV PWRGD Low Voltage ISINK = 1mA 0.2 IPGLC PWRGD High Leakage Current VPWRGD = 90V VPGV GATE Voltage at onset of PWRGD 40 60 V 80 A PWRGD 0.6 V 1 A 8 V Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 5 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Block Diagram VREG + SERIES REGULATOR VDD UV HYSTERESIS CS 0.5V 20PA 2.5V + - UV 60PA OV + 2.5V GATE 20PA OV HYSTERESIS CS VREG CONTROL LOGIC + 200mV UV/OV or FAULT VEE VEE VREG 6PA 240PA + 4V 100mV + - + - TIMER VEE 200Ps SOFTSTART 1V + - SENSE 50mV 6PA VEE PWRGD / PWRGD VEE VEE 6 Submit Documentation Feedback VEE VEE Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Typical Performance Characteristics IIN vs Temperature IIN vs VDD 1.2 0.801 VDD = 90V -40oC 0.701 1.1 0.601 1 -25oC IIN (mA) IIN (mA) 0.501 0.9 VDD = 48V 125oC 0.401 0.301 0.8 0.201 0.7 0.101 0.6 -40 0.001 -25 0 25 50 75 105 0 2 4 6 8 VDD (V) TEMPERATURE (oC) Figure 2. Figure 3. VDD Under-Voltage Shutdown (VUVS) vs Temperature VDD Under-Voltage Shutdown Hysteresis (VUVSH) vs Temperature 8.6 0.8 8.55 0.75 8.5 0.7 8.45 0.65 VUVSH (V) VUVS (V) 10 12 14 16 18 20 22 8.4 8.35 0.6 0.55 8.3 0.5 8.25 0.45 8.2 -40 -25 0 50 25 75 0.4 -40 105 -25 0 25 50 75 105 TEMPERATURE (oC) TEMPERATURE (oC) Figure 4. Figure 5. Under-Voltage Comparator Threshold (VUV) and OverVoltage Comparator Threshold (VOV) vs Temperature Under-Voltage Comparator Threshold Hysteresis Current Source (IUVHCS) vs Temperature 2.52 21 VOV 2.50 20.5 IUVHCS (PA) VUV(V) / VOV(V) 2.51 21.5 VUV 2.49 20 2.48 19.5 2.47 19 2.46 -40 -25 0 25 50 75 105 18.5 -40 -25 0 25 50 TEMPERATURE (oC) TEMPERATURE (oC) Figure 6. Figure 7. 75 105 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 7 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Over-Voltage Comparator Threshold Hysteresis Current Sink (IOVHCS) vs Temperature 1400 21 1200 tUVCD (ns) / tOVCD(ns) 21.5 20.5 IOVHCS (PA) UV Comparator Delay (tUVCD) and OV Comparator Delay (tOVCD) vs Temperature 20 19.5 tUVCD 1000 800 600 tOVCD 19 18.5 -40 400 -25 0 25 50 75 200 -40 105 -25 0 25 50 75 105 TEMPERATURE (oC) TEMPERATURE (oC) Figure 8. Figure 9. Circuit Breaker Current Limit Voltage (VCB) vs Temperature Analog Current Limit Voltage (VAC) vs Temperature 55 106 104 53 VAC (mV) VCB (mV) 102 51 100 98 49 96 47 -40 -25 0 25 50 75 94 -40 105 -25 o 25 50 75 105 o TEMPERATURE ( C) Figure 10. Figure 11. Fast Discharge Current Limit Voltage (VFDC) vs Temperature Timer High Voltage Threshold (VTHVT) vs Temperature 215 4.3 210 4.2 205 4.1 VTHVT (V) VFDC (mV) TEMPERATURE ( C) 200 4.0 195 3.9 190 3.8 185 -40 -25 0 25 50 75 105 o 8 0 3.7 -40 -25 0 25 50 75 105 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Timer On (Initial Cycle, Sourcing) vs Temperature 1.2 7.5 1.16 7.0 1.12 6.5 ITIMER (PA) VTLVT (V) Timer Low Voltage Threshold (VTLVT) vs Temperature 1.08 6.0 1.04 5.5 1.0 5.0 0.96 -40 -25 0 25 50 75 4.5 -40 105 -25 0 25 50 75 105 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 14. Figure 15. Timer On (Circuit Breaker, Sourcing) vs Temperature Timer Off (Cooling Cycle, Sinking) vs Temperature 260 7.5 250 7 240 6.5 ITIMER (PA) ITIMER (PA) o 230 6 220 5.5 210 5 200 -40 -25 0 25 50 75 4.5 -40 105 -25 0 o 25 50 75 105 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 16. Figure 17. Saturation Gate Drive Voltage (VG) vs Temperature (48V) Saturation Gate Drive Voltage (VG) vs Temperature 8 12 11.5 7.95 VDD - VEE = 48V VDD - VEE = 10V 7.9 11 VG (V) VG (V) 7.85 10.5 7.8 7.75 10 7.7 9.5 9 -40 7.65 -25 0 25 50 75 105 7.6 -40 -25 0 25 50 75 105 TEMPERATURE (oC) TEMPERATURE (oC) Figure 18. Figure 19. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 9 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) PWRGD Low Voltage (VPGLV) vs Temperature 75 0.35 70 0.3 65 0.25 VPGLV (V) IGATE (PA) Gate Pin Current (Sourcing) (IGATE) vs Temperature 60 0.2 55 0.15 50 0.1 45 -40 -25 0 25 50 75 ISINK = 1mA 0.05 -40 105 25 0 25 50 TEMPERATURE ( C) TEMPERATURE (oC) Figure 20. Figure 21. o 75 105 Gate Voltage at onset of PWRGD (VPGV) vs Temperature 8.1 8.05 8.0 VPGV (V) 7.95 7.9 7.85 7.8 7.75 7.7 -40 -25 0 25 50 75 105 TEMPERATURE (oC) Figure 22. 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 FUNCTION DESCRIPTION The LM5068 is designed to facilitate the insertion and removal of circuit cards into live backplanes in a controlled manner. Because the supply bypass capacitors on the circuit card can draw large transient currents, it is critical to control the supply current during insertion to limit system power glitches and connector damage. Controlling inrush current prevents other boards in the system from resetting during board insertion. Load short-circuit protection is accomplished by active current limiting of the load current. The topology of the LM5068 is illustrated in the simplified application circuit shown in Figure 23. PLUG-IN BOARD + LIVE BACKPLANE CL LM5068 DC-DC CONVERTER VDD (GND) VEE (-48V) Figure 23. LM5068 Topology Start-Up Operation The LM5068 resides on a removable circuit card. Power is applied to the load or power conversion circuitry through an external N-Channel MOSFET switch and current sense resistor. When power is initially applied to the card, the gate of the external MOSFET is held low. When certain interlock conditions are met, a turn-on sequence begins and an internal 60 A current source charges the gate of the MOSFET. To initiate the start-up sequence, all of the following interlock conditions must be satisfied: * The input voltage VDD - VEE exceeds 9V(VUVS) * The voltage at UV is above 2.5V (VUV) * The voltage at OV falls below 2.5V (VOV) * The voltage on the Timer capacitor (CT) is less than 1V (VTLVT) * The GATE pin is below 0.5V (VGLT) When all of the interlock conditions are met, a 6 A TIMER current source is enabled to charge the timer capacitor CT. During this initial timer sequence the GATE output is held low. When the CT capacitor successfully charges up to 4V, the TIMER circuit resets the timer capacitor to 1V and activates a 60 A current source (IGATE) into the MOSFET gate. VDD (GND) RF R1 +C F VDD PWRGD CL UV + LM5068 R2 OV TIMER R3 +C VEE SENSE GATE T + CC VEE (-48V) RS Q1 Figure 24. Hot Swap Controller Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 11 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Over and Under-Voltage Lockout The line Under-voltage lockout (UVLO) circuitry of the LM5068 monitors VDD for under-voltage conditions, where VUVS is the negative going threshold and the hysteresis is VUVSH (see Electrical Characteristics). A VDD - VEE voltage less than 8.5V (VUVS) keeps the controller in a disabled mode. Raising the VDD voltage above 9.1V (VUVS + VUVSH) releases the VDD UVLO and enables the controller. In addition to the internal UVLO circuit, the UV and OV comparators monitor the input line voltage through an external resistor divider. Programmable UV and OV comparator hysteresis is implemented with switched 20A current sources that raise or lower the OV and UV pins when the comparators reach their threshold. Either UV or OV fault conditions will switch the GATE pin low and disconnect the power to the load. To restart the GATE pin, the supply voltage must return to a level which is greater than the UV fault and less than the OV fault threshold and all of the interlock conditions (with the exception of the TIMER) must be met. Removal of the circuit card from the backplane initiates an under-voltage condition. The series MOSFET is then disabled to disconnect the source of power to the load. The under-voltage threshold and hysteresis are programmed by the external resistor divider connected to the UV pin. Timer The value of the CT capacitor sets the duration of the LM5068's timer delay and filter functions. There are four charging and discharging modes: 1. 6A slow charge for initial timing delay and post-fault re-try timer (LM5068-2 and -4) 2. 240A fast charge for circuit breaker delay. 3. 6A slow discharge for circuit breaker "cool-off". 4. Low impedance switch to reset capacitor after initial timing delay, input under-voltage lockout, and during over-voltage and under-voltage initial timing. Current Control The LM5068 has three current sense thresholds which protect the backplane supply and circuit card from overload conditions. The voltage drop across the sense resistor (RS) is monitored at the SENSE pin. The overcurrent protection functions are determined through the following three distinct thresholds at the SENSE pin: 1. Circuit Breaker (CB) threshold (typically 50mV) 2. Analog Current Limit (ACL) loop threshold (typically 100mV) 3. Fast Discharge Current (FDC) threshold (typically 200mV) When the voltage drop across RS exceeds 50mV the Circuit Breaker comparator indicates an over-load condition. The TIMER sources 240A into CT when SENSE exceeds 50mV and sinks 6A from CT when SENSE falls below 50mV. If the CT capacitor ramps to a 4V threshold, a fault condition is declared and the gate of the MOSFET is forced low, disconnecting the power to the load. Active Current Limiting (ACL) is activated when the voltage across sense resistor RS reaches 100mV. The LM5068 controls the gate of the MOSFET and maintains a constant output load current equal to 100mV/ RS. In the ACL mode the SENSE pin is greater than 50mV and the TIMER charges CT with 240A. A fault will be declared if the LM5068 remains in the ACL mode longer than the circuit breaker timer period. Fast Discharge Current (FDC) responds to fast rising over-loads such as short circuit faults. During a short circuit event the fast rising current may overshoot past the ACL threshold due to the finite response time of the ACL loop. If the SENSE voltage reaches 200mV a fast discharge comparator quickly pulls GATE pin low. The rapid response of the FDC circuit assures a fast and safe transition to the ACL mode. The LM5068 circuit breaker action filters low duty cycle over-load conditions to avoid declaring a fault during short duration load transients. The timer charges capacitor CT with 240A when the SENSE voltage is greater than 50mV. When the SENSE pin voltage falls below 50mV, a 6A current discharges the TIMER capacitor. Repetitive over-current faults with duty cycle greater than 2.5% will eventually charge CT and trip the fault timer. This feature protects the pass MOSFET which has a fast heating and slow cooling characteristic. 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Latch-Off and Auto-Retry If the fault conditions persist long enough for TIMER to charge CT to 4V, the LM5068 latches off (LM5068-1, -3) or switches off and initiates the re-try timer (LM5068-2, -4). At the fault condition, after reaching the 4V, the TIMER pin will continue to ramp-up with 6A current source until it reaches the internal regulated voltage, which is equivalent to the saturation GATE drive voltage. The LM5068-1 and LM5068-3 remains off until the controller is reset by either temporarily pulling the UV pin low, pulling the TIMER pin below 1 volt, or decreasing the input voltage below the internal VDD under-voltage lockout (UVLO) threshold. The LM5068-2 and LM5068-4 respond to a fault condition by pulling the GATE and TIMER pins low and then initiating a timer sequence for automatic re-try. The re-try timer sequence begins with CT capacitor being charged slowly to 4V with a 6A current source and then discharged quickly to 1V with a 30mA discharge current. After 8 charge/discharge cycles the GATE pin is released and charged with a 60A current source. If the fault condition persists, the LM5068 will again turn off the MOSFET and another 8-cycle fault timer sequence will begin. Power Good Flag The power good flag (PWRGD) is activated when the MOSFET GATE is fully enhanced (>8V) and the voltage input UV and OV comparators are satisfied. The power good output is a 90V capable open drain N-Channel MOSFET. The LM5068-1 and LM5068-2 provide an active HIGH power-good state, while the LM5068-3 and LM5068-4 are configured for an active LOW power-good state. The UV comparator, OV comparator, VDD UVLO, or a circuit breaker time-out will reset the power good flag. Internal Soft-Start An internal soft-start feature ramps the (positive) input of the analog current limit amplifier during initial start-up. The ramp duration is approximately 200s. This feature reduces the load current slew rate (di/dt) at start-up. Design Information The LM5068 contains an internal regulator enabling the VDD pin to be connected directly to the line voltage from 10 to 90V. A local RC filter (0.1F ceramic capacitor and 499 resistor) connected between VDD and VEE is recommended to filter supply transients that exceed the 100V Absolute Maximum Rating. UV and OV Thresholds and Voltage Divider Selection for R1, R2, and R3 Two comparators detect under-voltage and over-voltage conditions at the UV and OV pins. The threshold voltages (VUV , VOV) of the UV and OV comparators are nominally 2.5V. Hysteresis is accomplished by 20A current sources (IUVHCS), into the external resistor divider connected to the UV and OV pins as shown in Figure 25 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 13 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Vsupply www.ti.com UV HYSTERESIS CS RF VDD 20PA R1 CF + 2.5V + UV R2 OV + 2.5V R3 20PA VEE OV HYSTERESIS CS LM5068 Figure 25. UV/OV Setting Hysteresis is necessary to prevent a possible "chattering" condition when the controller enables or disables the external MOSFET. The change in line current interacts with the line impedance. This interaction can cause several rapid on/off cycles on the MOSFET. A hysteresis window larger than the line impedance voltage drop prevents this condition. The impedance seen looking into the resistor divider from the UV and OV pin determines the hysteresis level. UV/OV ON and OFF thresholds are calculated as follow: R1 UV turn-on = UV turn-off = VUV + VUV + IUVHCSR1 R 2 + R3 R 1 + R 2 + R3 R2 + R3 OV turn-off = VUV R1 + R2 + R 3 R3 VOV OV turn-on = R3 (1) (2) VOV (3) - IUVHCS (R1 + R2) + VOV (4) The independent UV and OV pins provide complete flexibility for the user to select the operational voltage range of the system. However, due to the UV Abs Max rating, the UV and OV thresholds can't be simultaneously set to extremes in one resistor string. For the wide ranges of input voltages (i.e. UV threshold to12V and OV threshold to 90V) it is recommended to use two separate voltage dividers to set the UV and OV thresholds independently. 14 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 The typical operating ranges of under-voltage and over-voltage thresholds are calculated from the above equations with known resistors. For example, for resistor values: R1=130K, R2=5.5K, and R3=4.5K, the computed thresholds are: * UV turn-on = 37.60V * UV turn-off = 35.0V * OV turn-off = 77.78V * OV turn-on = 75.07V To maintain the threshold's accuracy, a resistor tolerance of 1% or better is recommended. Calculation of Normal, Circuit Breaker, and Retry Timing The CT capacitor at the TIMER pin controls the timing functions of the LM5068. When the interlock conditions are met the timer capacitor is charged to 4V in a slow initial delay time period tIDT calculated from: tIDT = 4V x CT 6 PA (5) If the SENSE pin detects more than 50mV across RS, the TIMER pin charges CT with 240A. The Circuit Breaker timeout period tCBT is calculated from: tCBT = 4V x CT 240PA (6) When the LM5068-2 or LM5068-4 is latched, it pulls down the GATE pin and initiates eight, 6A charging cycles between 1V and 4V on CT. The total re-try time period tRT is given by: tRT = 8 x 3V x CT 6PA (7) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 15 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Sense Resistor (Rs), Timer Capacitor (CT) and N-Channel Mosfet (Q1) Selection To select the proper MOSFET, the following safe operating area (SOA) parameters are needed: maximum input voltage, maximum current and the maximum current conduction time. First, RS is calculated for the maximum operating load current (IL(MAX)) and the minimum circuit breaker trip point (VCB(MIN)): VCB(MIN) RS = IL(MAX) 40mV = IL(MAX) (8) During the initial charging process, the LM5068 may operate the MOSFET in current limit, forcing VAC(MIN) (80mV) to VAC(MAX) (120mV) across RS. The minimum in-rush current and maximum short-circuit limit are calculated from: IINRUSH(MIN) = 80mV RS ISHORT-CIRCUIT(MAX) = (9) 120mV RS (10) The value of TIMER capacitor (CT) is calculated in order to prevent CT from timing out before the load capacitor is fully charged using the slowest expected charging rate of the load capacitor. Assuming there is no initial resistive loading, the time necessary to charge the load capacitor CL is calculated from: CL x VIN(MAX) tCL CHARGE = IINRUSH(MIN) (11) Applying Equation 9 and Equation 11 to Equation 6 gives the TIMER capacitor value of: CL x VIN(MAX) x RS x 240PA CT = 4V x 80mV (12) Finally, the SOA curves of a prospective MOSFET are checked using VIN from equation Equation 10 and time of the current flow from Equation 6. (MAX), and ISHORT-CIRCUIT (MAX) calculated Example: For: IL=1A, VDD = 48V, VDD (MAX) = 100V and CL=100F, 40mV RS = CT = 1A = 40m: (13) 100PF x 100V x 40m: x 240PA = 300nF 4V x 80mV (14) To account for tolerances of RS, CL, TIMER current and TIMER threshold voltage, the computed CT value should be increased, for this example 50% was selected, therefore: CT = 300nF * 1.5 = 450nF The maximum active current limiting value and duration are: ISHORT-CIRCUIT(MAX) = tCBT = 16 4V x CT 240PA 120mV = 3A 40m: (15) 4V x 450nF = 7.5ms = 240PA (16) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 The N-channel MOSFET selection for use with the LM5068 controller in this example must be capable of sustaining VDD=100V and I(MAX)=3A for 7.5ms in the worst case fault condition. A device that meets the established criteria is the Vishay - 5UB85N10-10. External Sense Resistor Precise current measurement depends on the accuracy of the sense resistor (RS). For the optimal results, Kelvin connection and close location of RS to the LM5068 should be considered. Figure 26 demonstrates PCB layout for the Kelvin sensing. The RS power rating should be greater than I2L*R, where IL is the normal maximum operating load. GATE PIN UV PIN LM5068 VEE PIN SENSE PIN TO NEGATIVE TERMINAL OF POWER SOURCE SENSE RESISTOR TO SOURCE OF MOSFET HIGH CURRENT PATH Figure 26. Sense Resistor Connections Timing Diagrams Current Limit Initial Timing 12 3 4 56 Normal Mode 7 VTHVT 6PA 6PA TIMER VTLVT 60PA GATE DRAIN VAC VCB SENSE PWRGD Gate Ramp-up Figure 27. System Power-Up Timing Behavior Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 17 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Assuming all of the initial conditions are met, the power-up sequence starts with Timer capacitor (CT) getting charged. CT is charged with 6A current source up to VTHVT (4V) then quickly discharge to VTLVT (1V). At time point (2) the 60A GATE current source is enabled. The GATE voltage increases until the MOSFET starts conducting causing the SENSE voltage to increase until Active Current Limiting is activated (3). During the current limiting period (3-4), CT is charged again, but there is not enough time to reach the 4V threshold before the load capacitor is fully charged and the SENSE voltage falls below VCB. The GATE continues to fully enhance the MOSFET and activating the PWRGD when the GATE voltage exceeds 8V (see Figure 27). UV DROPS BELOW UV HIGH, GATE AND TIMER ARE PULLED DOWN UV CLEARS UV LOW, TIMER RAMPS UP PROVIDED ALL INTERLOCK CONDITIONS ARE MET 1 2 TIMER CLEARS VTLVT. GATE VOLTAGE RAMPS UP 4 3 5 6 7 8 9 10 11 UV HIGH UV UV LOW VTHVT 6 PA 240 PA 6 PA VTLVT TIMER 60 PA GATE 60 PA VAC VCB SENSE PWRGD DRAIN INITIAL TIMING GATE RAMP-UP Figure 28. Under-Voltage Timing Behavior UV drops below UV HIGH (time point 1) puts the controller into a disabled mode. Later, UV increases over the UV LOW threshold (time point 3), which initiates a system power-up sequence. 18 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 OV PIN OVERSHOOTS OV HIGH, GATE IS PULLED DOWN. PGOOD IS PULLED LOW AND TIMER IS UNAFFECTED 1 2 OV DROPS BELOW OV LOW, GATE STARTS RAMPING UP AND PGOOD BECOMES HIGH WHEN GATE VOLTAGE REACHES VG 3 4 5 6 7 OV LOW OV HIGH OV VTHVT 230 PA 6 PA TIMER GATE 60 PA VG 60 PA VAC VCB SENSE PWRGD Figure 29. Over-Voltage Timing Behavior During normal operation, if the OV pin exceeds OV HIGH, as shown at time point 1 in the above diagram, the TIMER status is unaffected. The GATE and PWRGD ( for LM5068-1 & -2) pins are pulled low and the load is disconnected. At time point 2, OV recovers and drops below the OV LOW threshold, the GATE start-up cycle begins. If the load capacitor is completely depleted during OV conditions, a full start-up cycle is initiated. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 19 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 www.ti.com Normal Mode 1 2 VTHVT 240PA TIMER VTLVT GATE DRAIN VAC VCB SENSE PGOOD Circuit Breaker Limit Figure 30. Circuit Breaker Current Limit Fault The above timing waveform shows the circuit breaker current limit fault behavior. The timer capacitor is charged with 240A when the SENSE pin exceeds VCB. If the SENSE pin drops below VCB before the TIMER reaches VTHVT, the timer capacitor will be discharged with 6A. In the above figure when TIMER exceeds VTHVT, GATE is pulled low immediately to disconnect power to the load. Normal Mode 1 2 345 6 Normal Mode VTHVT 240PA 6PA TIMER VTLVT 60PA GATE DRAIN VAC VCB SENSE PWRGD HIGH Analog Circuit Limit Gate Ramp-up Figure 31. Analog Current Limit Fault 20 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Figure 31 shows analog current limit behavior when the SENSE pin voltage exceeds VAC for a period of time, which activates the Analog Current Limit but never reaches the fault timer threshold. At that time the GATE is regulated by the analog current limit amplifier loop. When the SENSE voltage falls below VAC, GATE is allowed to charge with a 60A current source. A compensation circuit consisting of a resistor and a capacitor in series, connected between GATE and VEE stabilizes the current limit loop. Normal Mode 1 2 VTHVT VTLVT TIMER GATE DRAIN VFDC SENSE VAC VCB PWRGD Fast Gate Pull Down Figure 32. Fast Current Limit Fault In case of a severe fault (for example sudden short-circuit of the output load) the SENSE pin exceeds the VFDC threshold and GATE immediately pulls down until the Active Current Limit loop establishes control of the current in the MOSFET. Careful selection of TIMER capacitor and MOSFET with adequate current and voltage ratings will prevent damage to MOSFET low impedance faults. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 21 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Normal Mode www.ti.com 1 2 Circuit Breaker Timeout Mode 3 4 5 6 7 Normal Mode VTHVT 240PA 6PA TIMER 6PA VTLVT 30mA 60PA GATE DRAIN VAC VCB SENSE PWRGD Circuit Breaker Limit Gate Ramp-up Figure 33. Shutdown Cooling Timing Behavior Figure 33 shows the timer behavior for LM5068-2, -4 during fault re-try time. During normal operation, whenever the SENSE pin exceeds the 50mV, circuit breaker fault limit, the timer capacitor begins to charge. If the TIMER pin voltage exceeds 4V, the GATE is pulled down immediately, and LM5068-2, -4 disconnects power to the load. The TIMER starts the fault re-try cycle by discharging CT with 30mA to the VTLVT threshold. The TIMER then charges CT with 6A to the VTHVT threshold. After eight charging phases and nine discharging phases, LM50682, -4 initiates an automatic retry start-up cycle. 22 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Evaluation Board Schematic GND GND J1 J2 -48V TP8 UV/OV TP1 VDD R10 499: R1 0: R5 100k: + C5 100PF + -48V C6 0.1PF TP4 UV R2 100k: VEE U1 TP5 OV R3 4.02k: VDD 8 OV TIMER 7 3 UV GATE 6 4 VEE SENSE 5 1 PWRGD 2 TP6 TIMER + R4 3.40k: C2 NOT USED + R9 0: + TP7 GATE LM5068 C1 NOT USED C4 0.33PF VEE + R6 0: C3 22nF Q1 SUB85N10-10 R7 50m: : F1 10A TP2 VEE R8 0: TP3 SENSE Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 23 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 PART VALUE C1 NOT USED 24 www.ti.com PACKAGE DESCRIPTION PART NUMBER C2 NOT USED C3 0.022uF/ 50V C0805 CAPACITOR, CERAMIC,KEMET C0805C223K5RAC C4 0.33uF / 50V C0805 CAPACITOR,CERAMIC,KEMET C0805C334K5RAC C5 100uF / 100V CAPACITOR, ALUMINIUM ELECTROLYTIC, SURFACE MOUNT,PANASONIC EEV-FK2A101M C6 0.1uF / 100V C1206 CAPACITOR, CERAMIC, TDK C3216X7R2A104KT F1 10A FUSE SMD_FUSE J1 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010 J2 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010 Q1 100V / 60A N-Channel Power MOSFET,TO263 VISHAY SUB85N10-10 R1 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F R2 100K R1206 SMD RESISTOR, 1% TOL CRCW12061003F R3 4.02K R0805 SMD RESISTOR, 1% TOL CRCW08053401F R4 3.04K R0805 SMD RESISTOR, 1% TOL CRCW08053040F R5 100K R0805 SMD RESISTOR, 1% TOL CRCW08051003F R6 0 R0805 SMD RESISTOR, 1% TOL CRCW08050000F R7 50m R2512 SMD RESISTOR, 1% TOL WSL-2512 .050F R8 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F R9 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F SMD RESISTOR, 1% TOL CRCW1206499RF Texas Instruments LM5068 R10 499 R1206 U1 LM5068 VSSOP-8 COOPER BUSSMAN FAST ACTING TR/SFT-10 FUSE TRON (Digikey # 283-2439-2-ND) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 25 LM5068 SNVS254C - JANUARY 2004 - REVISED MARCH 2013 26 www.ti.com Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 LM5068 www.ti.com SNVS254C - JANUARY 2004 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 26 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM5068 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM5068MM-2/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S67B LM5068MM-4/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S69B LM5068MMX-2/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 S67B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5068MM-2/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5068MM-4/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5068MMX-2/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5068MM-2/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MM-4/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MMX-2/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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