ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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GENERA L DESCRIPTION
T he A K43 87 offe rs th e pe rfect mix for cost and performance based au dio syste ms. Using AK M's multi bit
arc hit ecture for its modu la t or the AK 438 7 del i ve rs a wi de dyna mi c r ange wh ile pr eser vi ng linea rity for
impro ved THD+N performance. T he AK 4387 int egrat es a combination of SCF and CT F filters in creasing
performa nc e for systems with excess ive clock jitte r. The 24 Bit word lengt h and 19 2kHz sampling rate
make this part ideal for a wide ran ge of applications includ in g DVD-Audio. T he AK4 387 is offered in a
space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
S C F wit h High Tol e rance t o Cl ock Jit t e r
Single Ended Output Buffer
Digita l de-emphasi s for 32k, 44.1k an d 48kHz sampling
Soft mute
Digital A ttenuator (Linea r 256 steps)
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -90dB
Dynamic Range: 106dB
Power supply: 4. 5 to 5. 5V
Very Small Package: 16pin TSSOP
LRCK
BIC
K
SDTI
Audio
Data
Interface
MCLK
RSTN
∆Σ
Modulator AOUTL
8X
Interpolator SCF
LPF
AOUTR
AVDD
V
SS
V
COM
De-emphasis
Control
µP
Interface
Clock
Divider
CSN
CCL
K
CDTI
∆Σ
Modulator
8X
Interpolator
DZF
SCF
LPF
ATT
ATT
DVDD
106dB 192kHz 24-Bit 2ch ∆Σ DAC
AK4387
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Ordering Guide
AK4387ET -20
∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4387 Evaluation Board for AK4387
Pin Layo ut
1
MCLK
LRCK
BICK
CSN
CCLK
CDTI
Top
View
2
3
4
5
6
7
8
DZF
DVDD
VSS
AVDD
VCOM
AOUTL
AOUTR
NC
16
15
14
13
12
11
10
9
RSTN
SDTI
Compatibility with AK4384
1. Function
Functions AK4384 AK4387
THD+N -94dB -90dB
Output Vol tag e 3.4Vpp 2.95Vpp
Slow Roll-Off Filter Available Not Availa ble
Mode Settin g Seri al /Par allel Serial
Zero Da ta Detect Pin 2 pins 1 pi n
2. Pi n Configuration
AK4387 AK4384 Pin# Pin# AK4384 AK4387
MCLK MCLK 1 16 DZFL DZF
BICK BICK 2 15 DZFR DVDD
SDTI SDTI 3 14 VDD AVDD
LRCK LRCK 4 13 VSS VSS
RSTN PDN 5 12 VCOM VCOM
CSN SMUTE/CSN 6 11 AOUTL AOUTL
CCLK ACKS/CCLK 7 10 AOUTR AOUTR
CDTI DIF0/CDTI 8 9 P/S NC
3. Register map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
01H Control 2 DZFE 1 0 DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 0 0 INVL INVR DZFB 0 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
: Differ ent points from AK4384
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audi o Ser i al Data Clock Pi n
3 SDTI I Audio Ser i al Data Input Pin
4 LRCK I L/R Clock Pin
5 RSTN I Reset Mode Pin
When at “L”, the AK4387 is in the power-down mode and is held in reset.
The AK4387 must be reset once upon power-up.
6 CS N I Chip Select Pin
7 CCLK I Control Data Clock Pin
8 CDTI I Control Data Input Pi n
9 NC - No Connect pin
No internal bonding. This pin s hould be opene d or conne cted to VSS.
10 AOUTR O Rch Anal og Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pi n, AVDD/2
Norma lly connected to VSS with a 0.1µF c eramic capacito r in parallel w ith a
10µF electrolytic cap.
13 VSS - Ground Pin
14 AVDD - Power Supply Pin
15 DVDD - Power Supply Pin
16 DZF O Lch and Rch Data Zero Input Detect P in
Note: All input pin s sh ou ld not be left floatin g .
ABSOLU TE MAXIM U M RAT IN G S
(VSS= 0 V; Not e 1)
Parameter Symbol min max Units
Power Su ppl y AVDD, DVDD -0. 3 6 .0 V
Input Curr ent (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 DVDD+0.3 V
Ambi ent Oper at ing Temperature Ta -2 0 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages wi th respect to ground.
WARNING: Operat ion at or beyond these limits may results in permanent d amage to the device.
Normal operation is not guaranteed a t these extremes.
RECOMMENDED OPERAT I NG CONDITIO NS
(VSS= 0 V; Not e 1)
Parameter Symbol min typ max Units
Power Supply (Note 2) AVDD, DVDD 4.5 5.0 5.5 V
Note 2 . The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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ANAL O G CHARACT E RIS T ICS
(Ta=25°C; AVDD= DVDD= 5 .0 V; fs=4 4. 1k Hz; BICK=6 4fs; Sig n a l Fr equen cy=1k Hz; 24 bit I n pu t Da ta ;
Measu rement frequency=20 Hz ∼ 20kHz; RL ≥5kΩ; Extern al ci rcuit: Figure 9 (Exampl e 2); unless other wise specified)
Parameter min Typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 3)
fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS -90
-42 -80
- dB
dB
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -90
-39 -
- dB
dB
THD+N
fs=192kHz
BW=40kHz 0dBFS
-60dBFS -85
-39 -
- dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 4) 98 106 dB
S/N (A-weighted) (Note 5) 98 106 dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel G ain Mismatch 0.2 0.5 dB
DC Accuracy
Gain Drift 100 - ppm/°C
Output Voltage (Note 6) 2.75 2.95 3.15 Vpp
Load Resistance (Note 7) 5 kΩ
Load Capacitan ce 25 pF
Power Supplies
Power Supply Current (AVDD+DVDD)
Nor mal Operat ion (RSTN pin = “H” , fs≤96kHz)
Nor mal Operat ion (RSTN pin = “H”, fs=192kHz)
Power-Down Mode (RSTN pin = “L”) (Note 8)
17
20
60
27
32
150
mA
mA
µA
Note 3. Measured by Audio Precision ( System Two). Refer t o the evaluati on board manual.
Note 4. 100dB at 16bit data.
Note 5. S/N does not depend on input bit length.
Note 6. Full-scale voltage (0dB). Ou tput voltage scales with the voltag e of AVDD,
AOUT (typ.@ 0 dB) = 2. 95 Vpp × AVDD/5.
Note 7. For AC-l oad.
Note 8. All digi tal inputs including cl ock pi ns (MCLK, BICK and LRCK) ar e held AVDD, DVDD or VSS.
SHARP RO LL-OF F FILTER CHARACT E RIS T ICS
(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 9)
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 9) SB 24.1 kHz
Passba nd Ripple PR ± 0. 0 2 dB
Stopband Atten uation SA 54 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Di g i t a l Fi lt e r + L P F
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.03
± 0.03
± 0.03
-
-
-
dB
dB
dB
Note 9. The passband and stopband frequencies scale with fs(system samplin g rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0. 546×fs.
Note 10. Th e calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both chan nel s to input register to the output of ana log signal.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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DC CHARACTERI ST ICS
(Ta=25°C; AV DD=DVDD=4.5 ∼ 5.5V)
Parameter Symbol min typ max Units
High-Level Input Vol ta ge
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA) VOH
VOL AVDD-0.4
- - -
0.4 V
V
Input Leakage Cur r ent Iin - - ± 10 µA
SWIT CHING CHARACTERISTICS
(Ta=25°C; AV DD=DVDD=4.5 ∼ 5.5V, CL = 20pF)
Parameter Symbol min typ max Units
Mas ter Clock Frequency
Duty Cycle fCLK
dCLK 2.048
40 11.2896
36.864
60 MHz
%
LRCK Fr eq ue nc y
Norma l Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Ti ming
BICK P eriod
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 11)
LRCK E d ge to BICK r ising (Note 11)
SDTI Hol d Time
SDTI Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Wi dth Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
RS TN Puls e Wi dth (No te 12)
tPD
150
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. Th e AK4387 can be reset by br in ging RSTN pin = “L”.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Timi ng D iagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Tim ing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Serial Interface Timing
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRI TE Command Input Timing
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPD
VIL
RSTN
Power-down Timing
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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OPERATION OVERVIEW
Syste m Clock
The external clo cks , whic h are required to o perate the AK4387, are MCL K, L RCK and B ICK . The master clo ck ( MCLK )
should be synchronized with LRCK but the phase is not cr itical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are tw o methods to set MCLK frequency . In Manual Setting Mode (ACKS bit
= “0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of M C LK at each sampl ing speed is
set automatically. (Table 2~4). After exiting reset (RSTN pin = “↑”), the AK4387 is in Auto Settin g Mode. In Auto
Setting Mode (ACKS bit = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master
clock becomes the appropriate fr equency (Table 6), it is not necessary to set DFS0/1 .
All exte rnal c lo cks (MCL K, BICK and LR CK) shoul d alw ay s b e p rese nt w henev er the AK4387 is i n the no rmal op eratio n
mode (RSTN pin = ”H”). If these clocks ar e not provided, th e AK4387 may dr aw excess curr ent and may fall into
unpredictable opera tion . This i s because the device utilizes dyn a mic refreshed logi c in ternally. The AK4387 should be
rese t by RSTN pin = “ L” afte r thres e c lo c ks are prov i ded. If the e xte rnal clo c k s are no t pres e nt, the AK 4387 sho uld b e in
the power-down mode (RSTN pin = “L”). After exiting reset at power-up etc., the AK4387 is in the power-down mode
until MCLK and LRCK ar e in put.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 8kHz~48kHz Default
0 1 Double Speed Mode 60kHz~96kHz
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 1152fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz
Ta bl e 2. Syste m Cl ock Ex a m ple (Nor m a l Sp eed Mode @ Ma nua l Sett i ng Mode)
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Tabl e 3. System Clock Example ( Double S pe ed Mode @Manual Setting Mode)
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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LRCK MCLK BICK
fs 128fs 192fs 64fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Tabl e 4. System Clock Example (Qua d Speed Mode @Manua l Setting Mode )
MCLK Sampling Speed
1152fs Normal (fs≤32kHz)
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - - Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - -
Quad
Table 6. System Clock E xam ple (Auto Setting Mode)
Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five ser ial
data modes. In all modes the serial data is MSB-fir st, 2’s compliment for m at and is latched on the rising edge of BI CK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format BICK Figure
0 0 0 0 16bit LSB Justified ≥32fs Figure 1
1 0 0 1 20bit LSB Justified ≥40fs Figure 2
2 0 1 0 24bit MSB Justified ≥48fs Figure 3 Default
3 0 1 1 24bit I2S Compatible ≥48fs Figure 4
4 1 0 0 24bit LSB Justified ≥48fs Figure 2
Table 7. Audio Data Forma ts
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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SDTI
BICK
LRCK
SDTI 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mo de 0 Don’t care Don’t care
15:MSB, 0:LSB
M ode 0 1514 6543210
Lch Data Rch Data
Figure 1. Mode 0 Timing
SDTI
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
M ode 1 D on’t care Don’t care
19:MSB, 0:L SB
SDTI
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0
Don ’t car e Don’t care
22 21 22 21
Lch Data Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care
23
Lch Data Rch Data
23 30 2222423 30
22 1 0 D on’t care
23 22
23
Figure 3. Mode 2 Timing
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:L SB
22 10Don’t care
23
Lch Data Rch Da ta
23 25 322423 25
22 1 0 Don’t care
23 23
Figure 4. Mode 3 Timing
De-emphasis Filter
A digital de-emphasis fil ter is available for 32, 44.1 or 48kHz sampling ra tes (tc = 50/15µs) and is enabled or disabled
wit h DE M0 and DEM 1 . In ca s e of dou bl e speed a n d qu a d spe ed mod e, th e digi t a l de- em p has is fi l t er i s al wa ys off.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF
Default
1 0 48kHz
1 1 32kHz
Table 8. De-emphasis Filter Control (Normal Speed Mode)
Output Volume
The AK4387 includes channel independent digital output volumes (ATT) with 256 lev els at linear step including MU TE.
These volumes are in front of t he DAC and can attenuate the input data fr om 0dB to –48dB and mute. Wh en changin g
levels, tr ansitions are executed via soft changes; thus no switching noise occurs during these transitions. The tran sition
time of 1 level and all 256 levels is shown in Table 10.
Tra n sit ion Time
Samplin g Speed 1 Level 255 to 0
Nor mal Speed Mode 4LRCK 1020LRC K
Double Speed Mode 8LRCK 2040LRC K
Quad Speed Mode 16LRC K 4080LRCK
Table 9. ATT Tr a n siti on Tim e
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Zero Detection
The AK4 387 has channel- independent zeros de te c t func tio n. When the input data at each channel is continuo usl y zero s
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each chann el immediately goes to “L” if input
data o f e ach channel is not zero after going DZF “H”. If RS TN b it is “0”, DZF pins of bo th channels go to “ H”. DZF pin
of both cha nnels go to “L” at 2 ~3/fs afte r RSTN bit returns to “1 ”. Zero detect fun ction can be disabl ed by DZFE bit. I n
this case, DZF pins of both chann els ar e always “L”. DZFB bit can inver t the polarity of DZF pin.
S oft Mute O pe r a ti on
So ft mute ope ratio n is perf ormed at dig ital domain. When the SMU TE bit go es to “1”, the ou tput signal is attenuated by
-∞ during ATT _DATA×ATT transition time (Table 9) from the current ATT level. When the SM UT E bit is returned to
“0”, the mute is cancelled an d the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontin ued an d returned to ATT level by the same cycle. The soft mute is effective for changing the sign al sour ce
with out stopping the sign al transmission.
SMUTE bit
Attenuation
DZF pin
ATT Level
-∞
AOUT
8192/fs
GD GD
(1)
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA×AT T transitio n time (Table 9). F or example, in Normal Spee d M o de , this time i s 1020LRCK c ycle s
(1020/fs) at ATT_DAT A=255.
(2) The analog output correspondin g to th e digital input has a gr oup delay, GD.
(3) If the soft mu te is cancelled bef ore atte nuati ng to -∞ af ter starting the op eration, the attenuation is disc o ntinued and
ret urn ed to ATT level by the sa me cycle.
(4) W hen the input data at e ach c hannel i s c ontinuou sly zeros fo r 8 192 LRCK c ycle s , DZF pin of e ac h c hannel go e s to
“H”. DZF pin immediately goes to “L” if inp ut data are not zer o after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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System Reset
Th e AK4387 should be reset once by bringin g RSTN pin = “L” upon power-up. Th e AK4387 is power ed up an d the
internal timing starts clo c king by L RC K “↑” after exiting reset and power down state by MCLK. The AK4387 is in the
power-down mode until MCLK and LRCK are input.
P ower-down
The AK43 87 is placed in t he po wer-do wn mo de b y b ringing RSTN pi n “ L” and the anlog o u tp uts b e c ome V CO M v oltage
(AVDD/2). Figur e 6 shows an exa mple of th e system t iming at the power-down an d power-up.
N or ma l Op er ati o n
Internal
State
RSTN
Power-down Nor m al Operation
GD GD
“0” dat a
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCL K , LR CK, BI CK
(1) (3)
(6)
DZF
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group dela y (GD).
(2 ) Ana log ou tputs are VC OM voltage ( AVDD/2) a t the power-down mode.
(3) Click noise occurs at the edge of RSTN signal. T his noise is output even if “0” data is input.
(4) The externa l clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTN pin = “L”).
(5) Please mute the analog output externally if the click n oise (3) influ ences system application.
The timing example is shown in this fi gure.
(6) DZF pin is “L” in th e power-down mode (RSTN pin = “L”).
Figure 6. Power-down/up Sequence Example
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Res e t Func ti on
When RSTN bit = 0, DAC is powered down but the internal register values ar e not initialized. The analog outputs go to
VCOM voltage and DZF pins go to “H”. Figure 7 shows the example of reset by RST N bit.
Internal
State
RSTN bit
Di gital Bloc k Powe r-down Normal Operation
GD GD
“0” dat a
D/A O ut
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZF
(3) (1)
(2)
Normal Oper ation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group dela y (GD).
(2 ) Analog outputs go to VCOM voltage (AVDD/2).
(3) Click noise o ccurs at the edges(“↑ ↓”) of the internal timing of RS TN bit. This noise is output ev en if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN pin = “L”).
(5 ) DZF pins go to “H” when the RSTN bit becom es “0”, and go to “L” a t 2/fs after RSTN bit becomes “1”.
(6) T here is a delay, 3~4/fs from RSTN bit “0” to the in tern al RSTN bit “0”, and 2~ 3 /fs from RSTN bit “1” to the
intern al RSTN bit “1”.
Figure 7. Reset Sequence Example
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Mode Control Interface
Internal registers may be written by 3-w ire µP interf ace pins, CSN, CCLK and CDTI. The data on this interface co nsists
of Chip Address (2bi ts, C1/0; fixed to “01”), Read/Wr it e (1bit; fixed to “1”, Write on ly), Register Addr ess (MSB fir st,
5bits) and Control Data (MSB f irst, 8b its). AK 43 87 latche s the data on the rising edge o f CCL K , so data should c lo c ke d
in on the falling edge. The writin g of data becomes valid by CSN “↑”. Th e clock speed of CCLK is 5MHz (max).
RSTN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the
registers are not initi aliz ed.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7
1
2
3
4R/WC0
0D0D1D2D3
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*The AK4387 does not suppor t the read comma nd and ch ip address. C1/0 an d R/W are fixed to “011”
*W hen the AK4 387 is in the p o wer do wn mod e (RSTN pin = “ L ”) o r the MCLK is not pro vided, w riting into the c o ntrol
register is inhibited.
Regi ster Ma p
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
01H Control 2 DZFE 1 0 DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 0 0 INVL INVR DZFB 0 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Notes:
For addresses from 0 5H to 1FH, data must not be written.
When RSTN pin goes “L”, the registers are initialized to their d efault values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All da ta can be written t o the register even if PW or RSTN bit is “0”.
The “0” register should be written “0”, the “1” r egister should be written “1” d ata.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
default 1 0 0 0 1 0 1 1
RST N: Internal timing r eset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK f requency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down contr ol
0: Power down. All registers are n ot initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Settin g Mode
1: E nable, Auto Setti n g Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0” , DFS1-0 set the sampling speed mode.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 DZFE 1 0 DFS1 DFS0 DEM1 DEM0 SMUTE
default 0 0 0 0 0 0 1 0
SMUTE: Soft Mute Ena bl e
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Tabl e 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Sp eed Mode and Quad Speed Mode, some click noise
occurs .
DZFE : Da t a Zer o Detect Enabl e
0: Disabl e
1: Enable
Zero dete ct function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 INVL INVR DZFB 0 0
default 0 0 0 0 0 0 0 0
DZFB: Inver ting Enable of DZF
0: DZF goes “H” at Zero Detecti on
1: DZF goes “L” at Zero Detection
INVR: In vert in g Lch Output Polarit y
0: Normal Output
1: Inverted Output
INVL: In ver tin g Rch Output Polar it y
0: Normal Output
1: Inverted Output
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
default 1 1 1 1 1 1 1 1
ATT = 20 log
10 (ATT_DATA / 255) [dB]
00H: Mute
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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SYSTEM DESIGN
F igure 9 and 10 show the syste m c o nnectio n diagram. An ev aluatio n bo ard (A KD4387) is ava ilable in o rder to allow an
easy study on the layout of a s urrounding circu it.
MCLK
1
BICK
2
SDTI
3
LRCK
4
RSTN 5
CSN 6
CCLK
7
CDTI 8
DZF 16
DVDD 15
AVDD 14
VSS 13
VCOM 12
AOUTL 11
A
OUTR 10
NC 9
Master Clock
Mode
Setting
AK4387
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Rch Out
Lch Out
Analog Ground Digital Ground
Analog
Supply 5V
+
10u
Optional External
Mute Circ uits
0.1u
10
Figure 9. Typical Connection Diagram (Example 1)
MCLK
1
BICK
2
SDTI
3
LRCK
4
RSTN 5
CSN 6
CCLK
7
CDTI 8
DZF 16
DVDD 15
AVDD 14
VSS 13
VCOM 12
AOUTL 11
A
OUTR 10
NC 9
Master Clock
Mode
Setting
AK4387
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Rch Out
Lch Out
Analog Ground Digital Ground
Analog
Supply 5V
+
10u
Optional External
Mute Circ uits
Figure 10. Typical Connection Diagram (Example 2)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins should not be left floatin g.
- T HD+ N val ue a t 19 2k Hz decr eas es by ar ou nd 3dB when u si n g E x a m pl e 2.
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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1. Grounding a nd Power Supply Decoupling
AVDD, DVDD and VSS are supplied from ana log su pply a nd should be sepa rated from system digital supply.
Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to AVDD, DVDD
as possible. The differential Vol tage between AVDD and VSS pins set the analog output range.
2. Anal og Outputs
The analog outputs are single-ended and centered a round the VCOM voltage. The output s ignal range is typically
2.95Vpp (typ@AVDD=5V). The phase o f the analog o utputs can be inverted channel independently by INVL/INVR b its.
The internal switched-capacitor filter a nd continuous-time fi lter attenuate the n oise gener ated by the delta-sigma
modula tor beyond the audio passband. The output volta ge is a positive full scale for 7FF FFFH (@24bit) and a negative
full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit ).
DC offsets on analog outputs are eliminated b y AC coupling since analog outputs have DC offsets of VCOM + a few mV.
Figure 11 shows an example of the ext ernal LPF with 2Vrms outp ut.
390p
3.3k
3.0k 3.9k
470p
+Vop
3.3k
-Vop
AOUT 22u
fc=108.6kHz, Q=0.706, g=-0.08dB at 40kHz
Analog
Out
22k
Figure 11. External 2nd ord er LP F Ci r c ui t Ex a m p l e (us ing op- a m p with du a l power su pp lies)
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
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PACKAGE
0-10°
Detail A
Seating Plane 0.10
0.17
±
0.050.22±0.1 0.65
*5.0±0.1 1.05±0.05
A
18
916
16
p
in TSSO P
(
Unit: mm
)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK4 387]
MS0429-E-00 2005/09
- 21 -
MARKING
AKM
4387ET
XXYYY
1) Pin #1 indication
2) Da te Code : XXYYY ( 5 dig i ts)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4387E T
4) Asahi Kasei Logo
Revisi on History
Date (YY/MM/DD) Revision Reason Page Contents
05/09/30 00 First Edition
I MP ORT A NT NO TI CE
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any such use, ex cept with the express written consent of the Representativ e Director of AKM. As
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to result, whether directly or i ndirectl y, in the loss of the saf ety or ef fectiv eness of the device
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