TOSHIBA TMP8255A PROGRAMMABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable input/output interface with three 8-bit I/O ports. 24 J/O ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is capable of versatile interface between MPU and peripheral devices. (1) 5V+5% Single power supply (2) 24 programmable I/O ports (3) Three operation modes (Mode 0, Mode 1, Mode 2) (4) Bit set/reset capability 2. PIN CONNECTIONS (TOP VIEW) PA30 1 ~ 40 DPAg PA2T 2 39 2 PAs PA, 03 38 D PAg PAg U4 37 D2 PAz RDQ5 36 DWR cso6 35 D RESET (GND) Vss 07 34 Do AiZ8 33 DD, Aol 9 32 DD2 PC70 10 31 D3 Ped 11 30 [D4 PCs 12 29 Ds PCa J 13 28 Dg PCo A 14 27 DD, Pc, 415 26 DP Vcc (+5V) PC2 0 16 25 0 PB7 Pc30 17 24 0 PBe PBoT 18 23 PBs PB,Q 19 22 OPBa PB2 J 20 21 DPB3 TMP8255AP-5 MPU85-128TOSHIBA 3. BLOCK DIAGRAM asa AY RESET TMP8255A D7~Do BIDIRECTIONAL DATA -d >d q READ WRITE CONTROL LOGIC | DATA BUS BUFFER Sy | | GROUPA GROUP B CONTROL CONTROL INTERNAL 8-BIT BUS GROUPA GROUP B PORT A |PORTC PORT C [PORT B 1/0 1/0 PA7y~PAg PC7~PCq 1/0 1/0 PC3~PCo PB7~PBo MPU85-129TOSHIBA TMP8255A 4. PIN NAMES AND PIN FUNCTIONS Input/Output Pin Name Number P P Function of Pin 3-state VO 3-state bidirectional 8-bit data bus. Do~D7 8 3-STATE Used for data transfer with MPU. Also, used for transfer of control words to PPI and status information from PPI. VO 3-state 8-bit I/O Port A. PA7~PAg 8 3-STATE Operation mode and input/output configuration are defined by software. Port A contains the output latch buffer and input latch. VO 3-state 8-bit I/O Port B. PB7~PBo 8 3-STATE Operation mode and input/output configuration are defined by software. Port B contains the output latch buffer and input latch. 3-state 8-bit 1/O Port C. Operation mode and input/output configuration are defined by PC>~PC 8 VO software. Port C can be divided into two 4-bit ports by the mode ? 0 3-STATE control and also, used as the control signal for Port A and Port B. In this case, 3 bits of PCg to PC2 are used for Port B and 5 bits of PC3 to PC7 for Port A. Chip select input. 6s 1 Input When this terminal is at "L" level, data transfer PP] and MPU P becomes possible. At "H" level, the data bus is placed in the high impedance state and control from the processor is ignored. Read signal. RD 1 Input When this terminal is at L level, data that is input into the port is transferred to MPU. Write signal. WR 1 Input When this terminal is at "L" level, data or control word is written into PPI from MPU. Ao, A 2 Input Used for selecting Port A, B, C and the control registers. Nurmally, Oo 1 P this terminal is connected to low order 2 bits of the address bus. When this terminal is at "H" level, all internal registers including the RESET 1 Input control register are cleared. In addition, all ports (Port A, B, C) are placed in the input mode (high impedance) of mode 0. Power Vv 1 ce Supply ov Power Vv 4 N 55 Supply GND MPU85-130TOSHIBA TMP8255A 5.1 FUNCTIONAL DESCRIPTION The PPI is a programmable peripheral interface with three 8-bit ports (Port A, B and C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes "1", the control registers are reset and all I/O ports are placed in input mode (high impedance status) . Table 5.1 Basic Operation of TMP8255A Ar | Ao | CS | RD | WR Function 0 0 0 0 1 Data bus < Porta 0 1 0 0 1 Data bus < PortB 1 0 0 0 1 Data bus Portc 0 0 0 1 0 PortA < Data bus 0 1 0 1 0 Port B < Data bus 1 0 0 1 0 Port C < Data bus 1 1 0 1 0 Control register < Data bus x x 1 x x Data bus = 3-state x x 0 1 1 Data bus = 3-state 1 1 0 0 1 inhibition of combination MODE SELECTION There are three basic modes of operation that can be selected by control words. Mode 0-Basic I/O (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word from the MPU. If D7 is set to "1" in writing a control word into the PPI, on operation mode is selected, while of D7="0", the set/reset function for Port C is selected. MPU85-131TOSHIBA TMP8255A 5.1.1 Control word to define operation mode Figure 5.1 shows the control words to define operation mode of the TMP8255A. Control Word 1 Group A Condtol Group B Control D7 De | Ds | Dg | D3 D2 | Dy | Do LJ input/output selection of low order + bits of Port C O' = Output 1 = Input input/output selection of PortB O' = Output 1' = Input Mode selection of Group B O'=ModeO 1 =Mode 1 Input/output selection of high order 4 bits of Port C O' = Output 1 =Input input/output selection of PortA O' = Output T' =Input Mode Selection Group A O' = Mode 0 D6 DS 00=Mode 0 1 = Designation of mode set flag 1 : = Mose x: Don't care Figure 5.1 Control Word for Mode Selection MPU85-132TOSHIBA TMP8255A 5.1.2 Port C bit set/reset control word Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Figure 5.2 shows the Port C bit set/reset control word. Control Word | 7 | ds [| ds | ds | ds | 2 | or | do | Bit set/reset selection Don't care "0" =Reset "1" =Set orem o fo fo [rs 0 0 1 PCy 0 1 0 PC2 0 1 1 PC3 Bit selection 1 0 0 PC4 1 0 1 PCs 1 1 0 PC5 1 1 1 PC7 Figure 5.2 Control Word for Bit Set/Reset 5.2. OPERATION MODES 5.2.1 Mode 0 (Basic I/O) This functional configuration is used for simple input or output operations. No handshaking is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 I/O ports are divided into four groups of Port A (8 BITS), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4), 3 (D3), 1 (D1) and 0 (Dg) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-133TOSHIBA TMP8255A Node Setting Control Word Port A PortC Port B Portc Da D3 Di Do (PC7~PCa) (PC3~PCo) 0 0 0 0 Out Out Out Out 0 0 0 1 Out Out Out In 0 0 1 0 Out Out In Out 0 0 1 1 Out Out In In 0 1 0 0 Out In Out Out 0 1 0 1 Out In Out In 0 1 1 0 Out In In Out 0 1 1 1 Out In In in 1 0 0 0 In Out Out Out 1 0 0 1 in Out Out In 1 0 1 0 tn Out In Out 1 0 1 1 In Out In in 1 1 0 0 In in Out Out 1 1 0 1 In In Out In 1 1 1 0 in in In Out 1 1 1 1 In In In in Figure 5.3 Port definition in Mode 0 5.2.2 Mode 1 (Strobe I/O) In Mode 1, input/output of port data is performed in conjunction with the strobe signals or handshaking signals. Port C is used to control Port A or Port B. The basic operatings in Mode 1 are as follows: e Mode 1 can be set for two groups of Group A and Group B. e Each group consist of 8-bit data port and 4-bit control/data port. The 8-bit data port can be set as input or output port. e The control/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode 1: e STB (Strobe Input) At "0", input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. e IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to"1". IBF is set ("1") by STB input being reset and is reset ("0") by the rising edge of RD input. MPU85-134TOSHIBA TMP8255A e INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at "0" if INTE (INTE flag) in the PPI is in the enabled state ("1") , IBF is set to"1". INTR is set to "1" immediately after the rising edge of this STB input and reset to "0" by the falling edge of RD input. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PC4 INTEB-Control by bit set/reset of PCa (2) When used as the output port in Mode 1: e OBF (Output Buffer Full F/F Output) This is a flag which shows that MPU has written data into a specified port. OBF is set to becomes "0" at the rising edge of WR signal and is set to "1" at the falling edge of ACK (Acknowledge input) signal. e ACK (Acknowledge Input) ACK signal is sent to the PP1 as a response from a peripheral device that received data from the port. INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to "1" and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to "1" and INTR signal becomes "1" immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PC MPU85-135TOSHIBA TMP8255A MODE 1 (PORT A) CONTROL WORD eB D7 Dg Ds Dg D3 D2 Dy Do ~e~ STBA > IBFA TE 7 BN PCg, PC7 __ L INTRA _f TT 1 QO = OUTPUT RD >ag 2 iBF 1 = INPUT PCg~ PCy 41/0 /o MODE 1 (PORT B) INTR i \ 7 CONTROL WORD <8 RD OO T7 / ,. Dy Dg Ds Dg D3 D2 Dy Dg < STRB PONT \ Ailes Pere || FON x Dy~Dp em ene nme ee 4 Re ee ee - | irae D7 <> RD +a Figure 5.4 Example of Strobe Input in Mode 1 MODE 1 {PORT A) CONTROL WORD PAz ~ PAg bex D7 Dg Ds Da D3 Dz Dy Do t OBFA < ACKA PCa, PCs _ [> INTRA O= OUTPUT WRa 1 = INPUT PCa~ PCs beet /0 MODE 1 (PORT B) CONTROL WORD PB7~ PBy [8 Dy Dg Ds Da D3 Dz Dy Do | OBFB [1 [x] x] x] x] so] x] < ACKE _ | INTRB WRd INTR PORT OUTPUT Figure 5.5 Example of Strobe Output in Mode 1 MPU85-136TOSHIBA TMP8255A PAy ~ PA bom PAy~ PAg o WwRd PCy |-> OBFA RD >< PC, |< STBA CONTROL WORD PCg |<* ACKA CONTROL WORD PCs > IBFA D7 Dg Ds Dg Dz Dz 01 Do . PC3 > INTRA D7 De Ds Dg D3 Dz Di Dp PC3 | INTRA [1 Tos Jo [vols fs |x| [1 To [4] 3 [vols To] x | 2 PCy ~ PCs KE 1/0 PCg ~ PCy 1/0 8 8 PCa, PCs PB7 ~ PBo PC5, PCy PBy ~ PBy PO O= OUTPUT) =__ O= OUTPUT = __ 1 = INPUT RD PC) j+ STBB 1 = INPUT WR-->G PC, |->> OBFB pc, b> IBFB PC, |< ACKB PCy > INTRB PCy }-> INTRB PORT A (STROBE OUTPUT) PORT A (STROBE INPUT) PORT B (STROBE INPUT) PORT B (STROBE OUTPUT) Figure 5.6 Example of Port A output, Figure 5.7. Example of Port A Input, Port B Input in Mode 1 Port B Output in Mode 1 5.2.3 Mode 2 (Strobed Bidirectional Bus 1/O) In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. These are 5 control signals as follows when Group A is used in Mode 2. e OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to "0" to inform a peripheral device that the PPI is ready to output data. However, Port A is dept in the floating (high impedance) state until ACK input signal is received. e ACK (Acknowledge Input) When ACK signal is set to "0", the data of the 3-state output buffer of Port A is send out. If ACK signal is at "1", Port A is in the high impedance state. e STB (Strobe Input) When STB input is set to "0", the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Dg) . MPU85-137TOSHIBA TMP8255A e IBF (Input Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to "1". e INTR (Interrupt Request Output) INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input. INTE 1- Used to generate INTR signal in conjunction with OBF and ACK signals, and is controlled by PCg bit set/reset. INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals, and is controlled by PC4 bit set/reset. Figure 5.8 shows the operating example and the timing diagram in Mode 2. INTRA OBF ACKA AK Of \\ Zl YO PORTA wanna aml RD \ f al Figure 5.8 Operating example in Mode 2 MPU85-138TOSHIBA TMP8255A Control Word in Mode 2 D7 De Ds Da D3 D2 Dy Do i 1 [1 |x | x | x | 10 | w | 1. | PC2~PCo 0 =Output x =Dont care 1 =Input Port 8 0 = Output 1=Input Group B mode 0 =Mode 0 1=Mode 1 Figure 5.9 Control Word and Configuration in Mode 2 Control Words PC3 3 INTRA PA7~PAg |j~~> D7 D Ds Da D3 D2 Dy Do 7~PAo su PC7 [> OBFA [1 [+] |x |x | o [1 | wo |] 7 PCg [* ACKA PC2~PCo _ __] PC |~ STBA 0 = Output PCs > IBEA 1 = Input 3 RDB -| PC2~PCo 37 1/0 wR -> PB7~PBo |~~ Port A - Mode 21/0 Port B - Mode 0 Input PC3 -> INTRA PA7~PAo a PC7 |-> OBFA Li tatxtxtxfitot x] oy oe PCg j~*- ACKA PCa4 |* STBA PCs [> IBFA PB7~PBg Po >| PC; |}> OBFB | PC2 |~< ACKB PCo >> _INTRB Control Words Z| 2 Port A - Mode 2 I/O Port B - Mode 1 Output Figure 5.10 Example in Combination with Mode 2 and Other Mode MPU85-139TOSHIBA TMP8255A 5.2.4 Pecautions for use in Mode 1 and 2 When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follows. If programmed as the input, they are accessed by normal Port C read. If Programmed as the output, high order bits of Port C (PC7-PC4) are accessed using the bit set/reset function. As to low order bits of Port C (PC3-PCo), in additions ot access by the bit set/reset function, 3 bits only can be accessed by normal writing. 5.3. READING PORT C STATUS When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 5.2 Status Word Format of Port C Data Mode D7 De Ds Da D3 D2 Dy Do Mode 1 Input 1/0 1/0 IBFA INTEA INTRA INTEB IBFB iINTRB Mode 1 Output | OBFA | INTEA 1/0 1/0 INTRA | INTEB OBFB | INTRB Mode 2 OBFA INTE1 IBFA INTE2 INTRA By Group B Mode MPU85-140TOSHIBA TMP8255A 6. ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Symbol Item Rating Unit Vec Supply Voltage -0.5to 7.0 Vv VIN Input Voltage -0.5to Vcc +7.0 Vv Pp Power Dissipation 1 Ww TSOLDER | Soldering Temperature (10sec) 260 c Tste Strobe Temperature -65to +150 Cc ToprR Operating Temperature Oto +70 c 6.2. DC ELECTRICAL CHARACTERISTICS TA =0C to 70C, Vcc =5V 45%, Vss =0V SYMBOL ITEM TEST CONDITION MIN. | TYP. | MAX. | UNIT Vit Input Low Voltage -0.5 - 0.8 Vv Vie Input High Voltage 2.2 - Vec Vv Vv Output Low Voltage (DB) lot = 2.5mMA - - 0.45 Vv OL (PER) lo. = 1.7mA - - |o4a5 |] ov Vv Output High Voltage (DB) lon = - 400pA 2.4 - - Vv OH (PER) lou = - 200pA 24] - Vv hie Input Leak Current OS VinS Vee - - +10 pA Output Leak Current I . SV eV. _ _- +1 A OFL (High Impedance State) 05 Vout Vec 0 B (Note 1) : . VexT = 1.5V _ Ibar Darlington Drive Current Rexr = 7502 1.0 40] mA lec Operating Supply Current VO cycle Time 1 - - 120 mA usec Note: Applied for optional 8 I/O terminals in Port B and Port C. MPU85-141TOSHIBA TMP8255A 6.4 AC ELECTRICAL CHARACTREISTICS TA=0C to 70C, VCC =5V + 5%, VSS =0V SYMBOL PARAMETER TM PB APT UNIT MIN. | MAX. tar Address set-up time for RD fall 0 - ns tRA Address hold time for RD rise 0 - ns trr RD pulse width 300 - ns trp Delay from RD fail to decided data output - 200 ns tpr Time from RD rise to data bus floating 10 100 ns trv Time from RD or WR rise to next RD or WR fall 850 _ ns taw Address set-up time for WR fall i) - ns twa Address holding time for WR rise 20 - ns tww WR pulse width 300 - ns tow Bus data set-up time for WR rise 100 - ns two Bus data holding time for WR rise 30 - ns twe Delay from WR rise to decided data output - 350 ns tr Port data set-up time for RD fall 0 - ns tur Port data holding time for RD rise 0 - ns tak ACK pulse width 300 - ns tsr STB pulse width 500 - ns tps Port data set-up time for STB rise 0 - ns tpH Port data holding time for STB rise 180 - ns tad Delay from ACK fall to decided data output - 300 ns tkb Time from ACK rise up to port (Port A in Mode2) floating 20 250 ns twos Delay from WR rise to OBF fall - 650 ns taos Delay from ACK fall to OBF rise - 350 ns tsip Delay from STE fall to IBF rise - 300 ns trip Delay from RD fall to IBF rise - 300 ns tRIT Delay from RD fall to INTR fall - 400 ns tsit Delay from ACK rise to INTR rise - 300 ns taiT Delay from ACK rise to INTR rise - 350 ns twit Delay from WR rise to INTR fall - 450 ns Note: 1. When the power supply is turned ON, reset pulse duration must be active for at least 500 ns or more. 2. AC Measuring Point Input Voltage Vin =2.0V, Vi,=0.8V Output Voltage VoH=2.0V, VoL=0.8V CL=150pF. MPU85-142TOSHIBA TMP8255A 6.4 CAPACITANCE TA =25C, Vcc =Vss5 =0V SYMBOL ITEM TEST CONDITION MIN. TYP. | MAX. | UNIT CIN Input Capacitance fo = 1MHz - 7 10 pF Cvo I/O Capacitance (*) - - 20 pF *:; All terminals except that to be measured should be earthed. MPU85-143TOSHIBA TMP8255A 7. TIMING DIAGRAM MODE 0 INPUT OPERATION INPUT CS, Ai, Ao D7~Dg - ee meer eee MODE 0 OUTPUT OPERATION MODE 1 INPUT OPERATION tps tery INPUT PORT DATA tst > STB f . (BF -<tsIT ~<- trip INTR | ) a RD aa tre a Figure 7.1 Timing diagram MPU85-144TOSHIBA TMP8255A WR INTR OUTPUT PORT DATA OQ QI al > oO A PERIPHERAL BUS WV MODE 1 OUTPUT OPERATION MODE 2 tww BIDIRECTION OPERATION tww Figure 7.2 Timing diagram MPU85-145TOSHIBA TMP8255A 8. PACKAGE DIMENSION 8.1 PLASTIC PACKGE DIP40-P-600 Unit : mm 40 2\ MoO om 13.440.2 TO ODOT OSS L 50.70.2 |.22TYP Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical positions with respect to No.1 and No.40 leads. MPU85-146