Enpirion® Power Evaluation Board User Guide
EN5337QI
Enpirion EN5337QI 3A DCDC Converter w/Integrated Inductor
Evaluation Board
Introduction
Thank you for c hoos ing Alter a Enpir ion power produc ts !
• The EN5337QI features integrated inductor, power MOSFETS, Controller,
a bulk of the c om pens ation Netw ork, and protec tion c ir c uitry agains t
system faults. This level of integration delivers a substantial reduction in
footprint and part count over competing solutions. However, the evaluation
board is not optim iz ed for m inim um footprint; rather for engineer ing eas e
of evaluation through pr ogram m ing options , c lip leads , tes t points etc .
• The EN5337QI features a customer programmable output voltage by
means of a resistor divider. The res is tor divider allow s the us er to s et the
output voltage to any value w ithin the r ange 0.75V t o ( VIN-VDROPOUT). The
evaluation board, as shipped is populated with a 4 resistor divider option.
The upper resistor is fixed (150kΩ) and has a phas e lead c apac itor (27pF)
in parallel. O ne of 4 low er res is tor s is s elec ted with the jum per option for
output voltages of 1.0V, 1.2V, 1.55V and 2.5V. To c hange any of the
output voltages , r etain the upper res is tor and c apac itor values and c hange
only the low er r es is tor.
• This devic e has no over -voltage protection feature. We strongly
rec om m end the c us tom er to ens ure the feedbac k loop is truly c los ed
before pow ering up the devic e es pec ially if the load c an not w iths tand the
input voltage.
• The input capacitor is a 10V rated 22uF X5R MLCC . The output filter
section is populated with 1 x 47uF and 1 x10uF, 6.3V rated X5R MLC
capacitors to ac hieve the required ~ 50uF of output c apac itanc e. This
c om bination of output c aps yields very low ESR and henc e low output
ripple. A s ingle 47uF c apac itor m ay be s ubs tituted if m inim iz ing footpr int
is important. The Soft-s tart c apac itor is a s m all 10V r ated 15nF X5R
MLCC.
• Pads are available to add an additional input c apac itor , and there are a
total of 5 pads to ac c om m odate the output c apac itor(s ). This allow s for
evaluation of perform anc e over a wide range of input/output c apac itor
combinations.
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Enpirion® Power Evaluation Board User Guide
EN5337QI
• Clip on term inals are provided for ENA, S S, P OK, VIN and VO UT. O ther
test points ar e als o m ade available.
• A jum per is provided for controlling the Enable signal. Enable m ay als o be
c ontr olled us ing an external switching s ourc e by rem oving the jum per and
applying the enable s ignal to the m iddle pin and gr ound.
• A jum per is als o pr ovided to c onnec t a res is tor load to PO K pin. This
jum per is es pec ially us eful to m eas ure the dis able c ur rent and elim inates
having to s ubtrac t the c urrent draw n by the PO K res is tor .
• Foot print is also provided for a SMA connector to SYNC input. The SYN C
input allows the devic e switching to be phas e loc ked to an exter nal c loc k
s ignal. This external c loc k s ync hroniz ation allow s for m oving any offending
beat frequenc y to be m oved out-of-band. A s w ept fr equenc y applied to this
pin res ults in s pread s pec tr um operation and reduces the peaks in the
nois e s pec tr um of em itted EMI.
• Num erous tes t points ar e provided as well as banana plugs for input and
output connections. Input / O utput r ipple are bes t m eas ured directly across
the appropriate capacitors. The s w itc hing w aveform m ay be view ed
between test points labeled SW and G ND.
• The board c om es w ith input dec oupling and revers e polar ity protec tion to
guard the devic e agains t c om m on s etup m is haps .
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Enpirion® Power Evaluation Board User Guide
EN5337QI
Quick Start Guide
of th e
Fi gure 1 shows a top view e va l uati on boa rd.
WARNING: c om plete s teps 1 through 4 befor e applying power to the
EN5337QI evaluation board.
STEP 1: Set the “ENAB LE” jum per to the D is able Pos ition.
Fi gure 2: Shows P OK & Enable Jum pers
(P OK jum per as show n conne cts pul l -up resi stor to V I N.
Enable j umper shown in DIS ABLE position. )
STEP 2: Connec t Power Supply to the input pow er c onnec tors , VIN (+) and
GND (-) as indic ated in Figure 1 and s et the s upply to the des ired voltage. The
devic e dis able c urrent m ay be m eas ured in this c onfiguration.
CAUTION: be m indful of the polar ity. Even though the evaluation board
c om es w ith revers e polar ity protec tion diodes , it is rarely a good idea to
revers e the input polar ity.
Disable
Position
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Enpirion® Power Evaluation Board User Guide
EN5337QI
STEP 3: C onnec t the load to the output c onnec tors VO UT ( +) and GND (-), as
indicated in Figure 1.
STEP 4: S elec t the output voltage s etting jum per. Y ou may also set the POK
jum per to inc lude the PO K load if PO K s ignal monitoring is intended. The only
tim e to dis able PO K is w hen m eas uring the abs olute D is able c urr ent.
Fi gure 3: Output Vol tage se l ecti on jum pers
Jumper shown sel e cts 1.2V output
(Jumper posi tions from l eft are: 2. 5V, 1.55V , 1. 0V an d 1. 2V)
STEP 5: Apply VIN to the board and m ove the ENABLE jum per to the enabled
position. The EN5337QI is now powered up! Various measurements such as
effic ienc y, line and load r egulation, input / output ripple, load transient, drop-out
voltage measurements may be made at this point. The over c urrent trip level,
short circuit protection, under voltage lock out thresholds, temperature coefficient
of the output voltage m ay als o be m eas ured in this c onfigur ation.
STEP 5A: Power Up/Dow n Behavior – Rem ove ENA jum per and c onnec t a
pulse generator (output disabled) signal to the middle pin of ENA and Ground.
Set the puls e am plitude to swing fr om 0 to 2.5 volts. Set the puls e per iod to
10ms ec . and duty c yc le to 50%. Hook up os c illos c ope probes to E NA, SS, POK
and VO UT w ith c lean ground r eturns . Apply power to evaluation board. Enable
pulse generator output. Observe the SS capacitor and VOUT voltage ramps as
ENA goes high and again as ENA goes low . The devic e when powered down
ramps dow n the output voltage in a c ontrolled m anner before fully s hutting dow n.
The output voltage level w hen PO K is as s erted /de-as s er ted as the devic e is
powered up / down m ay be obs erved as w ell as the c lean output voltage ram p
and POK signals.
Fi gure 4: Me ans to Pul se Enable
STEP 6: External Clock Synchroniza tion / Spread Spec trum Modes : In order
to ac tivate this m ode, it m ay be nec es s ary to a s older a SMA c onnec tor at J8.
GND
Ext. Enable
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Enpirion® Power Evaluation Board User Guide
EN5337QI
Alternately the input cloc k s ignal leads m ay be direc tly s oldered to the through
holes of J8 as shown below.
Fi gure 4: SMA Connector for Externa l Cl ock Input
Power dow n the devic e. Move ENA into dis able pos ition. C onnec t the c loc k
s ignal as jus t indic ated. The c loc k s ignal s hould be c lean and have a frequency in
the range of 4.5 to 5.5MHz ; am plitude 0 to 2.5 volts w ith a duty c yc le betw een 20
and 80%.
With SYNC s ignal dis abled, power up the devic e and m ove ENA jumper to
Enabled pos ition. The devic e is now pow ered up and outputting the des ired
voltage. The devic e is s witc hing at its free running frequenc y. The s witc hing
wavefor m m ay be obs erved betw een tes t points SW and GND . Now enabling the
SYNC s ignal will autom atic ally phas e loc k the internal s w itc hing fr equenc y to the
externally applied frequency as long as the external clock parameters are within
the s pec ified range. To obs erve phas e-loc k c onnec t os c illos c ope pr obes to the
input clock as well as to the SW test point. P has e loc k range c an be deter m ined
by s weeping the external c loc k frequenc y up / dow n until the devic e jus t goes out
of loc k at the tw o extr em es of its range.
For s pread s pec trum operation the input c loc k frequenc y m ay be s wept betw een
tw o frequenc ies that are w ithin the loc k range. The s w eep (jitter) repetition rate
s hould be lim ited to 10kHz. The r adiated E MI s pec trum m ay be now m eas ured in
various states – fr ee running, phas e loc ked to a fixed fr equenc y and s pr ead
spectrum.
GND
Ext. Clock
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Enpirion® Power Evaluation Board User Guide
EN5337QI
Figure 5: EN5337 Evaluati o n Boar d S ch emati c
Output Voltage Select
Programming the Output Voltage.
The EN5337QI output voltage is programmed using a simple resistor divider
network. Figure 6 shows a schematic view of the resistor divider configuration.
The EN5337QI output voltage is determined by the voltage presented at the XFB
pin. The voltage is set by way of a resistor divider betw een VOUT and AGND w ith
the midpoint going to XFB. A phase lead capacitor is also required across the
upper resistor – the one between VOUT and XFB.
R2
C10
TP4
1
C11
J1
1
2
3
J10
1
2
3
R4
TP5
0805
TP3
TP2
J11
1
2
J12
1
2
C9
C12
0402
TP17
TP18
TP17 & TP18 are
used for special
testing. They are
not labeled on PCB.
PVIN FB1
R3
GND OUT GND IN
C13
TP12
R6
TP15
J2
1
2
J3
1
2
TP6
TP7
TP13
TP14
J9
1
3
5
2
4
6
87
POK
AVIN
ENA
TP8
TP9
TP10
TP11
TP16
POK
ENA
SS
VOUT
VIN
U2 D1
+
C1
PVIN
VOUT
Add short across R6
when all other
routing is completed
C16 J13
1
2
C17
J14
1
2
R1
R5
R7
J4
C6
C7
XFB
EAOUT
XFB EAOUT
U1
EN5337Q
NC(SW)
1
NC(SW)
2
NC3
3
NC4
4
VOUT
5
VOUT
6
VOUT
7
VOUT
8
VOUT
9
VOUT
10
VOUT
11
NC(SW)
12
PGND
13
PGND
14
PGND
15
PGND
16
PGND
17
PGND
18
VIN
19
PGND 25
VDDB 24
BTMP 23
PG 22
VIN 21
VIN 20
NC(SW) 38
NC(SW) 37
NC(SW) 36
NC(SW) 35
NC(SW) 34
AVIN 33
AGND 32
XFB 31
SS 30
EAOUT 29
POK 28
ENA 27
SYNC 26
C5
R8 C14
J6
C15
C4
SW
0805
0805
0805
0805
0805
0805
0805
0805
0805
J5
1206/0805
J7
0805
1206/0805
1206
1206
C2
C3
C8
SYNC
1206/0805
1206/0805
1206/0805
TP1
0402
J8
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Enpirion® Power Evaluation Board User Guide
EN5337QI
XFB
CSS
VOUT
POK
PGNDAGND
SS
PVIN
AVIN
V
OUT
V
IN
22µF~50uF
R
B
R
A
C
A
Fi gure 6: VOUT resistor divider ne tw ork and Phase lead Details.
R A =150kΩ, CA = 27pF
)75.0( *75.0 VVOUT RAV
RB −
=
Test Recommend atio ns
Recommendations
To guarantee m eas ur em ent ac c urac y, the follow ing prec autions s hould be
observed:
1. Make all input and output voltage m eas urem ents at the board us ing the
tes t points pr ovided. This w ill elim inate voltage drop ac ros s the line and
load c ables that c an produc e fals e r eadings .
2. Meas ure input and output c ur rent w ith s eries am m eter s or ac c urate
shunt resistors. This is especially important when m eas uring effic ienc y.
3. Use a balanced impedance probe tip s how n below to m eas ure
s witc hing s ignals and input / output ripple to avoid noise coupling into
the probe gr ound lead. Input ripple, output ripple, and load trans ient
deviation are best measured at the res pec tive input / output c apac itors .
4. The board inc ludes a pull-up resistor for the POK signal and ready to
m onitor the power O K s tatus . The PO K s ignal m ay be viewed at c lip
lead m arked PO K.
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Enpirion® Power Evaluation Board User Guide
EN5337QI
5. A 15nF s oft-start capacitor is populated on the board for ~1msec soft-
sta rt time.
6. The over-current protection circuit typically limits the maximum load
c urrent to approxim ately 1.5X the rated value – nominally 4.5A.
Input and Output Capacitors
The input c apac itanc e r equirem ent is between 10-20uF X5R/X7R for the
EN5337QI. Altera rec om m ends that a low ESR MLC c apac itor be us ed. The
voltage r ating s hould be rated high enough to provide adequate m ar gin for your
application. There is a pre-tinned pad for one additional 1206 c apac itor to
experim ent w ith input filter perform anc e.
The output capacitance requirement is approximately 50uF of X5R/X7R
c apac itanc e. The EN5337QI-E evaluation board comes populated with 1 x 47uF
1206 and 1 x 10uF 0805, 6.3V MLC c apac itors . The 2 parallel capacitors provide
reduced ESR and hence lower output ripple v oltage. If a minimum footprint
configuration is desired, a single 47uF MLC capacitor can be used.
NOTE: Pleas e refer to produc t datas heet for s pec ific rec ommendations.
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Enpirion® Power Evaluation Board User Guide
EN5337QI
Contact Information
Altera Corporation
101 Innovation Drive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com/
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