FIN1108TMTD(Preliminary) - Fairchild Semiconductor

March 2002

Revised May 2003

FIN1108 • FIN1108T (Preliminary) LVDS 8 Port High Speed Repeater

FIN1108 • FIN1108T (Preliminary)

LVDS 8 Port High Speed Repeater

General Description

This 8 port repeater is designed for high speed intercon-

nects utilizing Low Voltage Differential Signaling (LVDS)

technology.

The FIN 11 08 acce pts and outputs LVDS le vels w ith a ty pi-

cal differen tial outp ut swing of 330 mV which p rovides low

EMI at ultra low power dissipation even at high frequen-

cies. The FIN1108 provides a VBB reference for AC cou-

pling on the inputs. In addition the FIN1108 can directly

accept LVPECL, HSTL, and SSTL-2 for translation to

LVDS.

The FIN1108T has inte rnal term ination across the receiver

inputs for reduced part count, reduced stub length and bet-

ter noise immu nity. See Applications section.

Features

■Greater than 800 Mbps data rate

■3.3V power supply operation

■3.5 ps maximum random jitter and 135 ps maximum

deterministic jitter

■Wide rail-to-rail common mode range

■LVDS receiver inputs accept LVPECL, HSTL, and

SSTL-2 directly

■Ultra low power consumption

■20 ps typical channe l -to-c ha nn el skew

■Power off protection

■> 7.5 kV HBM ESD Protection

■Meets or exceeds the TIA/EIA-644-A LVDS standard

■Available in space saving 48-lead TSSOP package

■Open circuit fail safe protection

■VBB reference output

■FIN1 108T (RT) features Internal Termination Resistors

Ordering Code:

Devices also available in Tape and Reel. S pecify by ap pending su ffix letter “X ” to th e ordering co de.

Order Number Package Number Package Description

FIN1108MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

FIN1108TMTD

(Preliminary) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

FIN1108 • FIN1108T (Preliminary)

Pin Descriptions

Function Table

H = HIGH Logi c Level

L = LOW Logic Level

X = Don’t Care

Z = High Impeda nc e

Connection Diagram

Functional Diagram

Pin Name Description

RIN1+, RIN2+,

RIN3+, RIN4+,

RIN5+, RIN6+,

RIN7+, RIN8+

Non-inverting LVDS Input

RIN1−, RIN2−,

RIN3−, RIN4−,

RIN5−, RIN6−,

RIN7−, RIN8−

Inverting LVDS Input

DOUT1+, DOUT2+,

DOUT3+, DOUT4+,

DOUT5+, DOUT6+,

DOUT7+, DOUT8+

Non-inverting Driver Output

DOUT1−, DOUT2−,

DOUT3−, DOUT4−,

DOUT5−, DOUT6−,

DOUT7−, DOUT8−

Inverting Driver Output

EN Driver Enable Pin for All Output

EN12 Inverting Driver Enable Pin for

DOUT1 and DOUT2

EN34 Inverting Driver Enable Pin for

DOUT3 and DOUT4

EN56 Inverting Driver Enable Pin for

DOUT5 and DOUT6

EN78 Inverting Driver Enable Pin for

DOUT7 and DOUT8

VCC Power Supply

GND Ground

VBB Refere nce Voltage Output

Inputs Outputs

EN ENxx DIN+DIN−DOUT+DOUT−

HL HLHL

HL LHLH

H L Fail Safe Case H L

XHXXZZ

LXXXZZ

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FIN1108 • FIN1108T (Preliminary)

Applications

Signal Optim iza tion via Int erna l Terminat io n

For LVDS signaling in point-to-poin t applications, receivers

or repeaters with on-chip termination are preferable to

reduce the overshoot or undershoot due to the reflection

caused by stubs at receiver inputs. As a rule of thumb, usu-

ally the termination resist or for an LVDS receiver shoul d be

placed as close as possible to the receiver, especially for

high speed applications. If the distance between termina-

tion resist ors and recei vers is to o lon g, the in tercon necti on

will be seen as an un-terminated stub which can produce

reflection s resu lting in hi gher EM I. Inte rnal te rmin ation c an

effectively smooth out this ringing which can otherwise

jeopard ize the receiv er noise m argin. Thi s is impor tant for

reliable high-speed operation with tighter required signal

settling times. Below is a list of the ad vantages/disadvan-

tages of internal ter mina tion .

Internal termination is not suitable for all applications. In

order to set a proper VOD at the driver outputs, receivers

with on-chip termination resistors only work for point-to-

point applications since multi-drop applications would

requir e termination res istor for eac h receiver, reducing the

equivalent termination to RT/n. This wou l d redu c e t h e dr iv e r

output swing by n.

Advantages: Disadvantages:

1. Reduced device count resulting in reduced board space

and production cost. 1. Without special process treatment, on-chip termination can

experience greater temperature variation. This is usually

tolerable for low speed applications that have a sufficient

unit interval.

2. Reduced reflections caused by the stub length on the

receiver inputs, improving the signal integrity. 2. For applications with high common-mode noise, a center

tapped capacitor at the receiver side is desirable to filter

out the common-mode voltage noise of the input L VDS sig-

nal. This scheme works for an external termination scheme

with two (50Ω each for nominal 100Ω termination resistor)

half-value termination resistors connected in series and

center tapped to a capacitor to Ground. To implement this

scheme using internal termination resist ors, a center tap

pin would have to be used. This would increase the pack-

age size of the part.

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FIN1108 • FIN1108T (Preliminary)

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings”: are those values beyond which

damage to the device may occur. The databook specifications should be

met, without exception, to ensure that the system design is reliable over its

power supply, temperature and output/input loading variables. Fairchild

does no t re c om m end operation of circuit s o ut s ide data book specif ic ation.

DC Electrical Characteristics

Note 2: All typic al values are at TA = 25°C and with VCC = 3.3 V.

Supply Voltag e (VCC)−0.5V to +4.6V

LVDS DC Input Voltage (VIN)−0.5V to +4.6V

LVDS DC Output Voltage (VOUT)−0.5V to +4.6V

Driver Short Circuit Current (IOSD) Cont inuous 10 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Max Junction Temperature (TJ)150°C

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

ESD (Human Body Model) 7500V

ESD (Machine Model) 400V

Supply Voltag e (VCC) 3.0V to 3.6V

Magnitude of Differential

Vol tage ( |VID|) 100 mV to VCC

Common Mode Voltage

Range (VIC)(0V + |VID|/2) to (VCC − |VID|/2)

Operating Temperature (TA)−40°C to +85°C

Symbol Parameter Test Conditions Min Typ Max Units

(Note 2)

VTH Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, + 1.2V, or VCC − 0.05V 100 mV

VTL Differential Input Threshold LOW See Figure 1; VIC = +0.05V, + 1.2V, or VCC − 0.0 5V −100 mV

VIH Input HIGH Voltage (EN or EN)2.0V

CC V

VIL Input LOW Voltage (EN or EN)GND0.8V

VOD Output Differential Voltage 250 330 450 mV

∆VOD VOD Magnitude Change from 25 mV

Differential LOW-to-HIGH RL = 100 Ω, Driver Enabled,

VOS Offset Voltage See Figure 2 1.125 1.23 1.375 V

∆VOS Offset Magnitude Change from 25 mV

Differential LOW-to-HIGH

IOS Short Circuit Output Current DOUT+ = 0V and DOUT− = 0V, −3.4 −6mA

Driver Enabled

VOD = 0V, Driver Enabled ±3.4 ±6mA

IIN Input Current (EN, EN, DINx+, DINx−)V

IN = 0V to VCC, Other Input = VCC or 0V ±20 µA

(for Differential Inputs)

IOFF Power Off Input or Output Current VCC = 0V, VIN or VOUT = 0V to 3.6V ±20 µA

ICCZ Disabled Power Supply Current Drivers Disabled 20 mA

ICC Power Supply Current Drivers Enabled, Any Valid Input Condition 80 mA

IOZ Disabled Output Leakage Current Driver Disabled, DOUT+ = 0V to 3.6V or ±20 µA

DOUT− = 0V to 3.6V

VIC Common Mode Voltage Range VID/2 VCC − (VID/2) V

CIN Input Capacitance Enable Input 3 pF

LVDS Input 3

COUT Output Capacitance 3pF

VBB Output Reference Voltage VCC = 3.3V, IBB = 0 to −275 µA 1.125 1.2 1.375 V

RTTerminating Resistance 100 Ω

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FIN1108 • FIN1108T (Preliminary)

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 3: All typical values are at TA = 25°C and wit h VCC = 3.3V.

Note 4: tSK(LH), tSK(HL) is the ske w betw ee n spe cified outpu ts of a s ingle de vic e whe n the ou tputs have ident ical lo ads an d are swi tch ing in th e sam e direc-

tion.

Note 5: tSK(PP) is the ma gnitude of t he differen c e in propa gation delay times between an y specified term inals of tw o devi c es s w it c hing in the same direction

(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.

Note 6: Passing criteria for maximum frequency is the output VOD > 250 mV and the duty cycle is better than 45% / 55% with all channels switching.

Note 7: Output loading is transmiss ion line environm ent only; CL is < 1 pF of stray test fixture capacitance.

FIGURE 1. Differ entia l Receiver Voltage Definitions

FIGURE 2. Differential Driver DC Test Circuit

Note A: All LVDS input pulses have freq uency = 10 MHz, tR

or tF < = 0.5 ns

Note B: CL includes all probe and jig capacitances

FIGURE 3. Differential Driver Propagation Delay

and Transition Time Test Circuit

Symbol Parameter Test Conditions Min Typ Max Units

(Note 3)

tPLHD Differential Output Propagation Delay 0.75 1.1 1.75 ns

LOW-to-HIGH

tPHLD Differential Output Propagation Delay 0.75 1.1 1.75 ns

HIGH-to-LOW RL = 100 Ω, CL = 5 pF,

tTLHD Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV, 0.29 0.4 0.58 ns

tTHLD Differential Output Fall Time (80% to 20%) VIC = VID/2 to VCC − (VID/2), 0.29 0.4 0.58 ns

tSK(P) Pulse Skew |tPLH - tPHL| Duty Cycle = 50%, 0.02 0.2 ns

tSK(LH), Channel-to-Channel Skew See Figure 1 and Figure 1 0.02 0.15 ns

tSK(HL) (Note 4) 0.02

tSK(PP) Part-to-Part Skew (Note 5) 0.5 ns

fMAX Maximum Frequency (Note 6)(Note 7) 400 >630 MHz

tPZHD Differential Output Enable Time 35ns

from Z to HIGH

tPZLD Differential Output Enable Time 3.1 5 ns

from Z to LOW RL = 100 Ω, CL = 5 pF,

tPHZD Differential Output Disable Time See Figure 2 and Figure 3 2.2 5 ns

from HIGH to Z

tPLZD Differential Output Disable Time 2.5 5 ns

from LOW to Z

tDJ LVDS Data Jitter, VID = 300 mV, PRBS = 223 - 1, 80 135 ps

Deterministic VIC = 1.2V at 800 Mbps

tRJ LVDS Clock Jitter, VID = 300 mV, 1.9 3.5 ps

Random (RMS) VIC = 1.2V at 400 MHz

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FIN1108 • FIN1108T (Preliminary)

FIGURE 4. AC Waveform

Note A: All LVTTL input pulses have frequency = 10MHz, tR or tF < = 2 ns

Note B: CL includes all probe and jig capacitances

FIGURE 5. Differential Driver Enable and Disable Circuit

FIGURE 6. Enable and Disable AC Waveforms

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FIN1108 • FIN1108T (Preliminar y) LVDS 8 Port High Speed Repeater

48-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD48

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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