-20 V +25 V
-7V +12 V
SUPER485
RS485
-20V -15V -10V -5V 0 5V 10V 15V 20V 25V
0.1
1
10
100
HVD20
HVD23
HVD24
HVD21
HVD22
SignalingRate-Mbps
10 100 1000
CableLength-m
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
Extended Common-Mode RS-485 Transceivers
Check for Samples: SN65HVD20,SN65HVD21,SN65HVD22,SN65HVD23,SN65HVD24
1FEATURES DESCRIPTION
•Common-Mode Voltage Range (–20 V to 25 V) The transceivers in the HVD2x family offer
More Than Doubles TIA/EIA-485 Requirement performance far exceeding typical RS−485 devices.
•Receiver Equalization Extends Cable Length, In addition to meeting all requirements of the
Signaling Rate (HVD23, HVD24) TIA/EIA−485−A standard, the HVD2x family operates
•Reduced Unit-Load for up to 256 Nodes over an extended range of common-mode voltage,
and has features such as high ESD protection, wide
•Bus I/O Protection to Over 16-kV HBM receiver hysteresis, and failsafe operation. This family
•Failsafe Receiver for Open-Circuit, of devices is ideally suited for long-cable networks,
Short-Circuit and Idle-Bus Conditions and other applications where the environment is too
•Low Standby Supply Current 1-µA Max harsh for ordinary transceivers.
•More Than 100 mV Receiver Hysteresis These devices are designed for bidirectional data
transmission on multipoint twisted-pair cables.
APPLICATIONS Example applications are digital motor controllers,
remote sensors and terminals, industrial process
•Long Cable Solutions control, security stations, and environmental control
–Factory Automation systems.
–Security Networks These devices combine a 3-state differential driver
–Building HVAC and a differential receiver, which operate from a
single 5-V power supply. The driver differential
•Severe Electrical Environments outputs and the receiver differential inputs are
–Electrical Power Inverters connected internally to form a differential bus port
–Industrial Drives that offers minimum loading to the bus. This port
features an extended common-mode voltage range
–Avionics making the device suitable for multipoint applications
over long cable runs.
HVD2x APPLICATION SPACE
HVD2x Devices Operate Over a Wider
Common-Mode Voltage Range
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The ‘HVD20 provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64 nodes.
The ‘HVD21 allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew
rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise
emissions.
The ‘HVD22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and
for improved signal quality with long stubs. Up to 256 ‘HVD22 nodes can be connected at signaling rates up to
500 kbps.
The ‘HVD23 implements receiver equalization technology for improved jitter performance on differential bus
applications with data rates up to 25 Mbps at cable lengths up to 160 meters.
The ‘HVD24 implements receiver equalization technology for improved jitter performance on differential bus
applications with data rates in the range of 1 Mbps to 10 Mbps at cable lengths up to 1000 meters.
The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of
the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence
of any active transmitters on the bus. This feature prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling.
The SN65HVD2X devices are characterized for operation over the temperature range of –40°C to 85°C.
PRODUCT SELECTION GUIDE
PART NUMBERS CABLE LENGTH AND SIGNALING RATE(1) NODES MARKING
D: VP20
SN65HVD20 Up to 50 m at 25 Mbps Up to 64 P: 65HVD20
D: VP21
SN65HVD21 Up to 150 m at 5 Mbps (with slew rate limit) Up to 256 P: 65HVD21
D: VP22
SN65HVD22 Up to1200 m at 500 kbps (with slew rate limit) Up to 256 P: 65HVD22
D: VP23
SN65HVD23 Up to 160 m at 25 Mbps (with receiver equalization) Up to 64 P: 65HVD23
D: VP24
SN65HVD24 Up to 500 m at 3 Mbps (with receiver equalization) Up to 256 P: 65HVD24
(1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.
AVAILABLE OPTIONS
PLASTIC THROUGH-HOLE PLASTIC SMALL-OUTLINE(1)
P−PACKAGE D−PACKAGE
(JEDEC MS-001) (JEDEC MS-012)
SN65HVD20P SN65HVD20D
SN65HVD21P SN65HVD21D
SN65HVD22P SN65HVD22D
SN65HVD23P SN65HVD23D
SN65HVD24P SN65HVD24D
(1) Add R suffix for taped and reeled carriers.
2Submit Documentation Feedback Copyright ©2002–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
Table 1. DRIVER FUNCTION TABLE
HVD20, HVD21, HVD22 HVD23, HVD24
INPUT ENABLE OUTPUTS INPUT ENABLE OUTPUTS
D D
DE A B DE A B
H H H L H H H L
L H L H L H L H
X L Z Z X L Z Z
X OPEN Z Z X OPEN Z Z
OPEN H H L OPEN H L H
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
Table 2. RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT ENABLE OUTPUT
VID = (VA–VB) RE R
0.2 V ≤VID L H
–0.2 V <VID <0.2 V L H (see Note (1))
VID ≤ –0.2 V L L
X H Z
X OPEN Z
Open circuit L H
Short Circuit L H
Idle (terminated) bus L H
H = high level, L= low level, Z = high impedance (off)
(1) If the differential input VID remains within the transition range for
more than 250 µs, the integrated failsafe circuitry detects a bus fault,
and set the receiver output to a high state. See Figure 15.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
SN65HVD2X
Supply voltage(2), VCC –0.5 V to 7 V
Voltage at any bus I/O terminal –27 V to 27 V
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 16) –60 V to 60 V
Voltage input at any D, DE or RE terminal –0.5 V to VCC+ 0.5 V
Receiver output current, IO–10 mA to 10 mA
A, B, GND 16 kV
Human Body Model(3) All pins 5 kV
Electrostatic
dischargeElectrostatic discharge Charged-Device Model(4) All pins 1.5 kV
Machine Model(5) All pins 200 V
Continuous total power dissipation See Thermal Table
Junction temperature, TJ150°C
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5 5.5 V
Voltage at any bus I/O terminal A, B −20 25 V
High-level input voltage, VIH 2 VCC
D, DE, RE V
Low-level input voltage, VIL 0 0.8
Differential input voltage, VID A with respect to B −25 25 V
Driver −110 110
Output current mA
Receiver −8 8
Operating free-air temperature, TA(1) −40 85 °C
Junction temperature, TJ−40 130 °C
(1) Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions TYP(1
PARAMETER TEST CONDITIONS MIN MAX UNIT
)
VIK Input clamp voltage II=−18 mA –1.5 0.75 V
VOOpen-circuit output voltage A or B, No load 0 VCC V
No load (open circuit) 3.3 4.2 VCC
|VOD(SS)| Steady-state differential output voltage RL= 54 Ω, See Figure 1 1.8 2.5 V
With common-mode loading, See Figure 2 1.8
Change in steady-state differential
Δ|VOD(SS)| See Figure 1 and Figure 3 –0.1 0.1 V
output voltage between logic states
Steady-state common-mode output
VOC(SS) See Figure 1 2.1 2.5 2.9 V
voltage
Change in steady-state common-mode
∆VOC(SS) See Figure 1 and Figure 4 –0.1 0.1 V
output voltage, VOC(H) –VOC(L)
Peak-to-peak common-mode output
VOC(PP) RL= 54 Ω, CL= 50 pF, See Figure 1 and Figure 4 0.35 V
voltage, VOC(MAX) –VOC(MIN)
Differential output voltage over and
VOD(RING) RL= 54 Ω, CL= 50 pF, See Figure 5 10%
under shoot
IIInput current D, DE –100 100 µA
HVD20, HVD23 -400 500
VO<= -7 V to 12 V, Other input = 0 V HVD21, HVD22, HVD24 -100 125
Output current with power off.
IOµA
High impedance state output current. HVD20, HVD23 -800 1000
VO<= -20 V to 25 V, Other input = 0 V HVD21, HVD22, HVD24 -200 250
IOS Short-circuit output current VO=–20 V to 25 V, See Figure 9 –250 250 mA
COD Differential output capacitance 20 pF
(1) All typical values are at VCC = 5 V and 25°C.
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Differential output propagation delay, low-to-high HVD20, HVD23 6 10 20
RL= 54 Ω,
CL= 50 pF, HVD21, HVD24 20 32 60 ns
tPHL Differential output propagation delay, high-to-low See Figure 3 HVD22 160 280 500
trDifferential output rise time HVD20, HVD23 2 6 12
RL= 54 Ω,
CL= 50 pF, HVD21, HVD24 20 40 60 ns
tfDifferential output fall time See Figure 3 HVD22 200 400 600
tPZH Propagation delay time, high-impedance-to-high-level output HVD20, HVD23 40
RE at 0 V, HVD21, HVD24 100 ns
See Figure 6
tPHZ Propagation delay time, high-level output-to-high-impedance HVD22 300
HVD20, HVD23 40
tPZL Propagation delay time, high-impedance-to-high-level output RE at 0 V, HVD21, HVD24 100 ns
See Figure 7
tPLZ Propagation delay time, high-level output-to-high-impedance HVD22 300
td(standby) Time from an active differential output to standby 2 µs
RE at VCC, See Figure 8
td(wake) Wake-up time from standby to an active differential output 8 µs
HVD20, HVD23 2
tsk(p ) Pulse skew | tPLH –tPHL| HVD21, HVD24 6 ns
HVD22 50
(1) All typical values are at VCC = 5 V and 25°C
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT(+) Positive-going differential input voltage threshold VO= 2.4 V, IO=–8 mA 60 200
See Figure 10 mV
VIT(–)Negative-going differential input voltage threshold VO= 0.4 V, IO= 8 mA –200 –60
VHYS Hysteresis voltage (VIT+ –VIT–) 100 130 mV
VCM = −7 V to 12 V 40 120 200
Positive-going differential input failsafe voltage
VIT(F+) See Figure 15 mV
threshold VCM = −20 V to 25 V 120 250
VCM = −7 V to 12 V –200 –120 −40
Negative-going differential input failsafe voltage
VIT(F–)See Figure 15 mV
threshold VCM = −20 V to 25 V –250 –120
VIK Input clamp voltage II=–18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH =−8 mA, See Figure 11 4 V
VOL Low-level output voltage VID =–200 mV, IOL = 8 mA, See Figure 11 0.4 V
HVD20, HVD23 –400 500
VI=–7 to 12 V,
Other input = 0 V HVD21, HVD22, HVD24 –100 125
II(BUS) Bus input current (power on or power off) µA
HVD20, HVD23 –800 1000
VI=−20 to 25 V,
Other input = 0 V HVD21, HVD22, HVD24 –200 250
IIInput current RE –100 100 µA
HVD20, HVD23 24
RIInput resistanceInput resistance kΩ
HVD21, HVD22, HVD24 96
CID Differential input capacitance 20 pF
VID = 0.5 + 0.4 sine (2π × 1.5 ×106t)
(1) All typical values are at 25°C.
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output HVD20, HVD23 16 35 ns
See Figure 11 HVD21, HVD22,
tPHL Propagation delay time high-to low level output 25 50
HVD24
tr Receiver output rise time See Figure 11 2 4 ns
tfReceiver output fall time
tPZH Receiver output enable time to high level 90 120 ns
See Figure 12
tPHZ Receiver output disable time from high level 16 35
tPZL Receiver output enable time to low level 90 120 ns
See Figure 13
tPLZ Receiver output disable time from low level 16 35
tr(standby) Time from an active receiver output to standby 2 µs
See Figure 14, DE at 0 V
tr(wake) Wake-up time from standby to an active receiver output 8
tsk(p) Pulse skew |tPLH –tPHL| 5
tp(set) Delay time, bus fail to failsafe set 250 350 µs
See Figure 15, pulse rate = 1 kHz
tp(reset) Delay time, bus recovery to failsafe reset 50 ns
RECEIVER EQUALIZATION CHARACTERISTICS(1)
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
0 m HVD23 2 ns
HVD20 6
100 m ns
HVD23 3
25 Mbps HVD20 15
150 m ns
HVD23 4
HVD20 27
200 m ns
HVD23 8
HVD20 22
200 m ns
HVD23 8
Peudo-random NRZ code with a bit HVD20 34
10 Mbps 250 m ns
Peak-to-peak pattern length of 216 –1, Beldon
tj(pp) HVD23 15
eye-pattern jitter 3105A cable, HVD20 49
See Figure 27 300 m ns
HVD23 27
HVD21 128
5 Mbps 500 m ns
HVD24 18
HVD20 93
HVD21 103
3 Mbps 500 m ns
HVD23 90
HVD24 16
HVD21 216
1 Mbps 1000 m ns
HVD24 62
(1) The HVD20 and HVD21 do not have receiver equalization, but are specified for comparison.
(2) All typical values are at VCC = 5 V, and temperature = 25°C.
6Submit Documentation Feedback Copyright ©2002–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HVD20 6 9
HVD21 8 12
HVD22 6 9
Driver enabled (DE at VCC), Receiver enabled (RE at 0 V), HVD23 7 11 mA
No load, VI= 0 V or VCC HVD24 10 14
HVD20 5 8
HVD21 7 11
HVD22 5 8
Supply
ICC Driver enabled (DE at VCC), Receiver disabled (RE at VCC),
current HVD23 5 9 mA
No load, VI= 0 V or VCC HVD24 8 12
HVD20 4 7
HVD21 5 8
Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V), No load HVD22 4 7 mA
HVD23 4.5 9
HVD24 5.5 10
Driver disabled (DE at 0 V), Receiver disabled (RE at VCC) D open All HVD2x 1 µA
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
9 V
1 kΩ
100 kΩ
Input
VCC
RE Inputs
9 V
1 kΩ
100 kΩ
Input
VCC
DE Input
29 V
R3 R1
R2
Input
A Input
29 V
R3 R1
R2
Input
B Input
29 V
VCC
A and B Outputs
9 V
VCC
R Output
5Ω
Output
VCC
VCC
Output
D Inputs (HVD20, 21, 22) D Inputs (HVD23, 24)
29 V
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
R1/R2 R3
HVD20, 23 9 kΩ45 kΩ
HVD21, 22, 24 36 kΩ180 kΩ
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
II
IO
IO
VOD 50pF
27 Ω
27 Ω
VOC
0Vor3V
IO
IO
VOD 60 Ω
VTEST
0 V or 3 V
375 Ω
375 Ω
VTEST = -20 V to 25 V
VOD
50 Ω
RL=54 Ω
CL=50pF
Signal
Generator
1.5V 1.5V
3V
0V
tPLH tPHL
VOD(H)
VOD(L)
90%
0V
10%
trtf
INPUT
OUTPUT
VOC
50 Ω
Signal
Generator
A
B
27 Ω
27 Ω
50 pF
D
VA
VB
VOC
VOC(PP) ∆VOC(SS)
≈-3.25 V
≈-1.75 V
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION
NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator
characteristics: rise and fall time <6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 Ω(unless otherwise
specified).
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
Figure 3. Driver Switching Test Circuit and Waveforms
Figure 4. Driver VOC Test Circuit and Waveforms
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
VOD(PP)
VOD(RING)
VOD(RING)
VOD(SS)
0 V Differential
VOD(SS)
50 Ω
CL=50pF
Signal
Generator
DE
D
0Vor3V
0 V if Testing A Output
3 V if Testing B Output
RL= 110 Ω
Output
S1
tPZL tPLZ
0.5V
DE
Output
1.5V 1.5V
2.5V
3V
0V
5V
VOL
5V
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
VOD(H) and VOD(L) steady state values.
Figure 5. VOD(RING) Waveform and Definitions
Figure 6. Driver Enable/Disable Test, High Output
Figure 7. Driver Enable/Disable Test, Low Output
10 Submit Documentation Feedback Copyright ©2002–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
VOD
RL=54 ΩCL=50pF
50 Ω
Signal
Generator
DE
D
0Vor3V
A
B
3V
1.5V
0V
0.2V
1.5V
td(Wake)
td(Standby)
DE
VOD
Voltage
Source
IOS
VO
IO
VO
VID
50 Ω
Signal
Generator
CL=15pF
50 Ω
Signal
Generator
A
VID
BR
IO
VO
50%
90%
10%
1.5V
0V
VOH
VOL
tPLH tPHL
trtf
InputB
Input A
Output 1.5V
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Driver Standby/Wake Test Circuit and Waveforms
Figure 9. Driver Short-Circuit Test
Figure 10. Receiver DC Parameter Definitions
Figure 11. Receiver Switching Test Circuit and Waveforms
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
50 Ω
Signal
Generator
RE
B
A
54 Ω
CL= 15 pF
R1 kΩ
0 V
VCC
VCC
D
DE
RE
R
1.5 V
tPZH tPHZ
3 V
0 V
VOH
VOH -0.5 V
GND
1.5 V
50 Ω
Signal
Generator
RE
B
A
54 Ω
CL=15pF
R1kΩ
5V
0V
VCC
D
DE
RE
R
1.5V
tPZL tPLZ
3V
0V
VCC
VOL +0.5V
1.5V
VOL
1.5 V
50 Ω
Signal
Generator
RE
B
A
CL= 15 pF
R
1 kΩ
Switch Down for V(A) = 1.5 V,
Switch Up for V(A) = -1.5 V
VCC
1.5 V or
-1.5 V
tr(Wake) tr(Standby)
RE
5 V
0 V
1.5 V VOH 0.5 V
VOL +0.5 V
3 V
0 V
VOH
VOL
R
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 14. Receiver Standby and Wake Test Circuit and Waveforms
12 Submit Documentation Feedback Copyright ©2002–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
Bus Data Valid Region
Bus Data
Transition Region
Bus Data Valid Region
tp(SET) tp(RESET)
200 mV
-40 mV
-200 mV
-1.5 V
VOH
VOL
1.5 V
VID
R
Pulse Generator,
15 msDuration,
1%DutyCycle
100 ΩVTEST
0V
15 ms1.5ms VTEST
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D or P PACKAGE
(TOP VIEW)
6
7
A
B
3
4
2
1
DE
D
RE
R
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
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SLLS552E –DECEMBER 2002–REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 15. Receiver Active Failsafe Definitions and Waveforms
Figure 16. Test Circuit and Waveforms, Transient Overvoltage Test
PIN ASSIGNMENTS
LOGIC DIAGRAM
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
THERMAL INFORMATION SN65HVD2x
THERMAL METRIC(1) SOIC (D) PDIP (P) UNITS
8 PINS PINS
θJA Junction-to-ambient thermal resistance(2) 78.1 52.5
θJC(top) Junction-to-case(top) thermal resistance (3) 56.5 57.6
θJB Junction-to-board thermal resistance (4) 50.4 38.6 °C/W
ψJT Junction-to-top characterization parameter (5) 4.1 19.1
ψJB Junction-to-board characterization parameter (6) 32.6 31.9
θJC(bottom) Junction-to-case(bottom) thermal resistance (7) nA n/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
POWER DISSIPATION
PARAMETERS TEST CONDITIONS VALUE UNIT
HVD20 VCC = 5 V, TJ= 25°C, 25 Mbps 295
RL= 54 Ω, CL= 50 pF (driver),
HVD21 5 Mbps 260
CL= 15 pF (receiver),
Typical HVD22 500 kbps 233 mW
50% Duty cycle square-wave signal,
Driver and receiver enabled
HVD23 25 Mbps 302
HVD24 5 Mbps 267
Device Power
dissipation, PDHVD20 VCC = 5.5 V, TJ= 125°C, 25 Mbps 408
RL= 54 Ω, CL= 50 pF,
HVD21 5 Mbps 342
CL= 15 pF (receiver),
Worst case HVD22 500 kbps 300 mW
50% Duty cycle square-wave signal,
Driver and receiver enabled
HVD23 25 Mbps 417
HVD24 5 Mbps 352
Thermal shut down junction temperature, TSD 170 °C
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
600
400
200
0
200
400
600
VCC =0V
VCC =5V
Bus Pin Voltage - V
BusPinCurrent- Am
DE=0V
-30 -20 -10 0 10 20 30
150
100
50
0
50
100
150
VCC =0V
VCC =5V
BusPinCurrent- Am
DE=0V
Bus Pin Voltage - V
-30 -20 -10 0 10 20 30
40
45
50
55
60
65
70
75
HVD22 HVD21
HVD20
VCC =5V,
DE=RE =VCC,
LOAD=54 Ω,50pF
SignalingRate-Mbps
I -SupplyCurrent-mA
CC
0.1 110 100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VCC =5.5V
VCC =5V
VCC =4.5V
I -DriverLoadCurrent-mA
L
V -DriverDifferentialOutputVoltage-V
OD
0 10 20 30 40 50 60 70 80
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
TYPICAL CHARACTERISTICS
HVD20, HVD23 HVD21, HVD22, HVD24
BUS PIN CURRENT BUS PIN CURRENT
vs vs
BUS PIN VOLTAGE BUS PIN VOLTAGE
Figure 17. Figure 18.
SUPPLY CURRENT DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs vs
SIGNALING RATE DRIVER LOAD CURRENT
Figure 19. Figure 20.
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
0
5
10
15
20
25
30
HVD20 = 25 Mbps
CableLength-m
HVD23=25Mbps
VCC =5V,
TA=25°C,
VIC =2.5V,
Cable:Belden3105A
100 120 140 160 180 200
Peak-to-PeakJitter-ns
1
0
1
2
3
4
5
6
VCM =25V
VCM =0V
VCM =20V
VCM =25V
VCM =0V
VCM =20V
V - Differential Input Voltage - V
ID
VIT(-) VIT(+)
V -ReceiverOutputVoltage-V
O
-0.2 -0.1 00.1 0.2
10
30
50
70
90
110
130
HVD21:500mCable
SignalingRate-Mbps
VCC =5V,
TA=25°C,
VIC =2.5V,
Cable:Belden3105A
HVD24:500mCable
Peak-to-PeakJitter-ns
3 3.5 4 4.5 5
0
10
20
30
40
50
60
70
HVD21=10Mbps
HVD20=10Mbps
HVD23=10Mbps
HVD24=10Mbps
VCC =5V,
TA=25°C,
VIC =2.5V,
Cable:Belden3105A
CableLength-m
200 220 240 260 280 300
Peak-to-PeakJitter-ns
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)HVD20, HVD23
RECEIVER OUTPUT VOLTAGE PEAK-TO-PEAK JITTER
vs vs
DIFFERENTAL INPUT VOLATGE CABLE LENGTH
Figure 21. Figure 22.
HVD20, HVD21, HVD23, HVD24 HVD20, HVD23
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER
vs vs
CABLE LENGTH SIGNALING RATE
Figure 23. Figure 24.
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
B
A
6
7
R
2
1
RE
DE
D
3
4
Active
Filters
+
+
120mV
120mV
Timer
250 sm
(VA
-VB):NotHigh
(VA
-V B):NotLow
BusInput
Invalid
Slew
Rate
Control
STANDBY
-
-
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
APPLICATION INFORMATION
THEORY OF OPERATION
The HVD2x family of devices integrates a differential receiver and differential driver with additional features for
improved performance in electrically-noisy, long-cable, or other fault-intolerant applications.
The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps
reject spurious noise signals which would otherwise cause false changes in the receiver output state.
Slew rate limiting on the driver outputs (SN65HVD21, 22, and 24) reduces the high-frequency content of signal
edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and
the main bus line. Designers should consider the maximum signaling rate and cable length required for a specific
application, and choose the transceiver best matching those requirements.
When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When
DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D
input.s
When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state.
When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus
inputs on the A and B pins.
If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including
auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This reduces
power consumption to less than 5µW. When either enable input is asserted, the circuitry again becomes active.
In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to
implement an active receiver failsafe feature. These components determine whether the differential bus signal is
valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the
differential input remains within the transition range for more than 250 microseconds, the timer expires and set
the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output
reflects the valid bus state, and the timer is reset.
Figure 25. Function Block Diagram
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
H(s) =k0(1–k )
1
k1p1(1–k )
2
k2p2k3p3
k0
(DC
loss)
p1
(MHz) k1 p2
(MHz) k2 p3
(MHz) k3
Similar to 160m of Belden 3105A 0.95 0.25 0.3 3.5 0.5 15 1
Similarto250mofBelden3105A 0.9 0.25 0.4 3.5 0.7 12 1
Similarto500mofBelden3105A 0.8 0.25 0.6 2.2 1 8 1
Similarto1000mofBelden3105A 0.6 0.3 1 3 1 6 1
H(s)
Signal
Generator
+(s+p )
1
+(s+p )
2
(1–k )
3+
(s+p )
3
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
Figure 26. HVD22 Receiver Operation With 20-V Offset on Input Signal
Figure 27. Cable Attenuation Model for Jitter Measurements
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552E –DECEMBER 2002–REVISED MAY 2010
INTEGRATED RECEIVER EQUALIZATION USING THE HVD23
Figure 28 illustrates the benefits of integrated receiver equalization as implemented in the HVD23 transceiver. In
this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden
3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero
(NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver inputs (after the
cable attenuation). Channel 2 (bottom) shows the output of the receiver.
Figure 28. HVD23 Receiver Performance at 25 Mbps Over 150 Meter Cable
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
www.ti.com
INTEGRATED RECEIVER EQUALIZATION USING THE HVD24
Figure 29 illustrates the benefits of integrated receiver equalization as implemented in the HVD24 transceiver. In
this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden
3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero
(NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle) shows the eye-pattern
of the differential voltage at the receiver inputs (after the cable attenuation). Channel 3 (bottom) shows the output
of the receiver.
Figure 29. HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
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SLLS552E –DECEMBER 2002–REVISED MAY 2010
NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS
The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If the
maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten
compensates for the cable. However, this means that both signal and noise are amplified. Therefore, the receiver
with higher gain is more sensitive to noise and it is important to minimize differential noise coupling to the
equalized receiver.
Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the
differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to
ground of the lines must differ.
For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is
approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is accomplished
by matching the lumped capacitance of each.
The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material,
distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match
each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines
balanced and less susceptible to differential noise coupling.
Another source of differential noise is from near-field coupling. In this situation, an assumption of equal
noise-source impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from a
nearby signal is coupled to one line of the differential pair. Minimization of this differential noise is accomplished
by keeping the signal pair close together and physical separation from high-voltage, high-current, or
high-frequency signals.
In summary, follow these guidelines in board layout for keeping differential noise to a minimum.
•Keep the differential input traces short.
•Match the length, physical dimensions, and routing of each line of the pair.
•Keep the lines close together.
•Match components connected to each line.
•Separate the inputs from high-voltage, high-frequency, or high-current signals.
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002–REVISED MAY 2010
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TEST MODE DRIVER DISABLE
If the input signal to the D pin is such that:
1. the signal has signaling rate above 4 Mbps (for the ‘HVD21 and ‘HVD24)
2. the signal has signaling rate above 6 Mbps (for the ‘HVD20 and ‘HVD23)
3. the signal has average amplitude between 1.2 V and 1.6 V (1.4 V ±200 mV)
4. the average signal amplitude remains in this range for 100 µsec or longer,
then the driver may activate a test-mode during which the driver outputs are temporarily disabled. This can cause
loss of transmission of data during the period that the device is in the test-mode. The driver will be re-enabled
and resume normal operation whenever the above conditions are not true. The device is not damaged by this
test mode.
Although rare, there are combinations of specific voltage levels and input data patterns within the operating
conditions of the HVD2x family which may lead to a temporary state where the driver outputs are disabled for a
period of time.
Observations:
1. The conditions for inadvertently entering the test mode are dependent on the levels, duration, and duty cycle
of the logic signal input to the D pin. Operating input levels are specified as greater than 2 V for a logic HIGH
input, and less than 0.8V for a logic LOW input. Therefore, a valid steady-state logic input will not cause the
device to activate the test mode
2. Only input signals with frequency content above 2 MHz (4 Mbps) have a possibility of activating the test
mode. Therefore, this issue should not affect the normal operation of the HVD22 (500 kbps).
3. For operating signaling rates of 4 Mbps (or above), the conditions stated above must remain true over a
period of: 4 Mbps x 100 µsec = 400 bits. Therefore, a normal short message will not inadvertently activate
the test model
4. One example of an input signal which may cause the test mode to activate is a clock signal with frequency 3
MHz and 50% duty cycle (symmetric HIGH and LOW half-cycles) with logic HIGH levels of 2.4 V and logic
LOW levels of 0.4 V. This signal applied to the D pin as a driver input would meet the criteria listed above,
and might cause the test-mode to activate, which would disable the driver. Note that this example situation
might occur if the clock signal were generated by a microcontroller or logic chip with a 2.7 V-supply.
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
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SLLS552E –DECEMBER 2002–REVISED MAY 2010
REVISION HISTORY
Changes from Original (December 2002) to Revision A Page
•Changed tPZH, tPHZ, tPZL, and tPLZ - From a MAX value of 120 To include TYP and MAX values for each entry
(RECEIVER SWITCHING CHARACTERISTICS table) ........................................................................................................ 6
Changes from Revision A (March 2003) to Revision B Page
•Added VIK TYP Value of 0.75V (DRIVER ELECTRICAL CHARACTERISTICS table) ......................................................... 4
•Deleted VIT(F+) - VCM = −20 V to 25 V MIN value (RECEIVER ELECTRICAL CHARACTERISTICS table) ....................... 5
•Added RECEIVER EQUALIZATION CHARACTERISTICS table ......................................................................................... 6
•Changed A Input circuit in the EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS ........................................ 8
•Added Figure 22,Figure 23, and Figure 24 to the TYPICAL CHARACTERISTICS .......................................................... 15
•Changed the INTEGRATED RECEIVER EQUALIZATION USING THE HVD23 section .................................................. 19
•Changed the INTEGRATED RECEIVER EQUALIZATION USING THE HVD24 section .................................................. 20
Changes from Revision B (June 2003) to Revision C Page
•Added the THERMAL CHARACTERISTICS table ............................................................................................................. 14
•Added the THEORY OF OPERATION section ................................................................................................................... 17
•Added the NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS section ............................................................. 21
Changes from Revision C (September 2003) to Revision D Page
•Added Conditions note to the ABSOLUTE MAXIMUM RATINGS table "over operating free-air temperature range
(unless otherwise noted)"..................................................................................................................................................... 3
•Deleted Storage temperature, Tstg from the ABSOLUTE MAXIMUM RATINGS table ......................................................... 3
•Added Receiver output current, IOto the ABSOLUTE MAXIMUM RATINGS table ............................................................. 3
Changes from Revision D (April 2005) to Revision E Page
•Changed IO- Added test condition and values per device number (DRIVER ELECTRICAL CHARACTERISTICS
table) ..................................................................................................................................................................................... 4
•Replaced the Dissipation Rating table with the THERMAL INFORMATION table ............................................................. 14
•Changed the THERMAL CHARACTERISTICS table to POWER DISSIPATION table ...................................................... 14
•Added the TEST MODE DRIVER DISABLE section .......................................................................................................... 22
Copyright ©2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD20D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD20DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD20DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD20DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD20P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD20PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD21D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD21DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD21DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD21DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD21P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD21PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD22D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD22DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD22DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD22DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD22P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD22PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD23D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD23DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD23DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD23DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD23P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD23PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD24D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2010
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD24DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD24DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD24DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD24P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD24PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD20DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD21DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD22DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD23DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD24DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-May-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD20DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD21DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD22DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD23DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD24DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 4-May-2010
Pack Materials-Page 2
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